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Text File | 1996-09-12 | 42.9 KB | 793 lines

[10. Configurability] EMBEDDED BIOS 4.0 CONFIGURABILITY ════════════════════════════════════════════════════════════════════════ Embedded BIOS is the most configurable BIOS in the industry. With over 330 configuration options organized into groups for easy OEM adaptation, Embedded BIOS can be configured to virtually any hardware platform that you can design, around an x86-compatible CPU. The key to Embedded BIOS 4.0 configurability is its plug-and-play personality modules for CPUs, Chipsets, and Board-level designs. We've done the work for the important CPUs and chipsets, and even the most common evaluation boards produced by our hardware partners. Our OEMs using a reference design such as the EXPLR1, EXPLR2, or AMD eval board can leverage our existing work without writing a single line of code. Options are available in addition to our basic architectural modules that allow individual features to be enabled or disabled, and various values such as COM port addresses to be fine-tuned. Embedded BIOS offers high performance, low latency, a full set of ROM tools, a standard ROM disk, a high-memory ROM disk, a REMOTE disk, a FLASH disk for read/write Flash array support, a built-in MINI-DOS that runs directly out of ROM, and an integrated disassembling debugger to get your system up and going quickly. Despite its enormous set of configuration options, Embedded BIOS is actually easy to configure. In fact, THE AVERAGE BIOS ADAPTATION TAKES ONLY 15 MINUTES TO PERFORM. How can this be? Because we've already written all the software codepaths in such a way that you can simply select the features and hardware you want, and a single command-- GSMAKE, builds the BIOS for you. EMBEDDED BIOS BOOT OPTIONS: ■ Boot out of ROM with Embedded DOS-ROM ■ Boot from Flash disk ■ Boot from low-memory ROM disk ■ Boot from extended-memory ROM disk ■ Boot from a REMOTE disk ■ Boot from FLOPPY/IDE/ATA disks MODULAR CONSTRUCTION LETS YOU INCLUDE ONLY NECESSARY BIOS FUNCTIONS: Embedded BIOS includes over 100,000 lines of MASM/TASM-compatible source code in over 60 modules. With the configuration options in OPTIONS.INC and CONFIG.INC (shown later) you can easily configure the core system BIOS without spending time reviewing how the code works. Also included is a BINARY CONFIGURATION PROGRAM (BCP) that allows you to tune a given binary version of the BIOS for your specific needs. ╔══════════════════════════════════════════════════════════════════════╗ ║ There are over 330 configuration options supported by Embedded BIOS. ║ ║ Here's a list of the actual configuration files that you will use to ║ ║ build a custom BIOS for your hardware (OPTIONS.INC & CONFIG.INC): ║ ╚══════════════════════EMBEDDED BIOS CONFIGURATION═════════════════════╝ ; Version of this BIOS. BIOS_MAJOR_VERSION = 4 BIOS_MINOR_VERSION = 0 ; Size of the BIOS in kilobytes. This is the size of the BIOS image, ; packed towards the top of the 64KB output file called BIOS.ABS. If ; you select 64, then the entire BIOS.ABS is used to store the BIOS. ; If you select 48, then only the top 48KB of the BIOS.ABS will be used; ; the bottom 16KB would be ffh's. Similarly, you can create a small ; BIOS by setting this parameter to something low, like 8 (KB). Odd ; sizes, such as 23, are also possible. In all cases, a full 64KB of ; data is written to BIOS.ABS; this parameter only defines how much of ; that image (towards the top) is used to store the BIOS itself. OPTION_BIOS_KBSIZE = 64 ; Configuration options selectable by the OEM. OPTION_SUPPORT_PCODE = 0 ; enable PCODE interpreter. OPTION_SUPPORT_SETUP = 1 ; build SETUP code. OPTION_SUPPORT_CONFIGBOX = 0 ; build Configuration Box code. OPTION_SUPPORT_POSTCODES= 0 ; support POST codes to progress port. OPTION_SUPPORT_POSTCODES_COM= 0 ; support POST codes thru serial port. OPTION_SUPPORT_POSTMSGS = 1 ; support POST messages to video. OPTION_SUPPORT_POWERON_DELAY= 1 ; support POST delay to stablize power supply. OPTION_SUPPORT_DEBUGGER = 1 ; build ROM-resident debugger code. OPTION_SUPPORT_SHADOW = 0 ; build shadowing logic. OPTION_SUPPORT_CACHE = 0 ; build cache logic. OPTION_SUPPORT_8250 = 1 ; build 8250 UART control code. OPTION_SUPPORT_8254 = 1 ; build 8253/8254 timer control code. OPTION_SUPPORT_8255 = 0 ; build 8255 PIO control code. OPTION_SUPPORT_PORT_B = 0 ; build PORT B init/control code. OPTION_SUPPORT_8259 = 1 ; build 8259 interrupt controller code. OPTION_SUPPORT_8259_2 = 1 ; build second 8259 at PC/AT address. OPTION_SUPPORT_8237 = 0 ; build 8237A DMA controller code. OPTION_SUPPORT_8237_2 = 0 ; build second 8237A at PC/AT address. OPTION_SUPPORT_8042 = 1 ; build 8042 keyboard controller code. OPTION_SUPPORT_CMOS = 1 ; build AT-style CMOS control code. OPTION_SUPPORT_NPX = 0 ; build numeric coprocessor code. OPTION_SUPPORT_V25 = 0 ; initialize V25 processor before POST. OPTION_SUPPORT_8680 = 0 ; build code to save C&T vector 1fh. OPTION_SUPPORT_VIRTIO = 0 ; build virtual I/O port code. OPTION_SUPPORT_XT_NMI = 0 ; build PC/XT NMI control code. OPTION_SUPPORT_VIDEO = 1 ; build code to support mono/color/ega. OPTION_SUPPORT_KEYBOARD = 1 ; build code to support PC/XT or PC/AT kbd. OPTION_SUPPORT_TESTBASEMEM = 1 ; build code to test base xxKB of memory. OPTION_SUPPORT_PAGEREG = 0 ; build code for PC/XT, PC/AT page registers. OPTION_SUPPORT_XTEXPANSION = 0 ; build code to enable PC/XT expansion unit. OPTION_SUPPORT_IDE = 0 ; build code to support IDE drives. OPTION_SUPPORT_FLOPPY = 0 ; build code to support floppy drives. OPTION_SUPPORT_SCT = 1 ; build system configuration table. OPTION_SUPPORT_TESTPAGEREG = 0 ; build code to test page regs (PC/AT only). OPTION_SUPPORT_PROTECT_MODE = 1 ; build code to support protected mode. OPTION_SUPPORT_LCD = 0 ; build code to support LCD messages. OPTION_SUPPORT_SERIAL = 1 ; build code to support serial I/O. OPTION_SUPPORT_PARALLEL = 1 ; build code to support parallel BIOS. OPTION_SUPPORT_ROM_EXTENSIONS = 0 ; build code to support ROM extensions. OPTION_SUPPORT_VIDEO_BOARDS = 0 ; build code to support video boards. OPTION_SUPPORT_REMOTE_DISK = 0 ; build code to support serial remote disk. OPTION_SUPPORT_ROM_DISK = 1 ; build code to support built-in ROM disk. OPTION_SUPPORT_SOUND = 0 ; build code to beep/click the speaker. OPTION_SUPPORT_DEVICECALLS = 1 ; build code to issue INT 15h's for spinloops. OPTION_SUPPORT_TIMEBIOS = 1 ; build code to support the time BIOS. OPTION_SUPPORT_CHIPSET = 0 ; build code to support chipset programming. OPTION_SUPPORT_POWERMAN = 0 ; build code to support power management. OPTION_SUPPORT_WATCHDOG = 0 ; build code to support a watchdog timer. OPTION_SUPPORT_SOFT_ERR = 1 ; build code to support soft error messages. OPTION_SUPPORT_TIMER_DEBUG = 0 ; build code to update video screen @ 18.2Hz. OPTION_SUPPORT_ROM_BASIC = 0 ; build code to call ROM E000h if no boot device. OPTION_SUPPORT_RAM_DISK = 1 ; build code to support ext mem RAM disk. OPTION_SUPPORT_FLASH = 0 ; build code to support flash devices. OPTION_SUPPORT_EXHMEMTEST = 1 ; build code to perform exhaustive mem test. OPTION_SUPPORT_KNOWN_ENTRYPOINTS = 1 ; build code at compatible locations. OPTION_SUPPORT_IBM_COMPAT = 1 ; build IBM compatibility string. OPTION_SUPPORT_SERMSG = 0 ; build code to support RS232 serial mfg protocol. OPTION_SUPPORT_MFGTESTS = 0 ; build code to support manufacturing tests. OPTION_SUPPORT_RFD_DISK = 0 ; build code to support resident flash disk. OPTION_SUPPORT_PARITY = 0 ; build code to initialize RAM parity. OPTION_SUPPORT_PASSWORD = 0 ; build code for password checking. OPTION_SUPPORT_DRIVE_TABLE = 0 ; build table of known IDE drive types. OPTION_SUPPORT_DEMO = 0 ; build demo version of BIOS. OPTION_SUPPORT_PCMCIA = 0 ; build PCMCIA Socket Services code. OPTION_SUPPORT_ATA = 0 ; build PCMCIA ATA init code only. OPTION_FORCE_9600_BAUD = 1 ; always set 9600 baud on serial ports. ; Select the following to enable setup screens as desired. Note ; you may need to enable other options (for example, SUPPORT_IDE ; or SUPPORT_DEBUGGER) to allow those SETUP screens to function. OPTION_SETUP_ADVANCED = 1 ; build SETUP screen for advanced options. OPTION_SETUP_CHIPSET = 0 ; build SETUP screen for OEM's chipset. OPTION_SETUP_PASSWORD = 0 ; build SETUP password screen. OPTION_SETUP_DIAGNOSTICS= 1 ; build SETUP screen for std diagnostics. OPTION_SETUP_OEM_DIAG = 0 ; build SETUP screen for OEM diagnostics. OPTION_SETUP_DEBUGGER = 1 ; build SETUP option to break into debugger. OPTION_SETUP_IDE = 0 ; build SETUP screen to manage hard drives. OPTION_SETUP_SHADOWCACHE= 0 ; build SETUP screen for shadowing/cache. OPTION_SETUP_POWERMAN = 0 ; build SETUP screen for power management. OPTION_SETUP_MFGLINK = 0 ; build SETUP screen for manufacturing link. OPTION_SETUP_RAMDISK = 1 ; build SETUP option to format RAM disk. ; Select one of the following options to enable the code that provides ; PCMCIA socket services for a particular adapter. OPTION_PCMCIA_365 = 0 ; Intel 82365 controller. OPTION_PCMCIA_6710 = 0 ; Cirrus 6710 controller (1 socket). OPTION_PCMCIA_6720 = 0 ; Cirrus 6720 controller (2 sockets). ; Select one of the following options to enable the code that provides ; ATA window initialization for a particular adapter. This code should ; not be enabled if you are defining Socket Services for PCMCIA cards. OPTION_ATA_365 = 0 ; Intel 82365 controller. OPTION_ATA_6710 = 0 ; Cirrus 6710 controller (1 socket). OPTION_ATA_6720 = 0 ; Cirrus 6720 controller (2 sockets). ; Select one of the following methods to support DRAM refresh. ; Enable the CHARGE option on PC/XT computers in addition to 8237. OPTION_REFRESH_8237 = 0 ; enable 8237A/8254 DRAM refresh. OPTION_REFRESH_CHIPSET = 0 ; enable chipset DRAM refresh. OPTION_REFRESH_CPU = 0 ; enable CPU DRAM refresh controller. OPTION_REFRESH_CHARGE = 0 ; charge DRAMs after starting refresh. ; Select one of the following methods to support DMA. OPTION_DMA_8237 = 0 ; use external 8237 DMA controller. OPTION_DMA_CPU = 0 ; use internal 8237 DMA controller. ; Select one or both of the following methods to support interrupts. OPTION_INT_8259 = 1 ; use external 8259's int controller. OPTION_INT_CPU = 0 ; use internal CPU interrupt controller. ; Select one or both of the following methods to support timers. OPTION_TIMER_8254 = 1 ; use external 8254 timer. OPTION_TIMER_CPU = 0 ; use internal CPU timer controller. ; Select one of the following (or none) methods to support ; a watchdog timer. OPTION_WATCHDOG_CHIPSET = 0 ; use chipset watchdog timer. OPTION_WATCHDOG_CPU = 0 ; use CPU watchdog timer. ; Select zero, one or more of the following options related to the 8042. OPTION_8042_TESTP22P23 = 0 ; test block/unblock of these pins. OPTION_8042_READPWRSTAT = 0 ; read power-on status from keyboard. OPTION_8042_CHECKBAT = 0 ; test outcome of BAT from keyboard. OPTION_8042_PS2 = 0 ; wait 7us after read of 8042 status reg. OPTION_8042_WAIT_BEFORE_BAT = 1 ; delay before BAT. ; Select one of the following (or none) methods to do keyboard input. OPTION_KEYBOARD_PCAT = 1 ; use PC keyboard latch or 8042 kbd. OPTION_KEYBOARD_CUSTOMER= 0 ; use customer-supplied code. ; Select one of the following (or none) methods to do video. OPTION_VIDEO_6845 = 0 ; use 6845 mono/color CRT controller. OPTION_VIDEO_HD61830 = 1 ; use Hitachi HD61830 LCD controller. OPTION_VIDEO_CUSTOMER = 0 ; use customer-supplied code. OPTION_VIDEO_DUPLICATE = 0 ; copy redirected INT 10h output to CRT. OPTION_VIDEO_VIDEOMEM = 0 ; video memory available (test enabled). ; Select one or more of the following methods to handle critical POST errors. OPTION_CRITICAL_CHIPSET = 0 ; pass ctrl to chipset personality module. OPTION_CRITICAL_BEEP = 1 ; beep the speaker w/beep code. OPTION_CRITICAL_LPTFAIL = 0 ; consider missing LPT ports critical. ; Select one or more of the following options related to soft POST errors. OPTION_SOFTERR_SETUP = 0 ; enter setup if soft error encountered. ; Select any of the following to enable OEM manufacturing tests. OPTION_MFGTESTS_BOOT = 0 ; enter MFG if TESTMODE before O/S boot. OPTION_MFGTESTS_CRITICAL= 0 ; enter MFG if critical error during POST. ; Select any of the following to enable exhaustive memory tests during POST. OPTION_MEMTEST_LOW_POST = 1 ; test low (<1MB) exhaustively in POST. OPTION_MEMTEST_HIGH_POST= 0 ; test high (>1MB) exhaustively in POST. OPTION_MEMTEST_WAIT = 0 ; pause between tested blocks. OPTION_MEMTEST_CLEAR = 1 ; clear blocks to 0000h's during testing. OPTION_MEMTEST_CLICK = 1 ; click speaker during test. ; Select one Flash mode (PROTMODE or LINEAR) to tell the BIOS ; which low-level driver interface will be used in your system. OPTION_FLASH_PROTMODE = 0 ; protected-mode Flash interface. OPTION_FLASH_LINEAR = 0 ; linear Flash interface. OPTION_FLASH_8BIT = 0 ; put 16-bit Flash driver in 8-bit mode. ; Select one of the following Flash device types if Flash programming ; is to be provided in the core BIOS. OPTION_FLASH_28F008 = 0 ; Intel 28F008 sectored parts. OPTION_FLASH_28F016 = 0 ; Intel 28F016 sectored parts. OPTION_FLASH_28F032 = 0 ; Intel 28F032 sectored parts. OPTION_FLASH_28F001 = 0 ; Intel 28F001 boot block parts. OPTION_FLASH_28F002 = 0 ; Intel 28F002 boot block parts. OPTION_FLASH_28F004 = 0 ; Intel 28F004 boot block parts. OPTION_FLASH_28F100 = 0 ; Intel 28F100 boot block parts. OPTION_FLASH_28F200 = 0 ; Intel 28F200 boot block parts. OPTION_FLASH_28F400 = 0 ; Intel 28F400 boot block parts. OPTION_FLASH_29F010 = 0 ; AMD 29F010 sectored parts. OPTION_FLASH_29F040 = 0 ; AMD 29F040 sectored parts. OPTION_FLASH_29F100 = 0 ; AMD 29F100 boot block parts. OPTION_FLASH_29F200 = 0 ; AMD 29F200 boot block parts. OPTION_FLASH_29F400 = 0 ; AMD 29F400 boot block parts. OPTION_FLASH_28F256 = 0 ; Intel/AMD 28F256 bulk erase parts. OPTION_FLASH_28F512 = 0 ; Intel/AMD 28F512 bulk erase parts. OPTION_FLASH_28F010 = 0 ; Intel/AMD 28F010 bulk erase parts. OPTION_FLASH_28F020 = 0 ; Intel/AMD 28F020 bulk erase parts. OPTION_FLASH_EMULATE = 0 ; emulate Flash with RAM. OPTION_FLASH_CUSTOMER = 0 ; customer-defined part. ; Select one or more of the following methods to support cache. OPTION_CACHE_CPU = 0 ; use internal CPU cache controller. OPTION_CACHE_CHIPSET = 0 ; use chipset cache controller. OPTION_CACHE_8042 = 0 ; use 8042 to control cache. OPTION_CACHE_IOPORT = 0 ; use I/O port to control cache. ; Select one or more of the following methods to support turbo mode. OPTION_TURBO_CPU = 0 ; use internal CPU turbo controller. OPTION_TURBO_CHIPSET = 0 ; use chipset turbo controller. OPTION_TURBO_8042 = 0 ; use 8042 to control turbo mode. OPTION_TURBO_IOPORT = 0 ; use I/O port to control turbo mode. ; Select one or more of the following methods to support CPU speed mode. OPTION_SPEED_CPU = 0 ; use internal CPU speed controller. OPTION_SPEED_CHIPSET = 0 ; use chipset CPU speed controller. OPTION_SPEED_8042 = 0 ; use 8042 to control CPU speed. OPTION_SPEED_IOPORT = 0 ; use I/O port to control CPU speed. ; Select one or more of the following methods to gate the A20 line. OPTION_A20_8042 = 0 ; program 8042 to enable/disab A20. OPTION_A20_CHIPSET = 0 ; program chipset to enab/disab A20. OPTION_A20_PORT92 = 1 ; use I/O port 92h to enab/disab A20. ; The A20 check works by enabling the A20 gate, then testing to see ; that memory isn't replicated at 0MB and 1MB boundaries, respectively. ; If no memory is in the machine, some motherboards will fail this test ; even though the A20 logic is working properly. OPTION_A20_FAILPOST = 0 ; set to 1 to fail if A20 fails. ; Select only one of the following methods to reboot the computer. ; You MUST select one of these methods for your target. OPTION_REBOOT_JUMP = 0 ; jump to F000:FFF0 to re-run POST. OPTION_REBOOT_PORT92 = 1 ; set bit 0 in port 92 to reboot. OPTION_REBOOT_8042 = 0 ; reboot by pulsing 8042 line. ; Select one of the following methods to switch back to real mode. ; On 286-based systems, there is no instruction to switch to real ; mode, so port 92h must be used to reset the machine, or a triple- ; fault method can be used to cause the processor to enter shutdown. ; WARNING: The triple-fault method is patented by Microsoft; you must ; obtain a license from Microsoft in order to enable this option. ; General Software specifically disavows any responsibility for the ; use or inability to use the triple-fault method in any situation. OPTION_TOREAL_PORT92 = 0 ; set bit 0 in port 92/shutdown byte. OPTION_TOREAL_8042 = 0 ; switch to real mode via 8042 reboot. OPTION_TOREAL_TRIPLEFLT = 0 ; triple fault/shutdown byte. OPTION_TOREAL_CPU = 1 ; switch with 386 instruction. ; Select one or more of the following methods to support serial I/O. OPTION_SERIAL_8250 = 1 ; use external 8250 serial controller. OPTION_SERIAL_CPU = 0 ; use CPU serial controller. OPTION_SERIAL_WAIT_DSR = 0 ; wait for DSR before receiving bytes. OPTION_SERIAL_WAIT_DSRCTS = 0 ; wait for DSR & CTS before sending bytes. OPTION_SERIAL_FIFO = 0 ; enable FIFO if available. ; Select one or more of the following methods to support parallel I/O. OPTION_PARALLEL_EXTERNAL= 1 ; use external parallel ports. OPTION_PARALLEL_CPU = 0 ; use CPU parallel controller. ; Select one (or none) of the following methods to support ; power management. OPTION_POWERMAN_CPU = 0 ; use CPU power management routines. OPTION_POWERMAN_CHIPSET = 0 ; use chipset power management routines. ; Select one or more of the following options for debugger support. OPTION_DEBUG_HOTKEY = 0 ; use ALT+CTRL to break-into the debugger. OPTION_DEBUG_FLASH = 0 ; enable Flash debugging support. OPTION_DEBUG_WATCHINT = 0 ; enable software interrupt watchpoints. OPTION_DEBUG_NMI = 1 ; enable NMI breakins to debugger. ; Enable the following options as necessary for floppy I/O. If your ; system does not have a fully-compatible DMA controller that can be ; used to perform floppy I/O, then you need to set the DMA option to 0. ; Set 82077 only if you have a controller with a FIFO. The SEEK option ; is used during initialization to seek the head during POST. OPTION_FLOPPY_SEEK = 0 ; (BCPA) enable/disable floppy seek during POST. OPTION_FLOPPY_DMA = 0 ; use DMA to access drive, else polled. OPTION_FLOPPY_82077 = 0 ; use 82077 on-chip FIFO. OPTION_FLOPPY_WATCHIO = 0 ; print-out floppy INT 13h calls. ; Enable the following option if you want to perform an IDE SEEK ; operation as part of the IDE initialization process. This option ; is meaningful ONLY if OPTION_SUPPORT_IDE is enabled. Note that ; setting OPTION_IDE_SEEK to 0 disables the code that does the work, ; so it cannot be patched. Setting it to 1 enables the code and sets ; its default state to enabled. OPTION_IDE_RESET = 0 ; reset IDE controller during POST. OPTION_IDE_SEEK = 0 ; (BCPA) enable/disable IDE seek during POST. OPTION_IDE_DISABLE_INTS = 0 ; use CLI/STI around sector I/O. OPTION_IDE_SLOWDOWN = 0 ; delay after each word transfer. ; Enable the following option to beep before booting the O/S. ; You must have the SOUND option enabled for this to take effect. OPTION_BEEP_ON_BOOT = 1 ; (BCPA) enable/disable beep before booting. ; Enable the following option if you want to avoid lengthy memory ; tests and delays on cold boots. With FAST_BOOT enabled, memory ; will be initialized but only checked at 64KB intervals. OPTION_FAST_BOOT = 0 ; boot as quickly as possible. ; Choose one of the following sources for the real-time clock. OPTION_RTC_CMOS = 1 ; use the CMOS Real-Time Clock. OPTION_RTC_72421 = 0 ; use 72421 RTC. ; Select one of the following methods to reset the memory controller ; on power-on, if required. The only known memory controller that ; needs this is the Intel 82335SX. When in doubt, leave these off. OPTION_RSTMEMCTL_8042 = 0 ; reset memory ctrllr via 8042. ; Set the following options to route the standard keyboard/video, ; setup keyboard/video, and debugger keyboard/video to the appropriate ; devices. The value 0 means the PC keyboard or video board. A ; nonzero value means the specified COM port (COM1=1, COM2=2, etc.). OPTION_CONIO_STANDARD = 0 ; (BCPA) 0=use PC video/keyboard. OPTION_CONIO_DEBUG = 1 ; (BCPA) 0=use PC video/keyboard. OPTION_CONIO_SETUP = 1 ; (BCPA) 0=use PC video/keyboard. ; Select one of the following options if you have enabled the ROM disk. OPTION_ROMDISK_LOW = 0 ; low-memory ROM disk (real mode). OPTION_ROMDISK_HIGH = 1 ; high-memory ROM disk (protected mode). ; Set the following option to specify the port number (0=none, ; 1=COM1, 2=COM2, etc.) associated with the remote disk driver. OPTION_REMDISK_PORT = 0 ; (BCPA) 0=none, 1=COM1, 2=COM2, etc. ; BIOS date identification. BIOS_DATE EQU '07/05/96' ; (BCPA) build date of BIOS. BIOS_NAME EQU 'Copyright (C) 1990-1996 General Software, Inc.' BIOS_RESERVED EQU ', All rights reserved.', 0, 1ah BIOS_LICENSEE EQU 'Vendor name and message goes here.' ; Sometimes, programming of UART baud rates and other things such ; as timers, can be directly affected by the CPU clock speed. While ; this isn't the case in PC/AT-class machines, it is in 186-EC or ; other similar designs. The following parameter is only used in ; those unusual systems, so you need not set it unless you're using ; 186-class or V-series CPUs. CPU_MHZ = 20 ; clock speed (used for UART timing). ; You must select the proper CPU class for the BIOS you are building. CPUCLASS_X86 = 1 ; 808x, 8028x, i386, i486, Pentium. CPUCLASS_186EA = 2 ; Intel 80186-EA processor. CPUCLASS_186EB = 3 ; Intel 80186-EB processor. CPUCLASS_186EC = 4 ; Intel 80186-EC processor. CPUCLASS_386EX = 5 ; Intel 80386-EX processor. CPUCLASS_V25 = 6 ; NEC V25 processor. CPUCLASS_ELAN = 9 ; AMD Elan processor. CPUCLASS_V51 = 10 ; NEC V51 processor. CPUCLASS = CPUCLASS_386EX ; You must select the proper chipset for the BIOS you are building. CHIPSET_NONE = 1 ; No chipset; this is the default. CHIPSET_SL82C461 = 2 ; Symphony 82c461 chipset. CHIPSET_VL82C310 = 3 ; VLSI 82c310 chipset. CHIPSET_CT82C836 = 4 ; C&T 82c836 chipset. CHIPSET_ELAN = 6 ; AMD Elan Eval board. CHIPSET_SEQUOIA1= 7 ; PicoPower SEQUOIA-1 chipset. CHIPSET_HT18 = 8 ; Headland Technology HT-18 (386SX). CHIPSET_R380EX = 9 ; RadiSys R380EX chipset. CHIPSET = CHIPSET_R380EX ; select chipset type here. ; If you are using an evaluation board, and you want to use default ; values for the CPU initialization MACRO, then select that board here. ; If you select a supported board, then you will be invoking a macro ; defined in the associated CPU INC file (i.e., 186EC.INC or 386EX.INC). BOARDCLASS_NONE = 0 ; no specific evaluation board. BOARDCLASS_I186EC = 1 ; Intel 186-EC eval board. BOARDCLASS_MB0 = 2 ; Intel 386-EX MB0 evaluation board. BOARDCLASS_MB1 = 3 ; Intel 386-EX MB1 evaluation board. BOARDCLASS_MB1_ROM_AT_C000 = 4 ; Intel 386-EX MB1 eval board w/256K ROM disk. BOARDCLASS_EXPLR1 = 5 ; Intel 386-EX EXPLORER 1 eval board. BOARDCLASS_CUSTOM = 6 ; custom board defined by customer. BOARDCLASS_ELANREV2 = 7 ; AMD Elan rev 2.2 board. BOARDCLASS_EXPLR2 = 8 ; Intel Explorer 2 eval board. BOARDCLASS = BOARDCLASS_EXPLR2 ; sample only. ; Power-on delay, in "loops". The code doesn't know anything about ; CPU cycles during power-on delay since peripherals aren't operating. POWER_ON_DELAY = 255 ; (BCPA) # iterations through a loop $ loop. ; The following parameters define the end of standard CMOS, ; the beginning of the Extended CMOS (used by the Chipset) and ; the offset of the beginning of the CMOS cache area. CONFIG_MAX_CMOS_LOCATIONS = 40h ; (BCPA) 40 on old 286 boards. CONFIG_START_CHIPSET_CMOS = 40h ; (BCPA) start of extended CMOS. CONFIG_START_CMOS_CACHE = 10h ; (BCPA) starting offset for CMOS read/write cache. CONFIG_CMOS_INDEX = 70h ; index port for RTC/CMOS. CONFIG_CMOS_DATA = 71h ; data port for RTC/CMOS. ; This parameter defines the initial state of the CMOS Real-Time Clock. CONFIG_DEFAULT_RTC = 026h ; (BCPA) CMOS RTC time base/rate. ; The following parameters are used to initialize CMOS locations ; in the event that CMOS has lost power or is otherwise corrupted. ; The routine ReadCmosConfig in BIOS.ASM uses these fields to ; program the CMOS bytes directly. Refer to CMOS.INC for details ; about the values of these bytes. OEM_FLOPPY_NONE = 0 OEM_FLOPPY_360 = 1 OEM_FLOPPY_12 = 2 OEM_FLOPPY_720 = 3 OEM_FLOPPY_144 = 4 OEM_FLOPPY_288 = 5 OEM_FLOPPY_ROM = 6 ; ROM disk. OEM_FLOPPY_RAM = 7 ; RAM disk. OEM_FLOPPY_RFD = 8 ; Resident Flash disk. OEM_INIT_CMOS_FLOPPY = ((OEM_FLOPPY_NONE SHL 4) OR (OEM_FLOPPY_NONE)) OEM_INIT_CMOS_HARD = 10h ; (BCPA) drive C: is type 1. OEM_INIT_CMOS_EQUIP = 00000001b ; (BCPA) default devflags lsb byte. OEM_INIT_CMOS_TYPEMATIC = 00h ; (BCPA) no typematic programming. OEM_INIT_CMOS_OPTIONS = CMOS_OPTIONS_BOOT_A_C ; (BCPA) boot A: then C:. OEM_INIT_CMOS_ADVSETUP = (CMOS_ADVSETUP_TEST1MB OR \ CMOS_ADVSETUP_TESTCLICK OR \ CMOS_ADVSETUP_DELETE) ; (BCPA). OEM_INIT_CMOS_SYSINFO = (CMOS_SYSINFO_KEYBOARD OR \ CMOS_SYSINFO_CONFIGBOX OR \ CMOS_SYSINFO_ROMDISK OR \ CMOS_SYSINFO_EXHMEMTEST OR \ CMOS_SYSINFO_HDSEEK) ; (BCPA). OEM_INIT_CMOS_SHADOW1 = 00h ; (BCPA) shadow nothing by default. OEM_INIT_CMOS_SHADOW2 = 00h ; (BCPA) shadow nothing by default. OEM_INIT_CMOS_OPTIMIZE = (CMOS_OPTIMIZE_POWER OR \ CMOS_OPTIMIZE_RFD OR \ CMOS_OPTIMIZE_ATA) OEM_INIT_CMOS_HARD_0 = 0 ; hard disk drive type #0. OEM_INIT_CMOS_HARD_1 = 0 ; hard disk drive type #1. OEM_INIT_CMOS_FD0_CYL = 0 ; fixed disk 0 cylinders. OEM_INIT_CMOS_FD0_HEADS = 0 ; fixed disk 0 heads. OEM_INIT_CMOS_FD0_SPT = 0 ; fixed disk 0 sectors per track. OEM_INIT_CMOS_FD1_CYL = 0 ; fixed disk 0 cylinders. OEM_INIT_CMOS_FD1_HEADS = 0 ; fixed disk 0 heads. OEM_INIT_CMOS_FD1_SPT = 0 ; fixed disk 0 sectors per track. ; Number of attempts made to read from the floppy drive before failing. CONFIG_FLOPPY_RETRY = 3 ; (BCPA) default # of floppy retries. ; Number of attempts made to boot from a drive before failing. CONFIG_BOOT_ATTEMPT = 1 ; (BCPA) default # of boot attempts from each drive. ; DRAM refresh interval, specified in microseconds. CONFIG_REFRESH_INTERVAL = 15 ; (BCPA) 15us refresh period. ; Number of times to loop waiting for the 8042 controller to be "ready". CONFIG_WAIT_8042 = 00400h ; (BCPA) amount of "time" to wait for 8042 controller. ; Number of times to loop waiting for the 8042 controller to ; finish executing a command. CONFIG_SETTLE_8042 = 400h ; (BCPA) amount of "time" to wait for 8042 controller. ; Number of times to loop for delay during memory test count-ups. CONFIG_WAIT_COUNT = 200h ; (BCPA) delay between block checks. ; Number of times to loop for delay during LPT initialization. CONFIG_WAIT_LPT = 1000h ; (BCPA) delay while LPT port initializes. ; Default BIOS I/O timeout values, in seconds. CONFIG_SERIAL_TIMEOUT = 1 ; (BCPA) one second timeout by default. CONFIG_PARALLEL_TIMEOUT = 1 ; (BCPA) one second timeout by default. ; The following parameter defines the POST status I/O port number. ; Normally, this is 80h in a PC-compatible platform, although it ; can be other values (such as 3ffh for the scratchpad register ; on a 16550 UART), so that CsPostError can get at the value. CONFIG_POST_PROGRESS_PORT = 80h ; I/O port to write POST codes to. CONFIG_POST_PROGRESS_COM = 3f8h ; base I/O address of POST COM port. CONFIG_MFG_PROGRESS_PORT = 80h ; I/O port to write MFGMODE codes to. ; The following parameter (PORT) is used by the INT 15h function 86h ; "wait" function as the I/O port number to read in order to establish ; a CPU-independent timing. CYCLES specifies the number of I/O's to ; perform inside the loop. If your machine runs its I/O bus faster than ; normal, you may need to increase this value to slow down the timing. CONFIG_IODELAY_PORT = 2ffh ; I/O port to use for wait states. CONFIG_IODELAY_CYCLES = 1 ; # I/O instructions to use in loop. CONFIG_IODELAY_DIVISOR = 15 ; divide mics by this to get loops. ; Maximum amount of low memory to allow (so the BIOS memory test ; doesn't try to include VGA memory as a part of low memory). If ; your configuration has more than 640K of low memory, then you ; need to change this limit to effectively use that memory. You ; can reduce the 640 by some amount if you need a private scratch ; space at the upper end of memory as well. CONFIG_MAX_LOW_MEMORY = 640 ; (BCPA) default low memory size limit. ; If you have selected OPTION_SUPPORT_TESTBASEMEM, then you must ; select the size of low memory to be tested. This memory will ; be wiped out by POST. Normally, this is set to 64 (64KB), but ; you can change it to some number LESS than that to preserve any ; data stored in SRAM, etc., that you don't want cleared during POST. CONFIG_TESTBASE_SIZE = 64 ; (BCPA) low memory test size in KB. ; The following parameter determines the maximum amount of extended ; memory to test, in 64KB blocks, starting at 1MB. Warning: If this ; parameter causes the memory test to extend into Flash memory blocks, ; it can cause a machine lock-up because the test involves writing ; data TO the memory, and these data can be taken as COMMANDS by Flash. CONFIG_MAX_EXT_MEMORY = 48 ; 4MB limit for EX MB1 board. ; The BIOS needs a 1K area for scratch workspace. This is initially ; located at the segment address specified below, but is later moved ; automatically (during POST) by the BIOS to the top of memory. CONFIG_EXTRA_SEGMENT = 0050h ; (BCPA) by default, this starts at seg 50h. ; Default Equipment byte. CONFIG_DEFAULT_EQUIP_BYTE = 00111101b ; (BCPA) default equip.byte for PC/XT. ; ROM Scan configuration parameters. CONFIG_VIDEO_ROM_SCAN = 0c000h ; (BCPA) seg addr of video adapter ROM. CONFIG_LOW_ROM_SCAN = 0c800h ; (BCPA) first seg addr of ROM scan area. CONFIG_HIGH_ROM_SCAN = 0f000h ; (BCPA) first seg addr outside ROM scan. CONFIG_MINI_DOS_SCAN = 0e800h ; (BCPA) seg addr of Mini-DOS. CONFIG_ROM_SCAN_INTERVAL= 2048 ; (BCPA) bytes between ROM scan addresses. ; Video configuration parameters. CONFIG_VIDEO_SEG_GRAPHIC= 0a000h ; (BCPA) seg addr of graphics video RAM. CONFIG_VIDEO_SEG_MONO = 0b000h ; (BCPA) seg addr of monochrome RAM. CONFIG_VIDEO_SEG_COLOR = 0b800h ; (BCPA) seg addr of color RAM. ; User interface controls. CONFIG_BEEP_LENGTH = 200 ; (BCPA) duration for beeps to last (x10ms). CONFIG_BEEP_CYCLE = 100 ; (BCPA) cycle time for oscillation (x/Hz). CONFIG_BEEP_8254_TONE = 0533H ; (BCPA) divisor for 8254's T2 timer. ; PCMCIA controller addressing. CONFIG_PCMCIA_IOBASE = 03e0h ; standard Cirrus address. ; 8042 cache, speed, and turbo control lines. CONFIG_CACHELINE_8042 = 23 ; (BCPA) cache enable pin number on 8042. CONFIG_TURBOLINE_8042 = 24 ; (BCPA) turbo mode pin number on 8042. CONFIG_SPEEDLINE_8042 = 28 ; (BCPA) CPU speed pin number on 8042. CONFIG_RESETLINE_8042 = 23 ; (BCPA) reset line pin number on 8042. CONFIG_8042LINE_POSITIVE= 80h ; (BCPA) positive logic programming on line. CONFIG_8042LINE_NEGATIVE= 00h ; (BCPA) negative logic programming on line. ; RFD/ROM/RAM/REMOTE disk configuration. The ROMDISK_DATA parameter ; specifies a real-mode segment address of the ROM disk data used by ; the low memory ROM disk. If you enable the high memory ROM disk, ; then the system uses ROMDISK_DATA_EXT_HI/LO as the physical address ; instead of a real-mode 16:16 address. The RAM disk does not allow ; real-mode addressing; instead it uses 32-bit physical addresses. ; Similarly, the RFD disk requires 32-bit physical addresses. CONFIG_ROMDISK_DATA = 0c040h ; (BCPA) seg addr, image of ROM data. CONFIG_ROMDISK_DATA_EXT_HI = 0000ch ; (BCPA) abcd in physaddr=abcdefgh. CONFIG_ROMDISK_DATA_EXT_LO = 00400h ; (BCPA) efgh in above address. CONFIG_RAMDISK_DATA_EXT_HI = 00010h ; (BCPA) abcd in physaddr=abcdefgh. CONFIG_RAMDISK_DATA_EXT_LO = 00000h ; (BCPA) efgh in above address. CONFIG_RAMDISK_MAXSIZE = (16*1024) ; max # KB in RAM disk area to scan. CONFIG_RFDDISK_DATA_EXT_HI = 0003ah ; (BCPA) abcd in physaddr=abcdefgh. CONFIG_RFDDISK_DATA_EXT_LO = 00000h ; (BCPA) efgh in above address. CONFIG_RFDDISK_KBSIZE = 2048 ; # KB in Flash array. CONFIG_RFDDISK_KBBLKSIZE= 32 ; # KB in each Flash block. CONFIG_REMDISK_BAUD = 11 ; (BCPA) 115 kbaud (see ext init INT 14h fn). ; Flash VPP programming controls. If your design employs Flash, and ; you want Vpp to be under control of the Flash firmware in the BIOS, ; you need to tell the BIOS which I/O port to use to control Vpp, and ; what the value is that should be written to the port to enable Vpp. ; The BIOS ORs-in this value with the port contents when enabling Vpp, ; and ANDs-out the value from the port contents when disabling Vpp. ; You'll also need to specify the number of microseconds for the enable ; function to wait for Vpp to ramp-up. This is dependent on analog pwr. CONFIG_FLASH_VPP_PORT = 240h ; example: use port 240h. CONFIG_FLASH_VPP_ENAB_MASK = 00100000b ; example: use bit 5. CONFIG_FLASH_VPP_WAIT_MICS = 100 ; example: wait 100us for Vpp to ramp-up. ; Flash temporary staging buffer. This parameter determines what ; 64KB segment of real-mode memory is to be used as a staging buffer ; for Flash operations, if OPTION_SUPPORT_MFGTESTS is enabled. This ; buffer is only used in the manufacturing tests so that the BIOS ; can be replaced by transferring a 64KB block over the serial line ; to RAM in this area, then issuing a erase/write command to the Flash ; to update the Flash block. CONFIG_FLASH_DATASEG = 2000h ; 64KB seg for staging data. ; Flash programming RAM-based code segment. This parameter defines ; the segment in RAM where the Flash routines copy the BIOS to and ; run out of during the actual Flash programming. This is important ; so that the Flash device doesn't receive fetch cycles from the CPU ; during the programming process. CONFIG_FLASH_CODESEG = 1000h ; 64KB seg for copying BIOS to. ; The custom OEM memory paging mechanism available through INT 15h ; function a2h is supported by the following two definitions, which ; specify where the segment of the memory window is, and what the ; I/O port is that will be used by INT 15h. CONFIG_PAGED_MEM_SEG = 0d000h ; segment address of memory window. CONFIG_PAGED_MEM_REG = 0380h ; I/O address of 8-bit page register. ; Timer programming. This constant does NOT program the hardware ; timer; it only indicates to a few components of the BIOS (such ; as the SETUP screen and floppy/hard disk systems) what the frequency ; of the INT 1ch timer ticks are. The constant is used to build ; delay values for motor on/off operations, etc. TIMER_0_HZ = 18 ; (BCPA) used to factor elased time. TIMER_0_INIT = 0ffffh ; initial value for T0 load. ; Parallel port BIOS configuration. Specify 0000h for no port. LPT1_BASE = 0378h ; (BCPA) LPT1 base address. LPT2_BASE = 0278h ; (BCPA) LPT2 base address. LPT3_BASE = 03bch ; (BCPA) LPT3 base address. ; Serial port BIOS configuration. Specify 0000h for no port. COM1_BASE = 03f8h ; (BCPA) COM1 base address. COM2_BASE = 02f8h ; (BCPA) COM2 base address. COM3_BASE = 03e8h ; (BCPA) COM3 base address. COM4_BASE = 02e8h ; (BCPA) COM4 base address. ; Default settings for serial ports. COM1_INIT = 11100011b ; (BCPA) 9600, N, 8, 1. COM2_INIT = 11100011b ; (BCPA) 9600, N, 8, 1. COM3_INIT = 11100011b ; (BCPA) 9600, N, 8, 1. COM4_INIT = 11100011b ; (BCPA) 9600, N, 8, 1. ; Settings for the OEM test manufacturing port protocol. COM1_EOI = 64h ; do not modify. COM2_EOI = 63h ; do not modify. MFG_COM_BASE = COM2_BASE ; I/O port. MFG_INT_VECT = (8+3) ; interrupt vector for COM2. MFG_EOI_PORT = 20h ; first 8259 for COM1/COM2 on PC/AT. MFG_EOI_CMD = COM2_EOI ; specific EOI command for mfg port. CONFIG_MFG_BAUD = 1 ; 0=115kb, 1=56, 2=38.4, 3=19.2, 4=9600. ; These two parameter pairs can be used alone or in combination to ; specify I/O ports that can be read to determine if test mode is ; active. Set the REG/REG2 value to 0 to disable that specific test. ; When both are specified (nonzero), then EITHER of the test mode ; tests can cause the system to enter test mode. MFG_TESTMODE_REG= 0 ; I/O port containing TEST MODE bit. MFG_TESTMODE_BIT= 01h ; if bit is set, TEST MODE is enabled. MFG_TESTMODE_REG2= 0 ; I/O port containing TEST MODE bit. MFG_TESTMODE_BIT2= 00000100b ; if bit is set, TEST MODE is enabled. ; Machine type indicator. BIOS_HDWR = BIOS_MODEL_AT ; machine type to be stored in ROM. BIOS_HDWR_SUB = BIOS_SUBMODEL_AT; machine type submodel. ; Debugger options. DEBUG_CMDBUF_LEN = 128 ; # bytes in input command buffer. DEBUG_MAX_BREAKPOINTS = 8 ; # breakpoints supported.