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- module octal
- title' Octal counter based on example from MMI PAL Handbook
- Ngoc Nicholas Data I/O Corp. 28 Aug 1984'
-
- P7024 device 'P20X8';
-
- D0,D1,D2,D3,D4,D5,D6,D7 pin 3,4,5,6,7,8,9,10;
- Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 pin 15,16,17,18,19,20,21,22;
- CLK,I0,I1,OC,CO,CI pin 1,2,11,13,14,23;
-
- H,L,X,Z,C = 1, 0, .X., .Z., .C.;
-
- Data = [D7,D6,D5,D4,D3,D2,D1,D0];
- Count = [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0];
-
- Mode = [I1,I0];
- Clear = [ 0, 0];
- Hold = [ 0, 1];
- Load = [ 1, 0];
- Inc = [ 1, 1];
-
- equations
- !Q0 := (!I1 & !I0 "Clear LSB
- # I0 & !Q0) "Count/Hold
- $ ( I1 & !I0 & !D0 "Load
- # I1 & I0 & !CI) ;
-
- !Q1 := (!I1 & !I0 "Clear
- # I0 & !Q1) "Count/Hold
- $ ( I1 & !I0 & !D1 "Load
- # I1 & I0 & !CI & Q0) ;
-
- !Q2 := (!I1 & !I0 "Clear
- # I0 & !Q2) "Count/Hold
- $ ( I1 & !I0 & !D2 "Load
- # I1 & I0 & !CI & Q0 & Q1) ;
-
- !Q3 := (!I1 & !I0 "Clear
- # I0 & !Q3) "Count/Hold
- $ ( I1 & !I0 & !D3 "Load
- # I1 & I0 & !CI & Q0 & Q1 & Q2) ;
-
- !Q4 := (!I1 & !I0 "Clear
- # I0 & !Q4) "Count/Hold
- $ ( I1 & !I0 & !D4 "Load
- # I1 & I0 & !CI & Q0 & Q1 & Q2 & Q3) ;
-
- !Q5 := (!I1 & !I0 "Clear
- # I0 & !Q5) "Count/Hold
- $ ( I1 & !I0 & !D5 "Load
- # I1 & I0 & !CI & Q0 & Q1 & Q2 & Q3 & Q4) ;
- @page
- !Q6 := (!I1 & !I0 "Clear
- # I0 & !Q6) "Count/Hold
- $ ( I1 & !I0 & !D6 "Load
- # I1 & I0 & !CI & Q0 & Q1 & Q2 & Q3 & Q4 & Q5) ;
-
- !Q7 := (!I1 & !I0 "Clear MSB
- # I0 & !Q7) "Count/Hold
- $ ( I1 & !I0 & !D7 "Load
- # I1 & I0 & !CI & Q0 & Q1 & Q2 & Q3 & Q4 & Q5 & Q6) ;
-
- !CO = !CI & Q0 & Q1 & Q2 & Q3 & Q4 & Q5 & Q6 & Q7 ; "CARRY OUT
-
- test_vectors 'test load and increment'
- ([CLK,OC,Mode ,Data,CI] -> [CO,Count])
- [ C ,L ,Load , 1 ,X ] -> [ H, 1 ];
- [ C ,L ,Inc , X ,0 ] -> [ H, 2 ];
- [ C ,L ,Load , 3 ,X ] -> [ H, 3 ];
- [ C ,L ,Inc , X ,0 ] -> [ H, 4 ];
- [ C ,L ,Load , 7 ,X ] -> [ H, 7 ];
- [ C ,L ,Inc , X ,0 ] -> [ H, 8 ];
- [ C ,L ,Load ,^h0F,X ] -> [ H,^h0F ];
- [ C ,L ,Inc , X ,0 ] -> [ H,^h10 ];
- [ C ,L ,Load ,^h1F,X ] -> [ H,^h1F ];
- [ C ,L ,Inc , X ,0 ] -> [ H,^h20 ];
- [ C ,L ,Load ,^h3F,X ] -> [ H,^h3F ];
- [ C ,L ,Inc , X ,0 ] -> [ H,^h40 ];
- [ C ,L ,Load ,^h7F,X ] -> [ H,^h7F ];
- [ C ,L ,Inc , X ,0 ] -> [ H,^h80 ];
- [ C ,L ,Load ,^hFF,0 ] -> [ L,^hFF ];
- [ C ,L ,Inc , X ,0 ] -> [ H,^h00 ];
-
- test_vectors 'test load'
- ([CLK,OC,Mode ,Data,CI] -> [CO,Count])
- [ C ,L ,Load ,^hFF,L ] -> [ L,^hFF ];
- [ C ,L ,Load ,^hFE,X ] -> [ H,^hFE ];
- [ C ,L ,Load ,^hFD,X ] -> [ H,^hFD ];
- [ C ,L ,Load ,^hFB,X ] -> [ H,^hFB ];
- [ C ,L ,Load ,^hF7,X ] -> [ H,^hF7 ];
- [ C ,L ,Load ,^hEF,X ] -> [ H,^hEF ];
- [ C ,L ,Load ,^hDF,X ] -> [ H,^hDF ];
- [ C ,L ,Load ,^hBF,X ] -> [ H,^hBF ];
- [ C ,L ,Load ,^h7F,X ] -> [ H,^h7F ];
- [ C ,L ,Load ,^hFF,L ] -> [ L,^hFF ];
- @page
- test_vectors 'test count'
- ([CLK,OC,Mode ,Data,CI] -> [CO,Count])
- [ C ,L ,Clear, X ,X ] -> [ H, 0 ];
- [ C ,L ,Inc , X ,L ] -> [ H, 1 ];
- [ C ,L ,Inc , X ,L ] -> [ H, 2 ];
- [ C ,L ,Inc , X ,L ] -> [ H, 3 ];
- [ C ,L ,Inc , X ,L ] -> [ H, 4 ];
- [ C ,L ,Inc , X ,L ] -> [ H, 5 ];
- [ C ,L ,Inc , X ,L ] -> [ H, 6 ];
- [ C ,L ,Inc , X ,L ] -> [ H, 7 ];
- [ C ,L ,Inc , X ,L ] -> [ H, 8 ];
- [ C ,L ,Inc , X ,L ] -> [ H, 9 ];
- [ C ,L ,Inc , X ,L ] -> [ H, ^hA ];
- [ C ,L ,Inc , X ,L ] -> [ H, ^hB ];
- [ C ,L ,Inc , X ,L ] -> [ H, ^hC ];
-
- test_vectors 'test hold and High Z'
- ([CLK,OC,Mode ,Data,CI] -> [CO,Count])
- [ C ,L ,Load ,^hFE,X ] -> [ H,^hFE ];
- [ C ,L ,Inc , X ,L ] -> [ L,^hFF ];
- [ C ,L ,Inc , X ,H ] -> [ H,^hFF ];
- [ C ,L ,Hold , X ,L ] -> [ L,^hFF ];
- [ C ,L ,Inc , X ,L ] -> [ H,^h00 ];
- [ X ,H , X , X ,X ] -> [ X, Z ];
-
- "This is an 8-bit synchronous counter with parallel load, clear, and
- "hold capability. The load operation loads the inputs (D7-D0) into the
- "output register (Q7-Q0). The clear operation resets the output register
- "to all lows. The hold operation holds the previous value regardless of
- "clock transitions. The increment operation adds one to the output
- "register when the carry-in is true (!CI=L), otherwise the operation
- "is a hold. The carry-out (!CO) is true (!CO=L) when the output register
- "(Q7-Q0) is all highs, otherwise false (/CO=H).
-
- "These operations are exercised in the test vectors and summarized in the
- "Operations Table:
- "
- " !OC CLK I1 I0 !CI D7-D0 Q7-Q0 Operation
- " --------------------------------------------------
- " H X X X X X Z HI-Z
- " L C L L X X L Clear
- " L C L H X X Q Hold
- " L C H L X D D Load
- " L C H H H X Q Hold
- " L C H H L X Q PLUS 1 Increment
- " --------------------------------------------------
-
- "Two or more octal counters may be cascaded to provide larger counters.
- "The operation codes were chosen such that when I1 is high, I0 may be
- "used to select between load and increment as in a program counter
- "(jump/increment). Also, carry-out (!CO) and carry-in (!CI) are located
- "on pins 14 and 23 respectively, which provides for convenient
- "interconnections when two or more octal counters are cascaded to
- "implement larger counters.
-
- end octal;
-