home *** CD-ROM | disk | FTP | other *** search
- MODULO-60 C0UNTER
-
- This is an alternative way to describe a modulo-60 counter, which steps
- through the sequence 0, 1, 2, ..., 57, 58, 59, 0. This one uses a
- numerical equation rather than a map. Contrast this form with the
- equivalent numerical map in file MOD60.PLD.
-
- Q[5..0] is the six-bit counter value.
-
- HOLD is an input signal which prevents the counter from advancing.
-
- RESET is an input signal which clears the counter to zero on the next
- clock edge.
-
- HOLDO is an output signal which prevents any higher-order counters in a
- cascade from advancing until the lower-level counters overflow.
-
- CLK is the clock signal.
-
-
- |PAL16R6 in:(HOLD, RESET), out:Q[5..0], io:HOLDO, clock:CLK
- |
- | Active-Low: "All"
- | Conditioning: CLK // Q[5..0]
- |
- | Q[5..0] = (Q[5..0]+1 & RESET' & HOLD' & Q[5..0]/=59)
- | # (Q[5..0] & RESET' & HOLD )
- |
- | HOLDO = Q[5..0]/=59
-
-
- |Vectors:
- |{ Display CLK, (Q[5..0])d, HOLDO
- | Test RESET=1; CLK
- | Test RESET=0; CLK=65(0,1)
- | End }
-
-