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- MODULO-60 C0UNTER
-
- This counter steps through the sequence 0, 1, 2, ..., 57, 58, 59, 0.
- Modulo counters can be defined in several ways. This way uses a
- reasonable small number of product terms; the counter is allowed to count
- forward if it ever gets into states 60, 61, 62, or 63, which does not
- happen in practice.
-
- Q[5..0] is the six-bit counter value.
-
- HOLD is an input signal which prevents the counter from advancing.
-
- RESET is an input signal which clears the counter to zero on the next
- clock edge.
-
- HOLDO is an output signal which prevents any higher-order counters in a
- cascade from advancing until the lower-level counters overflow.
-
- CLK is the clock signal.
-
-
- |PAL16R6 in:(HOLD, RESET), out:Q[5..0], io:HOLDO, clock:CLK
- |
- | Active-Low: "All"
- | Conditioning: CLK // Q[5..0]
- |
- | Map: Q[5..0] -> Q[5..0]
- | { n -> n+1, n/=59 & RESET' & HOLD'
- | n -> 0, n==59 # RESET
- | n -> n, RESET' & HOLD }
- |
- | HOLDO = Q[5..0]/=59
-
-
- |Vectors:
- |{ Display CLK, (Q[5..0])d, HOLDO
- | Test RESET=1; CLK
- | Test RESET=0; CLK=65(0,1)
- | End }
-
-