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OrCAD PLD PROGRAMMABLE DEVICE REFERENCE TABLES The tables shown here describe the format of programmable logic devices processed by the OrCAD PLD compiler. The material is equivalent to the binary .TBL files in directory \ORCADESP\PLD\LIBRARY, except here the material appears in ASCII text format. The material is formatted as a booklet, with form feeds between pages, suitable for printing at six lines per inch and twelve characters per inch on standard paper. February, 1991 TABLE OF CONTENTS 1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Phases of the compiler . . . . . . . . . . . . . . . . . . . . . 1 Pin keywords . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Fuse array . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. GENERAL 20-SERIES DEVICES . . . . . . . . . . . . . . . . . . . 5 3. SPECIAL 20-SERIES DEVICES . . . . . . . . . . . . . . . . . . . 9 4. GENERAL 24-SERIES DEVICES . . . . . . . . . . . . . . . . . . . 12 5. SPECIAL 24-SERIES DEVICES . . . . . . . . . . . . . . . . . . . 19 6. GENERAL 28-SERIES DEVICES . . . . . . . . . . . . . . . . . . . 24 7. SELECTABLE REGISTER DEVICES . . . . . . . . . . . . . . . . . . 27 8. GALs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Automatic selection of modes . . . . . . . . . . . . . . . . . . 32 Registers and enables . . . . . . . . . . . . . . . . . . . . . 35 Forcing a specific mode . . . . . . . . . . . . . . . . . . . . 37 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . 37 Signatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9. RA DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10. EP DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 EP300 series . . . . . . . . . . . . . . . . . . . . . . . . . . 48 EP320 series . . . . . . . . . . . . . . . . . . . . . . . . . . 49 EP600 and EP900 series . . . . . . . . . . . . . . . . . . . . . 51 EP1800 series . . . . . . . . . . . . . . . . . . . . . . . . . 57 11. MACH DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12. EMITTER COUPLED DEVICES . . . . . . . . . . . . . . . . . . . . 64 13. EXCLUSIVE-OR DEVICES . . . . . . . . . . . . . . . . . . . . . . 67 14. GENERIC DEVICES . . . . . . . . . . . . . . . . . . . . . . . . 69 15. DEMONSTRATION DEVICE . . . . . . . . . . . . . . . . . . . . . . 71 16. PROGRAMMABLE READ ONLY MEMORIES . . . . . . . . . . . . . . . . 72 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 OrCAD PLD PROGRAMMABLE DEVICE REFERENCE TABLES 1. INTRODUCTION The tables shown here describe the format of programmable logic devices processed by the OrCAD PLD compiler. The material is equivalent to the binary .TBL files in directory \ORCADESP\PLD\LIBRARY, except here the material appears in ASCII text format. This is in fact the source material for the .TBL files. The format of the tables is described in an appendix of the OrCAD PLD reference guide, with some of the description repeated here. Phases of the compiler ---------------------- For simple devices, architectural configuration is handled within the compiler under the guidance of these reference tables. For more advanced devices, architecture is handled partly by a separate program, loaded as an overlay to the PLD compiler. Each class of devices has its own overlay, which carries a .BIN extension in the library. When processing a design, the compiler runs through these phases. 1. Parsing. In this phase, the source file is read, checked for proper syntax, and converted to a compact form in the computer's memory. 2. Logic synthesis. Numerical maps, state machines, truth tables, and other abstract definitions are converted to Boolean equations. 3. Logic reduction. The Boolean equations are processed to achieve smaller, more compact forms without changing the logic. 4. Architecture. The reduced equations are examined and the device is configured by setting its architectural fuses. This involves programming output macrocells, selecting device modes, and so forth. For simpler devices, the compiler handles this phase directly. For more elaborate devices, an overlay is called upon to do the work. 5. Fuse generation. Equations (now possibly altered during the architectural phase) are converted to a fuse map and stored in the main fuse array. Reports showing the final results are printed, the .VEC and .JED files are produced, and a final summary showing time and memory is printed. The most important data for everyday use are the pin lists associated with `in', `out', `io', and `clock' keywords for each device. As explained in the PLD reference guide, pin numbers can be listed explicitly. However, it is usually easier to list pin names such as `in' and `io'. To find out what pin names to use, you need these reference tables. PROGRAMMABLE DEVICE REFERENCE TABLES Page 2 Pin keywords ------------ In the tables that follow, pins for the programmable devices are grouped into at least seven different categories: Group Keyword Description 1 in Used for pins that are purely input. 2 out Used for pins that are output, possibly but not necessarily with feedback. 3 io Used for pins that are output with feedback. 4 clock Used to clock edge-triggered registers within the device. 5 enable Used to enable tri-state drivers within the device. This is used only for hard-wired common enable lines. 6 reset Used to reset internal registers (force them low). On the PAL22V10 and others, this is not an actual pin but rather is an internal node. 7 preset Used to preset internal registers (force them high). Like reset, on the PAL22V10 and others, this is not an actual pin but rather is an internal node. To see how the pin names are used, consider the table for a PAL16R6. (PAL is a registered trademark of Advanced Micro Devices). The PAL16R6 has eight pure input pins (numbered 2 through 9), six registered output pins with feedback (numbered 13 through 18), and two combinational input/ouput pins (numbered 12 and 19), also with feedback. There is a common clock and common enable for all the registers (pins 1 and 11). The PAL16R6 table lists the following groups of pins together with the actual pin numbers in the order they are assigned by the PLD compiler: Type PAL16R6 Activity 0 Group 1 (in) 2 3 4 5 6 7 8 9 Group 2 (out) 18 17 16 15 14 13 Group 3 (io) 19 12 Group 4 (clock) 1 Group 5 (enable) 11 Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 Rows 19(1t7) 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) 13(8R) 12(1t7) PROGRAMMABLE DEVICE REFERENCE TABLES Page 3 The first two lines of the table simply identify the device and declare that the device favors active-low signals (output drivers are inverters). The next three lines define which pins are connected to signals in Group 1 (in), Group 2 (out), and Group 3 (io). Suppose a PLD definition begins like this. PAL16R6 in:(A, B, C, D, E, F), out:Y[5..0] Then the signals marked `in' will be matched with the Group 1 pins, starting at the left. A is assigned to pin 2, B to pin 3, C to pin 4, and so forth. Pins 8 and 9 remain disconnected. Group 1 (in) 2 3 4 5 6 7 8 9 : : : : : : A B C D E F Likewise, the signals marked `out' will be matched with the Group 2 pins. This time no pins remain disconnected. Group 2 (out) 18 17 16 15 14 13 : : : : : : Y5 Y4 Y3 Y2 Y1 Y0 Since no signals are marked `io', pins 19 and 12 remain disconnected. It is important to understand that the keywords `in', `out', `io', and so forth are just symbolic names for pins, and that the precise pin assignment for each keyword depends upon the device. To find out precisely what keywords apply to the device you are using, you must consult the tables that follow. If you use keywords that are not defined for a device, or if you attach more signals to a keyword than available pins permit, the PLD compiler will register a complaint in the form of a fatal error message. Fuse array ---------- The last two lines of the table are less important for everyday use, since they represent the internal structure of the device, and since that structure is defined in data books. The line labelled Columns describes which pins are connected to input columns of the fuse array. As is typical for these devices, column 0 is connected through a buffer and column 1 is connected through an inverter. Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 : : : : : : Columns 3 and 4 Columns 30 and 31 : Columns 2 and 3 Columns 0 and 1 PROGRAMMABLE DEVICE REFERENCE TABLES Page 4 The line labelled Rows describes which pins are connected to output rows in the fuse array. Each row represents a product term. The pin number appears first, and it is followed by a parenthesized description of product terms. For the PAL16R6, the rows are defined like this: Rows 19(1t7) 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) 13(8R) 12(1t7) Each item has the following meaning. 19(1t7) Pin 19 has one tri-state and seven combinational product terms. 18(8R) Pin 18 has eight registered product terms. 17(8R) Pin 17 has eight registered product terms. 16(8R) Pin 16 has eight registered product terms. 15(8R) Pin 15 has eight registered product terms. 14(8R) Pin 14 has eight registered product terms. 13(8R) Pin 13 has eight registered product terms. 12(1t7) Pin 12 has one tri-state and seven combinational product terms. If you look at other device tables, you will see other possibilities: 25(1) Pin 25 has only one combinational product term. 19(1t16R) Pin 19 has one tri-state and 16 registered product terms. 23(2x2R) Pin 23 has an exclusive-or gate with two product terms on each input, and the output of the gate is registered. Each row in the device is numbered. Row numbering starts with zero for the first pin in the list and advances by the number of product terms in parentheses. Thus, for the PAL16R8, where each output pin has eight product terms total, row numbers advance by eight for each pin: Rows 19(1t7) 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) 13(8R) 12(1t7) : : : : : : : : : : : : : : : Rows 56-63 : : : : : : Rows 48-55 : : : : : Rows 40-47 : : : : Rows 32-39 : : : Rows 24-31 : : Rows 16-23 : Rows 8-15 Rows 0-7 With 64 rows and 32 columns, the PAL16R6 has 64x32 or 2048 fuses. Fuse 0 represents row 0, column 0; fuse 1 represents row 0, column 1; fuse 31 represents row 0, column 31; fuse 32 represents row 1, column 0; and so forth. In general, the fuse number in the main array is the row number times the number of columns per row plus the column number. Many devices, such as the PAL22V10, have additional configuration fuses outside the main array. PROGRAMMABLE DEVICE REFERENCE TABLES Page 5 2. GENERAL 20-SERIES DEVICES Twenty-pin devices with a complete array of fuses are referred to in these tables as the "general 20-series". Devices in this group usually have eight product terms available for each output, and most outputs include feedback into the array. Registers are available, for example in the PAL16R6, but these registers are hard-wired and cannot be bypassed to form combinational output. In all the tables that follow, backslash (\) at the end of a line indicates that the material continues on the next line. A number in brackets after the keyword Rows indicates the beginning number for programmable polarity fuses. |Type PAL16L8 |Activity 0 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 2 (out) 19 12 |Group 3 (io) 18 17 16 15 14 13 | |Columns 2 1 3 18 4 17 5 16 6 15 7 14 8 13 9 11 |Rows 19(1t7) 18(1t7) 17(1t7) 16(1t7) 15(1t7) 14(1t7) \ | 13(1t7) 12(1t7) |Type PAL16H8 |Activity 1 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 2 (out) 19 12 |Group 3 (io) 18 17 16 15 14 13 | |Columns 2 1 3 18 4 17 5 16 6 15 7 14 8 13 9 11 |Rows 19(1t7) 18(1t7) 17(1t7) 16(1t7) 15(1t7) 14(1t7) \ | 13(1t7) 12(1t7) |Type PAL16P8 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 2 (out) 19 12 |Group 3 (io) 18 17 16 15 14 13 | |Columns 2 1 3 18 4 17 5 16 6 15 7 14 8 13 9 11 |Rows[2048] 19(1t7) 18(1t7) 17(1t7) 16(1t7) 15(1t7) 14(1t7) \ | 13(1t7) 12(1t7) PROGRAMMABLE DEVICE REFERENCE TABLES Page 6 |Type PAL16LD8 |Activity 0 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 2 (out) 19 12 |Group 3 (io) 18 17 16 15 14 13 | |Columns 2 1 3 18 4 17 5 16 6 15 7 14 8 13 9 11 |Rows 19(8) 18(8) 17(8) 16(8) 15(8) 14(8) 13(8) 12(8) |Type PAL16HD8 |Activity 1 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 2 (out) 19 12 |Group 3 (io) 18 17 16 15 14 13 | |Columns 2 1 3 18 4 17 5 16 6 15 7 14 8 13 9 11 |Rows 19(8) 18(8) 17(8) 16(8) 15(8) 14(8) 13(8) 12(8) |Type PAL18P8 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 3 (io) 19 18 17 16 15 14 13 12 | |Columns 2 1 3 18 4 17 5 16 6 15 7 14 8 13 9 11 19 12 |Rows[2592] 19(1t8) 18(1t8) 17(1t8) 16(1t8) 15(1t8) 14(1t8) \ | 13(1t8) 12(1t8) |Type PAL16R4 |Activity 0 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 17 16 15 14 |Group 3 (io) 19 18 13 12 |Group 4 (clock) 1 |Group 5 (enable) 11 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 |Rows 19(1t7) 18(1t7) 17(8R) 16(8R) 15(8R) 14(8R) 13(1t7) 12(1t7) PROGRAMMABLE DEVICE REFERENCE TABLES Page 7 |Type PAL16R6 |Activity 0 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 18 17 16 15 14 13 |Group 3 (io) 19 12 |Group 4 (clock) 1 |Group 5 (enable) 11 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 |Rows 19(1t7) 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) 13(8R) 12(1t7) |Type PAL16R8 |Activity 0 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 19 18 17 16 15 14 13 12 |Group 4 (clock) 1 |Group 5 (enable) 11 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 |Rows 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) 13(8R) 12(8R) |Type PAL16RP4 |Activity 0 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 17 16 15 14 |Group 3 (io) 19 18 13 12 |Group 4 (clock) 1 |Group 5 (enable) 11 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 |Rows[2048] 19(1t7) 18(1t7) 17(8R) 16(8R) 15(8R) 14(8R) 13(1t7) 12(1t7) |Type PAL16RP6 |Activity 0 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 18 17 16 15 14 13 |Group 3 (io) 19 12 |Group 4 (clock) 1 |Group 5 (enable) 11 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 |Rows[2048] 19(1t7) 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) 13(8R) 12(1t7) PROGRAMMABLE DEVICE REFERENCE TABLES Page 8 |Type PAL16RP8 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 19 18 17 16 15 14 13 12 |Group 4 (clock) 1 |Group 5 (enable) 11 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 |Rows[2048] 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) 13(8R) 12(8R) PROGRAMMABLE DEVICE REFERENCE TABLES Page 9 3. SPECIAL 20-SERIES DEVICES Twenty-pin devices which are sparsely populated with fuses are referred to in these tables as the "special 20-series". Devices in this group usually have a limited number of product terms available for each output and the number of product terms often varies from pin to pin. Furthermore, feedback within the device is usually not available. When using these devices, be sure to study the tables that follow or the diagrams in your data books to make sure the devices are suitable for your applications. |Type PAL10L8 |Activity 0 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 2 (out) 19 18 17 16 15 14 13 12 | |Columns 2 1 3 4 5 6 7 8 9 11 |Rows 19(2) 18(2) 17(2) 16(2) 15(2) 14(2) 13(2) 12(2) |Type PAL10H8 |Activity 1 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 2 (out) 19 18 17 16 15 14 13 12 | |Columns 2 1 3 4 5 6 7 8 9 11 |Rows 19(2) 18(2) 17(2) 16(2) 15(2) 14(2) 13(2) 12(2) |Type PAL10P8 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 2 (out) 19 18 17 16 15 14 13 12 | |Columns 2 1 3 4 5 6 7 8 9 11 |Rows[320] 19(2) 18(2) 17(2) 16(2) 15(2) 14(2) 13(2) 12(2) |Type PAL12L6 |Activity 0 | |Group 1 (in) 1 2 19 3 4 5 6 7 8 9 12 11 |Group 2 (out) 18 17 16 15 14 13 | |Columns 2 1 3 19 4 5 6 7 8 12 9 11 |Rows 18(4) 17(2) 16(2) 15(2) 14(2) 13(4) PROGRAMMABLE DEVICE REFERENCE TABLES Page 10 |Type PAL12H6 |Activity 1 | |Group 1 (in) 1 2 19 3 4 5 6 7 8 9 12 11 |Group 2 (out) 18 17 16 15 14 13 | |Columns 2 1 3 19 4 5 6 7 8 12 9 11 |Rows 18(4) 17(2) 16(2) 15(2) 14(2) 13(4) |Type PAL12P6 | |Group 1 (in) 1 2 19 3 4 5 6 7 8 9 12 11 |Group 2 (out) 18 17 16 15 14 13 | |Columns 2 1 3 19 4 5 6 7 8 12 9 11 |Rows[384] 18(4) 17(2) 16(2) 15(2) 14(2) 13(4) |Type PAL14L4 |Activity 0 | |Group 1 (in) 1 2 19 3 18 4 5 6 7 8 13 9 12 11 |Group 2 (out) 17 16 15 14 | |Columns 2 1 3 19 4 18 5 6 7 13 8 12 9 11 |Rows 17(4) 16(4) 15(4) 14(4) |Type PAL14H4 |Activity 1 | |Group 1 (in) 1 2 19 3 18 4 5 6 7 8 13 9 12 11 |Group 2 (out) 17 16 15 14 | |Columns 2 1 3 19 4 18 5 6 7 13 8 12 9 11 |Rows 17(4) 16(4) 15(4) 14(4) |Type PAL14P4 | |Group 1 (in) 1 2 19 3 18 4 5 6 7 8 13 9 12 11 |Group 2 (out) 17 16 15 14 | |Columns 2 1 3 19 4 18 5 6 7 13 8 12 9 11 |Rows[448] 17(4) 16(4) 15(4) 14(4) PROGRAMMABLE DEVICE REFERENCE TABLES Page 11 |Type PAL16C1 |Activity 1 | |Group 1 (in) 1 2 19 3 18 4 17 5 6 7 14 8 13 9 12 11 |Group 2 (out) 16 | |Columns 2 1 3 19 4 18 5 17 6 14 7 13 8 12 9 11 |Rows 16(16) |Type PAL16L2 |Activity 0 | |Group 1 (in) 1 2 19 3 18 4 17 5 6 7 14 8 13 9 12 11 |Group 2 (out) 16 15 | |Columns 2 1 3 19 4 18 5 17 6 14 7 13 8 12 9 11 |Rows 16(8) 15(8) |Type PAL16H2 |Activity 1 | |Group 1 (in) 1 2 19 3 18 4 17 5 6 7 14 8 13 9 12 11 |Group 2 (out) 16 15 | |Columns 2 1 3 19 4 18 5 17 6 14 7 13 8 12 9 11 |Rows 16(8) 15(8) |Type PAL16P2 | |Group 1 (in) 1 2 19 3 18 4 17 5 6 7 14 8 13 9 12 11 |Group 2 (out) 16 15 | |Columns 2 1 3 19 4 18 5 17 6 14 7 13 8 12 9 11 |Rows[512] 16(8) 15(8) |Type PAL16N8 | |Pins 20 |Activity 0 | |Group 1 (in) 2 1 3 4 5 6 7 8 9 11 |Group 2 (out) 19 12 |Group 3 (io) 18 17 16 15 14 13 | |Columns 2 1 3 18 4 17 5 16 6 15 7 14 8 13 9 11 | |Rows 19(1t1) 18(1t1) 17(1t1) 16(1t1) \ | 15(1t1) 14(1t1) 13(1t1) 12(1t1) PROGRAMMABLE DEVICE REFERENCE TABLES Page 12 4. GENERAL 24-SERIES DEVICES Twenty-four pin devices with a complete array of fuses are referred to in these tables as the "general 24-series". Like their 20-pin counterparts, devices in this group usually have eight product terms available for each output, and most ouputs include feedback into the array. Registers are available, but are hard-wired here too. |Type PAL20L8 |Activity 0 | |Group 1 (in) 1 2 23 3 4 5 6 7 8 9 10 11 14 13 |Group 2 (out) 22 15 |Group 3 (io) 21 20 19 18 17 16 | |Columns 2 1 3 23 4 21 5 20 6 19 7 18 8 17 9 16 10 14 11 13 |Rows 22(1t7) 21(1t7) 20(1t7) 19(1t7) 18(1t7) 17(1t7) \ | 16(1t7) 15(1t7) |Type PAL20H8 |Activity 1 | |Group 1 (in) 1 2 23 3 4 5 6 7 8 9 10 11 14 13 |Group 2 (out) 22 15 |Group 3 (io) 21 20 19 18 17 16 | |Columns 2 1 3 23 4 21 5 20 6 19 7 18 8 17 9 16 10 14 11 13 |Rows 22(1t7) 21(1t7) 20(1t7) 19(1t7) 18(1t7) 17(1t7) \ | 16(1t7) 15(1t7) |Type PAL20P8 | |Group 1 (in) 1 2 23 3 4 5 6 7 8 9 10 11 14 13 |Group 2 (out) 22 15 |Group 3 (io) 21 20 19 18 17 16 | |Columns 2 1 3 23 4 21 5 20 6 19 7 18 8 17 9 16 10 14 11 13 |Rows[2560] 22(1t7) 21(1t7) 20(1t7) 19(1t7) 18(1t7) 17(1t7) \ | 16(1t7) 15(1t7) PROGRAMMABLE DEVICE REFERENCE TABLES Page 13 |Type PAL20R4 |Activity 0 | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 14 |Group 2 (out) 20 19 18 17 |Group 3 (io) 22 21 16 15 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows 22(1t7) 21(1t7) 20(8R) 19(8R) 18(8R) 17(8R) \ | 16(1t7) 15(1t7) |Type PAL20R6 |Activity 0 | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 14 |Group 2 (out) 21 20 19 18 17 16 |Group 3 (io) 22 15 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows 22(1t7) 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) \ | 16(8R) 15(1t7) |Type PAL20R8 |Activity 0 | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 14 |Group 2 (out) 22 21 20 19 18 17 16 15 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows 22(8R) 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) PROGRAMMABLE DEVICE REFERENCE TABLES Page 14 Unlike their 20-pin counterparts, the 24-pin registered devices with programmable polarity do not necessarily have the same internal fuse structure as the corresponding devices without programmable polarity. That is, ignoring the special polarity fuses, the fuse map for a PAL20RP4 is not necessarily identical to that of the PAL20R4. In particular, the PAL20RP4 may use pins 14 and 23 as input/output pins, whereas the PAL20R4 uses pins 14 and 23 as pure input pins. You must be sure whether your device uses 14 and 23 as pure input or as input/output and select the proper table. Tables with 14 and 23 as pure input pins end with the letter `I', as in PAL20RP4I. |Type PAL20RP4 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 20 19 18 17 |Group 3 (io) 23 22 21 16 15 14 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows[3440] 23(1t8) 22(1t8) 21(1t8) \ | 20(8R) 19(8R) 18(8R) 17(8R) \ | 16(1t8) 15(1t8) 14(1t8) |Type PAL20RP6 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 21 20 19 18 17 16 |Group 3 (io) 23 22 15 14 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows[3360] 23(1t8) 22(1t8) \ | 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) \ | 15(1t8) 14(1t8) |Type PAL20RP8 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 22 21 20 19 18 17 16 15 |Group 3 (io) 23 14 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows[3280] 23(1t8) \ | 22(8R) 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) \ | 14(1t8) PROGRAMMABLE DEVICE REFERENCE TABLES Page 15 |Type PAL20RP10 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 23 22 21 20 19 18 17 16 15 14 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows[3200] 23(8R) 22(8R) 21(8R) 20(8R) 19(8R) \ | 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) |Type PAL20RP4I | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 14 |Group 2 (out) 20 19 18 17 |Group 3 (io) 22 21 16 15 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows[2560] 22(1t7) 21(1t7) 20(8R) 19(8R) 18(8R) 17(8R) 16(1t7) 15(1t7) |Type PAL20RP6I | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 14 |Group 2 (out) 21 20 19 18 17 16 |Group 3 (io) 22 15 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows[2560] 22(1t7) 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) 15(1t7) |Type PAL20RP8I | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 14 |Group 2 (out) 22 21 20 19 18 17 16 15 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows[2560] 22(8R) 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) PROGRAMMABLE DEVICE REFERENCE TABLES Page 16 |Type PAL22P10 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 10 11 13 |Group 3 (io) 23 22 21 20 19 18 17 16 15 14 | |Columns 2 1 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 13 23 14 |Rows[3960] 23(1t8) 22(1t8) 21(1t8) 20(1t8) 19(1t8) \ | 18(1t8) 17(1t8) 16(1t8) 15(1t8) 14(1t8) The tables which follow handle devices like the PALR19L8 and PALT19L8, which have registers or latches on their input pins. Each table covers both the input registered (eg. R19L8) and input latched (eg. T19L8) device. By default, all registers are enabled and connected to the dedicated input clock pin. As described in the data books, these registers can be eliminated and converted to buffers. The conversion is done by programming a single architectural fuse located in each input macrocell. Following are the JEDEC fuse numbers to be programmed to convert registered/latched input to buffered input: Pin Column Type Fuse 2 0 Registered/Latched 2433 23 2 Registered/Latched 2432 3 4 Registered/Latched 2434 1 6 Combinational ---- 4 8 Registered/Latched 2435 5 12 Registered/Latched 2436 6 16 Registered/Latched 2437 7 20 Registered/Latched 2438 8 24 Registered/Latched 2439 9 28 Registered/Latched 2440 10 32 Registered/Latched 2441 13 34 Combinational ---- 11 36 Registered/Latched 2442 Fuses are set explicitly with statements of the form Fuses: { numbers -> state } For example, to leave fuses 2432 through 2436 intact and to program fuses 2437 through 2442, the following statement is included in the source. Fuses: { 2432 ~ 2436 -> 0 |Enable the buffer 2437 ~ 2442 -> 1 } |Enable the register/latch PROGRAMMABLE DEVICE REFERENCE TABLES Page 17 |Type PAL19L8 | |Pins 24 |Activity 0 | |Group 1 (in) 2 23 3 1 4 5 6 7 8 9 10 13 11 |Group 2 (out) 22 15 |Group 3 (io) 21 20 19 18 17 16 |Group 4 (clock) 14 | |Columns 2 23 3 1 4 21 5 20 6 19 7 18 \ | 8 17 9 16 10 13 11 | |Rows 22(1t7) 21(1t7) 20(1t7) 19(1t7) 18(1t7) \ | 17(1t7) 16(1t7) 15(1t7) The next three tables, which cover devices with registers on both input and output, have the same fuse assignment for converting input register/latches to buffers: Pin Column Type Fuse 2 0 Registered/Latched 2433 23 2 Registered/Latched 2432 3 4 Registered/Latched 2434 4 8 Registered/Latched 2435 5 12 Registered/Latched 2436 6 16 Registered/Latched 2437 7 20 Registered/Latched 2438 8 24 Registered/Latched 2439 9 28 Registered/Latched 2440 10 32 Registered/Latched 2441 11 36 Registered/Latched 2442 |Type PAL19R4 | |Pins 24 |Activity 0 | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 |Group 2 (out) 20 19 18 17 |Group 3 (io) 22 21 16 15 |Group 4 (clock) 1 14 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 \ | 8 17 9 16 10 15 11 | |Rows 22(1t7) 21(1t7) \ | 20(8R) 19(8R) 18(8R) 17(8R) \ | 16(1t7) 15(1t7) PROGRAMMABLE DEVICE REFERENCE TABLES Page 18 |Type PAL19R6 | |Pins 24 |Activity 0 | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 |Group 2 (out) 21 20 19 18 17 16 |Group 3 (io) 22 15 |Group 4 (clock) 1 14 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 \ | 8 17 9 16 10 15 11 | |Rows 22(1t7) \ | 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) \ | 15(1t7) |Type PAL19R8 | |Pins 24 |Activity 0 | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 |Group 2 (out) 22 21 20 19 18 17 16 15 |Group 4 (clock) 1 14 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 \ | 8 17 9 16 10 15 11 | |Rows 22(8R) 21(8R) 20(8R) 19(8R) \ | 18(8R) 17(8R) 16(8R) 15(8R) PROGRAMMABLE DEVICE REFERENCE TABLES Page 19 5. SPECIAL 24-SERIES DEVICES Twenty-four pin devices which are sparsely populated with fuses are referred to in these tables as the "special 24-series". Like the special 20-series, devices in this group usually have a limited number of product terms available for each output, the number of product terms often varies from pin to pin, and feedback within the device is usually not available. |Type PAL12L10 |Activity 0 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 10 11 13 |Group 2 (out) 23 22 21 20 19 18 17 16 15 14 | |Columns 2 1 3 4 5 6 7 8 9 10 11 13 |Rows 23(2) 22(2) 21(2) 20(2) 19(2) 18(2) 17(2) 16(2) 15(2) 14(2) |Type PAL12H10 |Activity 1 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 10 11 13 |Group 2 (out) 23 22 21 20 19 18 17 16 15 14 | |Columns 2 1 3 4 5 6 7 8 9 10 11 13 |Rows 23(2) 22(2) 21(2) 20(2) 19(2) 18(2) 17(2) 16(2) 15(2) 14(2) |Type PAL12P10 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 10 11 13 |Group 2 (out) 23 22 21 20 19 18 17 16 15 14 | |Columns 2 1 3 4 5 6 7 8 9 10 11 13 |Rows[480] 23(2) 22(2) 21(2) 20(2) 19(2) 18(2) 17(2) 16(2) 15(2) 14(2) |Type PAL14L8 |Activity 0 | |Group 1 (in) 1 2 23 3 4 5 6 7 8 9 10 11 14 13 |Group 2 (out) 22 21 20 19 18 17 16 15 | |Columns 2 1 3 23 4 5 6 7 8 9 10 14 11 13 |Rows 22(4) 21(2) 20(2) 19(2) 18(2) 17(2) 16(2) 15(4) PROGRAMMABLE DEVICE REFERENCE TABLES Page 20 |Type PAL14H8 |Activity 1 | |Group 1 (in) 1 2 23 3 4 5 6 7 8 9 10 11 14 13 |Group 2 (out) 22 21 20 19 18 17 16 15 | |Columns 2 1 3 23 4 5 6 7 8 9 10 14 11 13 |Rows 22(4) 21(2) 20(2) 19(2) 18(2) 17(2) 16(2) 15(4) |Type PAL14P8 | |Group 1 (in) 1 2 23 3 4 5 6 7 8 9 10 11 14 13 |Group 2 (out) 22 21 20 19 18 17 16 15 | |Columns 2 1 3 23 4 5 6 7 8 9 10 14 11 13 |Rows[560] 22(4) 21(2) 20(2) 19(2) 18(2) 17(2) 16(2) 15(4) |Type PAL16L6 |Activity 0 | |Group 1 (in) 1 2 23 3 22 4 5 6 7 8 9 10 15 11 14 13 |Group 2 (out) 21 20 19 18 17 16 | |Columns 2 1 3 23 4 22 5 6 7 8 9 15 10 14 11 13 |Rows 21(4) 20(4) 19(2) 18(2) 17(4) 16(4) |Type PAL16H6 |Activity 1 | |Group 1 (in) 1 2 23 3 22 4 5 6 7 8 9 10 15 11 14 13 |Group 2 (out) 21 20 19 18 17 16 | |Columns 2 1 3 23 4 22 5 6 7 8 9 15 10 14 11 13 |Rows 21(4) 20(4) 19(2) 18(2) 17(4) 16(4) |Type PAL16P6 | |Group 1 (in) 1 2 23 3 22 4 5 6 7 8 9 10 15 11 14 13 |Group 2 (out) 21 20 19 18 17 16 | |Columns 2 1 3 23 4 22 5 6 7 8 9 15 10 14 11 13 |Rows[640] 21(4) 20(4) 19(2) 18(2) 17(4) 16(4) PROGRAMMABLE DEVICE REFERENCE TABLES Page 21 |Type PAL18L4 |Activity 0 | |Group 1 (in) 1 2 23 3 22 4 21 5 6 7 8 9 16 10 15 11 14 13 |Group 2 (out) 20 19 18 17 | |Columns 2 1 3 23 4 22 5 21 6 7 8 16 9 15 10 14 11 13 |Rows 20(6) 19(4) 18(4) 17(6) |Type PAL18H4 |Activity 1 | |Group 1 (in) 1 2 23 3 22 4 21 5 6 7 8 9 16 10 15 11 14 13 |Group 2 (out) 20 19 18 17 | |Columns 2 1 3 23 4 22 5 21 6 7 8 16 9 15 10 14 11 13 |Rows 20(6) 19(4) 18(4) 17(6) |Type PAL18P4 | |Group 1 (in) 1 2 23 3 22 4 21 5 6 7 8 9 16 10 15 11 14 13 |Group 2 (out) 20 19 18 17 | |Columns 2 1 3 23 4 22 5 21 6 7 8 16 9 15 10 14 11 13 |Rows[720] 20(6) 19(4) 18(4) 17(6) |Type PAL20C1 |Activity 1 | |Group 1 (in) 1 2 23 3 22 4 21 5 20 6 7 8 17 9 16 10 15 11 14 13 |Group 2 (out) 19 18 | |Columns 2 1 3 23 4 22 5 21 6 20 7 17 8 16 9 15 10 14 11 13 |Rows 19(16) |Type PAL20L2 |Activity 0 | |Group 1 (in) 1 2 23 3 22 4 21 5 20 6 7 8 17 9 16 10 15 11 14 13 |Group 2 (out) 19 18 | |Columns 2 1 3 23 4 22 5 21 6 20 7 17 8 16 9 15 10 14 11 13 |Rows 19(8) 18(8) PROGRAMMABLE DEVICE REFERENCE TABLES Page 22 |Type PAL20H2 |Activity 1 | |Group 1 (in) 1 2 23 3 22 4 21 5 20 6 7 8 17 9 16 10 15 11 14 13 |Group 2 (out) 19 18 | |Columns 2 1 3 23 4 22 5 21 6 20 7 17 8 16 9 15 10 14 11 13 |Rows 19(8) 18(8) |Type PAL20P2 | |Group 1 (in) 1 2 23 3 22 4 21 5 20 6 7 8 17 9 16 10 15 11 14 13 |Group 2 (out) 19 18 | |Columns 2 1 3 23 4 22 5 21 6 20 7 17 8 16 9 15 10 14 11 13 |Rows[640] 19(8) 18(8) |Type PAL20L10 |Activity 0 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 10 11 13 |Group 2 (out) 23 14 |Group 3 (io) 22 21 20 19 18 17 16 15 | |Columns 2 1 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 13 |Rows 23(1t3) 22(1t3) 21(1t3) 20(1t3) 19(1t3) 18(1t3) \ | 17(1t3) 16(1t3) 15(1t3) 14(1t3) |Type PAL20H10 |Activity 1 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 10 11 13 |Group 2 (out) 23 14 |Group 3 (io) 22 21 20 19 18 17 16 15 | |Columns 2 1 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 13 |Rows 23(1t3) 22(1t3) 21(1t3) 20(1t3) 19(1t3) 18(1t3) \ | 17(1t3) 16(1t3) 15(1t3) 14(1t3) |Type PAL20P10 | |Group 1 (in) 1 2 3 4 5 6 7 8 9 10 11 13 |Group 2 (out) 23 14 |Group 3 (io) 22 21 20 19 18 17 16 15 | |Columns 2 1 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 13 |Rows[1600] 23(1t3) 22(1t3) 21(1t3) 20(1t3) 19(1t3) 18(1t3) \ | 17(1t3) 16(1t3) 15(1t3) 14(1t3) PROGRAMMABLE DEVICE REFERENCE TABLES Page 23 |Type PAL6L16 |Activity 0 | |Group 1 (in) 4 5 6 7 8 9 |Group 2 (out) 1 2 23 3 22 21 20 19 18 17 16 10 15 11 14 13 | |Columns 4 5 6 7 8 9 |Rows 1(1) 23(1) 2(1) 3(1) 22(1) 21(1) 20(1) 19(1) \ | 18(1) 17(1) 16(1) 10(1) 15(1) 14(1) 11(1) 13(1) |Type PAL8L14 |Activity 0 | |Group 1 (in) 3 4 5 6 7 8 9 10 |Group 2 (out) 1 2 23 22 21 20 19 18 17 16 15 11 14 13 | |Columns 3 4 5 6 7 8 9 10 |Rows 1(1) 23(1) 2(1) 22(1) 21(1) 20(1) 19(1) 18(1) \ | 17(1) 16(1) 15(1) 14(1) 11(1) 13(1) PROGRAMMABLE DEVICE REFERENCE TABLES Page 24 6. GENERAL 28-SERIES DEVICES The following twenty-eight pin devices are analagous to the general 20-series and 24-series devices, but with more input and output lines. Like their 20-pin and 24-pin counterparts, devices in this group usually have eight product terms available for each output, and most ouputs include feedback into the array. Hard-wired registers are available. |Type PAL24L10 |Activity 0 | |Group 1 (in) 1 28 2 27 3 4 5 6 8 9 10 11 12 13 14 15 |Group 2 (io) 25 24 23 22 20 19 18 17 |Group 3 (out) 26 16 |Group 4 (clock) 1 |Group 5 (enable) 15 | |Columns 2 28 3 27 4 1 5 25 6 24 8 23 9 22 \ | 10 20 11 19 12 18 13 17 14 15 | |Rows 26(1t7) \ | 25(1t7) 24(1t7) 23(1t7) 22(1t7) \ | 20(1t7) 19(1t7) 18(1t7) 17(1t7) \ | 16(1t7) | |VCC 7 |GND 21 |Type PAL24R10 |Activity 0 | |Group 1 (in) 28 2 27 3 4 5 6 8 9 10 11 12 13 14 |Group 2 (out) 26 25 24 23 22 20 19 18 17 16 |Group 4 (clock) 1 |Group 5 (enable) 15 | |Columns 2 28 3 27 4 26 5 25 6 24 8 23 9 22 \ | 10 20 11 19 12 18 13 17 14 16 | |Rows 26(8R) 25(8R) 24(8R) 23(8R) 22(8R) \ | 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) | |VCC 7 |GND 21 PROGRAMMABLE DEVICE REFERENCE TABLES Page 25 |Type PAL24R8 |Activity 0 | |Group 1 (in) 28 2 27 3 4 5 6 8 9 10 11 12 13 14 |Group 2 (out) 25 24 23 22 20 19 18 17 |Group 3 (io) 26 16 |Group 4 (clock) 1 |Group 5 (enable) 15 | |Columns 2 28 3 27 4 26 5 25 6 24 8 23 9 22 \ | 10 20 11 19 12 18 13 17 14 16 | |Rows 26(1t7) \ | 25(8R) 24(8R) 23(8R) 22(8R) 20(8R) 19(8R) 18(8R) 17(8R) \ | 16(1t7) | |VCC 7 |GND 21 |Type PAL24R6 |Activity 0 | |Group 1 (in) 28 2 27 3 4 5 6 8 9 10 11 12 13 14 |Group 2 (out) 24 23 22 20 19 18 |Group 3 (io) 26 25 17 16 |Group 4 (clock) 1 |Group 5 (enable) 15 | |Columns 2 28 3 27 4 26 5 25 6 24 8 23 9 22 \ | 10 20 11 19 12 18 13 17 14 16 | |Rows 26(1t7) 25(1t7) \ | 24(8R) 23(8R) 22(8R) 20(8R) 19(8R) 18(8R) \ | 17(1t7) 16(1t7) | |VCC 7 |GND 21 PROGRAMMABLE DEVICE REFERENCE TABLES Page 26 |Type PAL24R4 |Activity 0 | |Group 1 (in) 28 2 27 3 4 5 6 8 9 10 11 12 13 14 |Group 2 (out) 23 22 20 19 |Group 3 (io) 26 25 24 18 17 16 |Group 4 (clock) 1 |Group 5 (enable) 15 | |Columns 2 28 3 27 4 26 5 25 6 24 8 23 9 22 \ | 10 20 11 19 12 18 13 17 14 16 | |Rows 26(1t7) 25(1t7) 24(1t7) \ | 23(8R) 22(8R) 20(8R) 19(8R) \ | 18(1t7) 17(1t7) 16(1t7) | |VCC 7 |GND 21 PROGRAMMABLE DEVICE REFERENCE TABLES Page 27 7. SELECTABLE REGISTER DEVICES Tables in this group represent devices with simple selectable registers. That is, registers connected to output pins can either be used or bypassed. If bypassed, a purely combinational output results. With these devices, it is possible to create forms not otherwise available. For example, the equivalent of a PAL16R7 can be created, with seven registered outputs and one combinational output. The first table below represents a 20-pin device with eight input pins down the left-hand side, eight input/output pins down the right-hand side, power, ground, clock, and enable. Both clock and enable pins can be taken as normal inputs if not otherwise needed, giving ten inputs maximum. Internally each input/output pin has nine product terms available, one dedicated to tri-state enable, the others available for normal logic. All input/output pins can be programmed to be either active-high or active-low as well as combinational or registered. Registers are always low on power-up. In addition, two internal nodes can be programmed for asynchronous reset (node 21) and for synchronous preset (node 22). The device is considered to be active-high, since the two internal nodes are active-high. Twenty-four special fuses configure the device. The first fuse in a set corresponds to node 19, the second to node 18, and so forth. 2664~2671 Register bypass 0=registered 1=combinational 2672~2679 Polarity 0=active-low 1=active high 2680~2687 Enable 0=array enable 1=direct enable (pin 11) The device has two different tables available. The first table (PAL18U8) is used when at least one register is used. Input signals are then attached to pins 2 through 11, with the clock attached to pin 1. The second table (PAL18U8Z) may be used if no registers are programmed. Input signals are then attached to pins 1 through 11. The asterisk (*) on the row entries for nodes 21 and 22 indicate that those nodes are not subject to programmable polarity. PROGRAMMABLE DEVICE REFERENCE TABLES Page 28 |Type PAL18U8 | |Pins 20 |Activity 1 |Initialization L | |Group 1 (in) 2 3 4 5 6 7 8 9 11 |Group 3 (io) 19 18 17 16 15 14 13 12 |Group 4 (clock) 1 |Group 5 (enable) 11 |Group 6 (reset) 21 |Group 7 (preset) 22 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 1 11 | |Rows[2672] 19(1t8R) 18(1t8R) 17(1t8R) 16(1t8R) \ | 15(1t8R) 14(1t8R) 13(1t8R) 12(1t8R) \ | 21(1*) 22(1*) | |Register bypass[2664] 19 18 17 16 15 14 13 12 |Column inversion[=68] 19 18 17 16 15 14 13 12 |Type PAL18U8Z | |Pins 20 |Activity 1 |Initialization L | |Group 1 (in) 1 2 3 4 5 6 7 8 9 11 |Group 3 (io) 19 18 17 16 15 14 13 12 |Group 5 (enable) 11 |Group 6 (reset) 21 |Group 7 (preset) 22 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 1 11 | |Rows[2672] 19(1t8R) 18(1t8R) 17(1t8R) 16(1t8R) \ | 15(1t8R) 14(1t8R) 13(1t8R) 12(1t8R) \ | 21(1*) 22(1*) | |Register bypass[2664] 19 18 17 16 15 14 13 12 |Column inversion[=68] 19 18 17 16 15 14 13 12 PROGRAMMABLE DEVICE REFERENCE TABLES Page 29 The next device has programmable polarity and registers as well as internal nodes for asynchronous and synchronous reset, but this one has a larger number of product terms available for some pins as well as a larger number of output pins. However, the number of product pins varies from pin to pin. This works well for some applications such as counters, but the resulting pin assignment may not be ideal for layout and routing. Pin assignment can be done automatically by the PLD compiler on the PAL22V10. As an illustration, consider an 8-bit up/down counter, which requires 16 product terms for Q7, 14 product terms for Q6, down to 2 product terms for Q0. On the PAL22V10, some pins have 16 product terms, others have 14, and so forth, so the device is suitable for an 8-bit up/down counter, if only the pins are assigned properly. To start with, the signals Q[7..0] are assigned to the io pins in numeric order, without regard to the number of product terms needed or available. The configuration statement at the end of the source informs the compiler that signals Q[7..0] are unassigned. That is, the pins they are attached to are free to be changed. When this is compiled, therefore, signals Q[7..0] will be assigned by the compiler according to the number of product terms in their equations. The algorithm preserves as many of the original pin assignments as possible. For best results, this should be compiled with inversion off (/i0 on the command line). |PAL22V10 io:Q[7..0], in:(UP, RESET), clock:CLK | | i=7..1: Q[i] = CLK // RESET' & ( ((Q[i] ## Q[i-1..0]==-1) & UP) | # ((Q[i] ## Q[i-1..0]== 0) & UP') ) | | i=0: Q[i] = CLK // RESET' & (Q[i] ## 1) | | Configuration: "Unassigned", Q[7..0] | Reduction 1: Q[7..0] The reset and preset built into the chip are handled as special nodes numbered 25 and 26. They are named in the list of ports and programmed as signals hardwired to all other register nodes. For example, the following example has the reset node named ABR, and ABR is active when both A and B are active. This means that the registered signals X and Y will both be reset when A and B are simultaneously active. |PAL22V10 in:(A, B, C, D), io:(X, Y, Z), clock:CLK, reset:ABR | | ABR = A & B | | X = CLK // C & (D # E) | Y = CLK // C' # (D & E) | | Z = C ## D PROGRAMMABLE DEVICE REFERENCE TABLES Page 30 |Type PAL22V10 | |Pins 24 |Activity 1 |Initialization L |Overlay AUTOPIN | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 13 (1) |Group 3 (io) 23 22 21 20 19 18 17 16 15 14 |Group 4 (clock) (1) |Group 6 (reset) 25 |Group 7 (preset) 26 | |Columns 1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 10 14 11 13 | |Rows[5808(+2)] 25(1*) \ | 23(1t8R) 22(1t10R) 21(1t12R) 20(1t14R) 19(1t16R) \ | 18(1t16R) 17(1t14R) 16(1t12R) 15(1t10R) 14(1t8R) \ | 26(1*) | |Register bypass[5809(+2)] 23 22 21 20 19 18 17 16 15 14 |Column inversion[=68] 23 22 21 20 19 18 17 16 15 14 The table below, with an X at the end of the name, is the same as the one above except no automatic pin assignment is called for. If none is needed, and if the design is pushing the limits of memory, this table may be useful. It conserves memory by not calling the AUTOPIN.BIN overlay. |Type PAL22V10X | |Pins 24 |Activity 1 |Initialization L | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 13 (1) |Group 3 (io) 23 22 21 20 19 18 17 16 15 14 |Group 4 (clock) (1) |Group 6 (reset) 25 |Group 7 (preset) 26 | |Columns 1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 10 14 11 13 | |Rows[5808(+2)] 25(1*) \ | 23(1t8R) 22(1t10R) 21(1t12R) 20(1t14R) 19(1t16R) \ | 18(1t16R) 17(1t14R) 16(1t12R) 15(1t10R) 14(1t8R) \ | 26(1*) | |Register bypass[5809(+2)] 23 22 21 20 19 18 17 16 15 14 |Column inversion[=68] 23 22 21 20 19 18 17 16 15 14 PROGRAMMABLE DEVICE REFERENCE TABLES Page 31 Below is another representation of the same part, included only for compatibility with version 1.00 of the compiler. It can be used if no clock is required. Pin one appears first in the list. |Type PAL22V10Z | |Pins 24 |Activity 1 |Initialization L | |Group 1 (in) 1 2 3 4 5 6 7 8 9 10 11 13 |Group 3 (io) 23 22 21 20 19 18 17 16 15 14 |Group 6 (reset) 25 |Group 7 (preset) 26 | |Columns 1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 10 14 11 13 | |Rows[5808(+2)] 25(1*) \ | 23(1t8R) 22(1t10R) 21(1t12R) 20(1t14R) 19(1t16R) \ | 18(1t16R) 17(1t14R) 16(1t12R) 15(1t10R) 14(1t8R) \ | 26(1*) | |Register bypass[5809(+2)] 23 22 21 20 19 18 17 16 15 14 |Column inversion[=68] 23 22 21 20 19 18 17 16 15 14 PROGRAMMABLE DEVICE REFERENCE TABLES Page 32 8. GALs The GAL devices, which means Generic Array Logic devices, require special explanation (GAL is a registered trademark of Lattice Semiconductor). Some of these devices, such as GAL18V10, have more or less straightforward structure and can be treated much like the familiar PAL22V10. However, the GAL16V8, GAL20V8, and GAL16Z8 have several distinct modes of operation adapting them to be direct substitutes for the smaller PAL devices. These modes are called registered, complex, and simple; they are all explained in the manufacturer's data books. Automatic selection of modes ---------------------------- Briefly, registered mode is used for logic that would fit devices like PAL16R8, PAL16R6, and PAL16R4. It is needed whenever the logic employs edge-triggered registers, and also in some delicate feedback conditions. Complex mode is used for logic that would fit devices like PAL16L8. It can be used when the logic needs no registers but does need three-state gates. Simple mode is for logic that would fit in any of the small-scale devices like PAL14H6. The architectural complexity of the GAL devices is a consequence of the architectural diversity of the simple PAL devices. However, you do not have to keep all details of internal GAL structures in mind, because the architectural mode is selected automatically based on your specification. Some examples illustrate this. |GAL16V8 in:(A, B), io:Y[1..6] | | Y1 = A & B |And | Y2 = A # B |Or | Y3 = A ## B |Exclusive or | Y4 = A' |Not | Y5 = (A & B)' |Nand | Y6 = (A # B)' |Nor Above is an example of basic gates specified for a GAL16V8. When this example is compiled, the architectural phase examines the requirements, selects a mode, and indicates the selection with a short message on the screen. PROGRAMMABLE DEVICE REFERENCE TABLES Page 33 : 5. Reducing equations Signal Y1 Signal Y2 Signal Y3 Signal Y4 Signal Y5 Signal Y6 6. Configuring architectural fuses Complex GAL architecture selected. <--- Mode selection 7. Generating fuse array : Complex mode is selected here, based on the rules in the manufacturer's data books. Complex mode is the preferred mode; if several modes are possible, complex mode is the one selected. To see the modes change, some feedback can be added. First consider feedback on Y2. |GAL16V8 in:(A, B), io:Y[1..6] | | Y1 = A & B |And | Y2 = A # (B & Y2) |Or with feedback | Y3 = A ## B |Exclusive or | Y4 = A' |Not | Y5 = (A & B)' |Nand | Y6 = (A # B)' |Nor In the example above, the OR gate has been changed to a kind of SR flip-flop (see the PLD reference guide for an explanation of the SR flip-flop equation). When compiled, the same mode is selected. : 6. Configuring architectural fuses Complex GAL architecture selected. : However, see what happens with feedback on Y1 as well. |GAL16V8 in:(A, B), io:Y[1..6] | | Y1 = A & (B # Y1) |And with feedback | Y2 = A # (B & Y2) |Or with feedback | Y3 = A ## B |Exclusive or | Y4 = A' |Not | Y5 = (A & B)' |Nand | Y6 = (A # B)' |Nor PROGRAMMABLE DEVICE REFERENCE TABLES Page 34 This is still a kind of SR flip-flop, but with different polarity. When it is compiled, something new happens. : 6. Configuring architectural fuses Registered GAL architecture selected. [Complex mode cannot be used because input appears on macrocell 0.] : The device has switched to registered mode, even though no registers appear in the source. The reason is given in brackets: In complex mode, macrocell 0 has no input to the fuse array. This is the macrocell Y1 is attached to, which now feeds back into the array. Registered mode does support input on this macrocell, so registered mode is used instead. Whenever a mode is selected for reasons that may not be obvious, the compiler offers a short explanation of its decision. Sometimes none of the three modes will work, and the explanation becomes more elaborate. For instance, suppose separate input signals C through I are used for signals Y3 through Y6. |GAL16V8 in:(A, B, C, D, E, F, G, H, I), io:Y[1..6] | | Y1 = A & (B # Y1) |And with feedback | Y2 = A # (B & Y2) |Or with feedback | Y3 = C ## D |Exclusive or | Y4 = E' |Not | Y5 = (F & G)' |Nand | Y6 = (H # I)' |Nor Now the number of input signals allowed for registered mode has been exceeded, so this longer message appears. : 6. Configuring architectural fuses The GAL cannot be correctly configured. [Complex mode cannot be used because input appears on macrocell 0. Registered mode cannot be used because input appears on the enable line. Simple mode cannot be used because feedback is needed and this is neither an A nor a B part.] : None of the three modes will work here, so the compiler simply selects complex mode and proceeds. This leads to error messages where the logic does not fit, but you can still use the logic tester to see if the logic itself is correct. In this case, an error message like the following arises. E763 Signal Y1 is not input to the array. Because complex mode has been selected, and because complex mode has no feedback from macrocell 0, the compiler is notifying you that Y1 does not feed into the array. PROGRAMMABLE DEVICE REFERENCE TABLES Page 35 Registers and enables --------------------- The previous example shows automatic selection of registered mode, but does not show the use of registers themselves. To actually use registers, a clock signal is also needed. Suppose Y1 and Y5 are to be conditioned by a clock signal named CMAIN. Then three changes to the source code are required, marked with carets (^) below. |GAL16V8 in:(A, B), io:Y[1..6], clock:CMAIN | ^^^^^^^^^^^ | Y1 = CMAIN // A & B |Registered And ^^^^^^^^ | Y2 = A # B |Or | Y3 = A ## B |Exclusive or | Y4 = A' |Not | Y5 = CMAIN // (A & B)' |Registered Nand ^^^^^^^^ | Y6 = (A # B)' |Nor In this case, registered mode is selected, as expected, but no explanation is offered as to why complex mode was not. Because registers are actually in use, the compiler takes registered mode to be an obvious necessity and does not bother explaining why. : 6. Configuring architectural fuses Registered GAL architecture selected. : In the GAL16V8, each registered output is hardwired to a three-state enable gate connected to an enable signal on pin 11. If this pin is to be tied low, keeping the registers enabled at all times, then the specification shown above is correct. If pin 11 will be tied to a signal line that is active at some times and inactive at others, then it is best to define the operation more precisely. Suppose the enable signal is named BHEN and just the two registered signals are to be conditioned by enable. Then the changes to the source shown by carets below are needed. |GAL16V8 in:(A, B), io:Y[1..6], clock:CMAIN, enable:BHEN | ^^^^^^^^^^^ | Active-low: BHEN | ^^^^^^^^^^^^^^^^^ | Y1 = BHEN ?? CMAIN // A & B |Enabled/registered And ^^^^^^^ | Y2 = A # B |Or | Y3 = A ## B |Exclusive or | Y4 = A' |Not | Y5 = BHEN ?? CMAIN // (A & B)' |Enabled/registered Nand ^^^^^^^ | Y6 = (A # B)' |Nor PROGRAMMABLE DEVICE REFERENCE TABLES Page 36 The statement "Active-low: BHEN" is appropriate, for in the actual GAL device, the enable signal is hardwired to the registers through an inverter, and hence is always active when it is low. Furthermore, BHEN and CMAIN must be written in the order shown for signal Y1. The expression BHEN ?? CMAIN // A & B means that the output of the and gate is attached to a register and the output of the register is attached to the three-state enable gate. If it were written in the opposite order, like this, CMAIN // BHEN ?? A & B it would mean that the output of the and gate is attached to a three-state gate and the three-state output becomes the input to a register. That would be faulty because the GAL macrocells do not support such a configuration. (In any case, such a configuration is not really useful.) Another situation arises if both registered and nonregistered output must be conditioned by three-state enable. In the GAL architecture, three-state enable on registered macrocells are hardwired, whereas those on nonregistered macrocells eminate from the and/or array. Therefore, to enable nonregistered macrocells, the enable signal must be attached to a pin that enters the and/or array, and pin 11 is not such a pin. The changes marked by carets below will enable the nonregistered macrocell associated with Y2. |GAL16V8 in:(A, B, BHEN), io:Y[1..6], clock:CMAIN, enable:BHEN | ^^^^ | Active-low: BHEN | | Y1 = BHEN ?? CMAIN // A & B |Enabled/registered And | Y2 = BHEN ?? A # B |Enabled Or ^^^^^^^ | Y3 = A ## B |Exclusive or | Y4 = A' |Not | Y5 = BHEN ?? CMAIN // (A & B)' |Enabled/registered Nand | Y6 = (A # B)' |Nor See the appendix on pin assignment in the reference guide for further explanation. Please also study the manufacturer's data books for clarification of the internal structure of the and/or array, of the macrocells, and of the feedback paths. PROGRAMMABLE DEVICE REFERENCE TABLES Page 37 Forcing a specific mode ----------------------- In some cases, you may not want the compiler to select the mode, but instead want complete control yourself. The Configuration keyword, which is general for all device overlays, gives you that power. It has only three forms for GAL devices. Configuration: "Complex" Configuration: "Simple" Configuration: "Registered" Whenever one of these forms is used anywhere in the source code for a GAL, the configuration specified will be selected regardless of the structure of the equations. If the configuration is not right for the equations, then normal error messages will appear. Pin assignment -------------- Pin assignment for GAL devices is the same as for other devices, but because of the separate modes, some additional considerations arise. The introduction to this material explains the subject in general; the GAL16V8 is illustrated specifically here. The GAL16V8 table shows what pins are implied when the keywords in, out, and so forth are used. |Group 1 (in) 2 3 4 5 6 7 8 9 (11) (1) |Group 3 (io) 19 18 17 16 15 14 13 12 |Group 4 (clock) (1) |Group 5 (enable) (11) The first line, marked Group 1, describes which pins are assigned as input under the keyword `in'. The first signal named in the list is assigned to pin 2, the next to pin 3, and so forth. Parentheses surrounding pin numbers 1 and 11 mean that those pins can be assigned in more than one way. Pin 1, for example, can be used as input (in complex and simple mode) or as a clock signal (in registered mode). The way these pins are used helps the compiler determine the mode. The last example showed the following symbolic pin assignments. in:(A, B, BHEN), io:Y[1..6], clock:CMAIN, enable:BHEN There are only three signals under the `in' keyword, so these are assigned to the first three pins in the Group 1 list, like this. in:(A, B, BHEN) : : : Pin 2 3 4 PROGRAMMABLE DEVICE REFERENCE TABLES Page 38 Six signals are represented with the `io' keyword, shown expanded below and assigned to pins 19 through 14. io:(Y1, Y2, Y3, Y4, Y5, Y6), : : : : : : Pin 19 18 17 16 15 14 CMAIN is assigned to pin 1 clock:CMAIN : Pin 1 and BHEN to pin 11. (BHEN was previously also assigned to pin 4; this just means that pins 4 and 11 will be connected together on the circuit board.) enable:BHEN : Pin 11 The four lines for Group 1, 3, 4, and 5 in the table are equivalent to the following diagram. _____ ______ ___| |__| |__ clock/in10 |1 | |20| VCC ___| |__ in1 |2 | |19| io1 <- Macrocell 0 ___| |__ in2 |3 | |18| io2 <- Macrocell 1 ___| |__ in3 |4 | |17| io3 <- Macrocell 2 ___| |__ in4 |5 | |16| io4 <- Macrocell 3 ___| GAL16V8 |__ in5 |6 | |15| io5 <- Macrocell 4 ___| |__ in6 |7 | |14| io6 <- Macrocell 5 ___| |__ in7 |8 | |13| io7 <- Macrocell 6 ___| |__ in8 |9 | |12| io8 <- Macrocell 7 ___| |__ GND |10| |11| in9/enable |____________| The advantage of symbolic keywords over explicit pin numbers is that changing devices becomes easier. In any case, if you prefer explicit pin numbers, this example can be written as follows. 2:A, 3:B, 4:BHEN, 19..14:Y[1..6], 1:CMAIN, 11:BHEN PROGRAMMABLE DEVICE REFERENCE TABLES Page 39 Signatures ---------- Many GAL devices support electronic signatures. These are fuses not intended for programming the device but reserved for auxiliary information, such as the date the device was programmed, its revision level, the author's initials, or anything else. The signature is specified with a special keyword and can be given in the form of a character string or an integer, either hexadecimal or binary. Hexadecimal or binary signatures let you pack more information into the signature fuses; character signatures are usually easier to read. To store a character string as an electronic signature, one line is added to the source code. For example, Signature: "2/89 LAT" The text within quotation marks is converted to binary as an ASCII string and stored in the fuses reserved for electronic signatures. Some device programming machines will read and display the signature when presented with a programmed part or with a JEDEC file. Take the string "2/89 LAT" as an example. Reference to an ASCII chart shows the following values for individual characters. Char Dec Hex Binary "2" 50 32 00110010 "/" 47 2F 00101111 "8" 56 38 00111000 "9" 57 39 00111001 " " 32 20 00100000 "L" 76 4C 01001100 "A" 65 41 01000001 "T" 84 54 01010100 The binary signature can be stored as fuses in one of two ways. Characters are always stored left-to-right, but the bits that make them up can be stored either left-to-right or right-to-left. Which way you choose depends partly on what you are accustomed to and what your programming machine prefers. With left-to-right order, the fuses will appear in the JEDEC map like this. 00110010 00101111 00111000 00111001 00100000 01001100 ... : : : : : : "2" "/" "8" "9" " " "L" ... PROGRAMMABLE DEVICE REFERENCE TABLES Page 40 With right-to-left order, the characters keep their places, but the individual bits they comprise are reversed. 01001100 11110100 00011100 10011100 00000100 00110010 ... : : : : : : "2" "/" "8" "9" " " "L" ... Selection of the order can be made with the /B switch, as described in the user's guide. Signatures can also be entered as hexadecimal or binary integers. In this case, the number is padded to the left with the proper number of zeros before it is stored as signature fuses. Consider the following hexadecimal signature to be stored as a set of 64 signature fuses. Signature: 173C12B8330Fh It is first padded with zeros to make it 64 bits long. Since it contains twelve hexadecimal digits, or 48 bits, it must be padded with 16 more bits, or four hexadecimal zeros. Hex Binary Fuse offset 0 0000 0..3 0 0000 4..7 0 0000 8..11 0 0000 12..15 1 0001 16..19 7 0111 20..23 3 0011 24..27 C 1100 28..31 1 0001 32..35 2 0010 36..39 B 1011 40..43 8 1000 44..47 3 0011 48..51 3 0011 52..55 0 0000 56..59 F 1111 60..63 Now when it is stored the number is readable in the fuse map or the JEDEC file in the usual way. 0000 0000 0000 0000 0001 0111 0011 1100 0001 0010 1011 ... : : : : : : : : : : : 0 0 0 0 1 7 3 C 1 2 B ... PROGRAMMABLE DEVICE REFERENCE TABLES Page 41 If you select right-to-left storage (with the appropriate button or with the /B switch), the number is reversed, including its individual bits. This makes the number harder to read in the JEDEC file, but it may correspond more closely to the way you are accustomed to storing numbers in microcomputers. 1111 0000 1100 1100 0001 1101 0100 1000 0011 1100 1110 ... : : : : : : : : : : : F 0 3 3 8 B 2 1 C 3 7 ... You can use this information on the precise bit format as reference material in case you have trouble matching the requirements of your programming machine. |Type GAL16V8 | |Overlay GAL |Signature 2056(64) | |Pins 20 |Special fuses 146 |Initialization L |Inversion Off | |Group 1 (in) 2 3 4 5 6 7 8 9 (11) (1) |Group 3 (io) 19 18 17 16 15 14 13 12 |Group 4 (clock) (1) |Group 5 (enable) (11) | |Columns (Registered) 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 |Columns (Complex) 2 1 3 18 4 17 5 16 6 15 7 14 8 13 9 11 |Columns (Simple) 2 1 3 19 4 18 5 17 6 14 7 13 8 12 9 11 | |Rows[2048] 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) 13(8R) 12(8R) |Register bypass 19 18 17 16 15 14 13 12 PROGRAMMABLE DEVICE REFERENCE TABLES Page 42 |Type GAL16V8A | |Overlay GAL |Signature 2056(64) | |Pins 20 |Special fuses 146 |Initialization L |Inversion Off | |Group 1 (in) 2 3 4 5 6 7 8 9 (11) (1) |Group 3 (io) 19 18 17 16 15 14 13 12 |Group 4 (clock) (1) |Group 5 (enable) (11) | |Columns (Registered) 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 |Columns (Complex) 2 1 3 18 4 17 5 16 6 15 7 14 8 13 9 11 |Columns (Simple) 2 1 3 19 4 18 5 17 6 14 7 13 8 12 9 11 | |Rows[2048] 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) 14(8R) 13(8R) 12(8R) |Register bypass 19 18 17 16 15 14 13 12 |Type GAL20V8 | |Overlay GAL |Signature 2568(64) | |Pins 24 |Special fuses 146 |Initialization L |Inversion Off | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 14 (13) (1) |Group 2 (io) 22 21 20 19 18 17 16 15 |Group 4 (clock) (1) |Group 5 (enable) (13) | |Columns (Registered) 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Columns (Complex) 2 1 3 23 4 21 5 20 6 19 7 18 8 17 9 16 10 14 11 13 |Columns (Simple) 2 1 3 23 4 22 5 21 6 20 7 17 8 16 9 15 10 14 11 13 | |Rows[2560] 22(8R) 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) |Register bypass 22 21 20 19 18 17 16 15 PROGRAMMABLE DEVICE REFERENCE TABLES Page 43 |Type GAL20V8A | |Overlay GAL |Signature 2568(64) | |Pins 24 |Special fuses 146 |Initialization L |Inversion Off | |Group 1 (in) 2 23 3 4 5 6 7 8 9 10 11 14 (13) (1) |Group 2 (io) 22 21 20 19 18 17 16 15 |Group 4 (clock) (1) |Group 5 (enable) (13) | |Columns (Registered) 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Columns (Complex) 2 1 3 23 4 21 5 20 6 19 7 18 8 17 9 16 10 14 11 13 |Columns (Simple) 2 1 3 23 4 22 5 21 6 20 7 17 8 16 9 15 10 14 11 13 | |Rows[2560] 22(8R) 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) |Register bypass 22 21 20 19 18 17 16 15 |Type GAL16Z8 | |Overlay GAL |Signature 2056(64) |Object 1 | |Pins 24 |Special fuses 146 |Initialization L |Inversion Off | |Group 1 (in) 3 4 5 6 7 8 9 10 (13) (1) |Group 3 (io) 22 21 20 19 18 17 16 15 |Group 4 (clock) (1) |Group 5 (enable) (13) | |Columns (Registered) 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 |Columns (Complex) 3 1 4 21 5 20 6 19 7 18 8 17 9 16 10 13 |Columns (Simple) 3 1 4 22 5 21 6 20 7 17 8 16 9 15 10 13 | |Rows[2048] 22(8R) 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) |Register bypass 22 21 20 19 18 17 16 15 PROGRAMMABLE DEVICE REFERENCE TABLES Page 44 |Type GAL16Z8A | |Overlay GAL |Signature 2056(64) |Object 1 | |Pins 24 |Special fuses 146 |Initialization L |Inversion Off | |Group 1 (in) 3 4 5 6 7 8 9 10 (13) (1) |Group 3 (io) 22 21 20 19 18 17 16 15 |Group 4 (clock) (1) |Group 5 (enable) (13) | |Columns (Registered) 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 |Columns (Complex) 3 1 4 21 5 20 6 19 7 18 8 17 9 16 10 13 |Columns (Simple) 3 1 4 22 5 21 6 20 7 17 8 16 9 15 10 13 | |Rows[2048] 22(8R) 21(8R) 20(8R) 19(8R) 18(8R) 17(8R) 16(8R) 15(8R) |Register bypass 22 21 20 19 18 17 16 15 |Type GAL18V10 | |Pins 20 |Activity 1 |Initialization L |Signature 3476(64) |Special fuses 84 | |Group 1 (in) 2 3 4 5 6 7 8 (1) |Group 3 (io) 19 18 17 16 15 14 13 9 12 11 |Group 4 (clock) (1) |Group 6 (reset) 21 |Group 7 (preset) 22 | |Columns 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 11 9 | |Rows[3456(+2)] 21(1*) \ | 19(1t8R) 18(1t8R) 17(1t8R) 16(1t8R) 15(1t10R) \ | 14(1t10R) 13(1t8R) 12(1t8R) 11(1t8R) 9(1t8R) \ | 22(1*) | |Register bypass[3457(+2)] 19 18 17 16 15 14 13 12 11 9 |Column inversion[=68] 19 18 17 16 15 14 13 12 11 9 PROGRAMMABLE DEVICE REFERENCE TABLES Page 45 |Type GAL26CV12 | |Pins 28 |Activity 1 |Initialization L |Signature 6368(64) |Special fuses 88 | |Group 1 (in) 28 2 3 4 5 6 8 9 10 11 12 13 14 (1) |Group 3 (io) 27 26 25 24 23 22 20 19 18 17 16 15 |Group 4 (clock) (1) |Group 6 (reset) 29 |Group 7 (preset) 30 | |Columns 1 28 2 27 3 26 4 25 5 24 6 23 8 22 \ | 9 20 10 19 11 18 12 17 13 16 14 15 | |Rows[6344(+2)] 29(1*) \ | 27(1t8R) 26(1t8R) 25(1t8R) 24(1t8R) 23(1t10R) 22(1t12R) \ | 20(1t12R) 19(1t10R) 18(1t8R) 17(1t8R) 16(1t8R) 15(1t8R) \ | 30(1*) | |Register bypass[6345(+2)] 27 26 25 24 23 22 20 19 18 17 16 15 |Column inversion[=68] 27 26 25 24 23 22 20 19 18 17 16 15 | |GND 21 |VCC 7 PROGRAMMABLE DEVICE REFERENCE TABLES Page 46 9. RA DEVICES In the RA series, each output macrocell has a D flip-flop with three-state enable. The D input to the flip-flop is connected to a sum-of-products array (typically four product terms). Separate product terms are also reserved for the clock, for three-state enable, for asynchronous reset, and for asynchronous set (typically a single product term each). As shown in the databooks, the macrocell is structured so that the D flip-flop is bypassed if both the reset and the set terms are active simultaneously, rendering the macrocell a combinational logic element. With the OrCAD PLD compiler, it is not necessary to explicitly force the reset and set terms high to obtain combinational output; if no register is used in the source, then these two terms will be forced high automatically by the compiler. If a register is used in the source, however, then reset and set will be taken from any values specified in the dff function in the source. For example, to bypass the register in an RA device and obtain purely combinational logic, a normal logic statement like the following is used. | OUT = (A & B') # C If the three-state gate is to be used, then it is specified in the usual way. For example, this statement enables the output whenever EN1 and EN2 are both active: | OUT = EN1&EN2 ?? (A & B') # C To include the register in an RA device, a register is specified in the source, either with the rising edge operator (//) or with the dff function. Either of these is equivalent. | OUT = CLK&CLKEN // (A & B') # C | OUT = dff((A & B') # C, CLK&CLKEN) Three-state gates, if needed, are added with the three-state operator (??). | OUT = EN1&EN2 ?? CLK&CLKEN // (A & B') # C | OUT = EN1&EN2 ?? dff((A & B') # C, CLK&CLKEN) and reset and set are handled as usual for the dff function. | OUT = EN1&EN2 ?? dff((A & B') # C, CLK&CLKEN, RESET) Of course, if you specify a register and explicitly enable its reset and set terms, like this, | OUT = dff((A & B') # C, CLK&CLKEN, 1, 1) then the RA device has no choice but to behave combinationally. While this and other things like it will work, they are not good practice, for they lack portability to other series of devices. PROGRAMMABLE DEVICE REFERENCE TABLES Page 47 As explained in the reference guide, conditioning statements apply to logic synthesized from numerical maps, streams, truth tables, state machines, and so forth. Here is an example. |PAL16RA8 in:(A[2..0], CLK, LOAD, CLR, SET, G2), io:QA[0..2] | | Conditioning: G2 ?? dff(QA[2..0], CLK, CLR, SET) | | Map: QA[2..0] -> QA[2..0] | { n -> n+1, LOAD' | n -> A[2..0], LOAD } |Type PAL16RA8 |Activity 0 |Initialization H | |Pins 20 |Special fuses 8 |Register bypass RA | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 3 (io) 19 18 17 16 15 14 13 12 |Group 4 (clock) 1 |Group 5 (enable) 11 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 | |Rows[2048] 19(tcrs4R) 18(tcrs4R) 17(tcrs4R) 16(tcrs4R) \ | 15(tcrs4R) 14(tcrs4R) 13(tcrs4R) 12(tcrs4R) |Type PAL20RA10 |Activity 0 |Initialization H | |Pins 24 |Special fuses 10 |Register bypass RA | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 3 (io) 23 22 21 20 19 18 17 16 15 14 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 \ | 7 18 8 17 9 16 10 15 11 14 | |Rows[3200] 23(tcrs4R) 22(tcrs4R) 21(tcrs4R) 20(tcrs4R) 19(tcrs4R) \ | 18(tcrs4R) 17(tcrs4R) 16(tcrs4R) 15(tcrs4R) 14(tcrs4R) PROGRAMMABLE DEVICE REFERENCE TABLES Page 48 10. EP DEVICES The EP devices include the EP300, EP600, EP900, and the EP1800 families. They range from small devices that replace 16-pin PALs to much larger devices with 68 pins and 48 output macrocells. The databooks published by the manufacturers contain material needed to understand the operation of these devices. Further notes here describe how to apply the OrCAD PLD compiler once you understand them. EP300 series ------------ The EP300/310 usually needs no special attention. It has nine product terms, one of them dedicated to three-state enable. Feedback into the array can come either from the pin, from the output of the register, or directly from the output of the array. Normally, if you do nothing special, the compiler will automatically take feedback from the pin for combinational logic and from the output of the register for sequential logic. This is compatible with the operation of simpler PAL devices. In other words, just using the EP300/310 in the normal way will lead to the expected results. If you want to change the way feedback normally works, for example to take feedback from the array, then one or more configuration statements are needed in the source. The configuration statements contain conditions and lists of signals to which the conditions apply. For example, to take feedback directly from the array for signals Z[3..0] and from the pins for signals Q and S, these two configuration statements are placed in the source: | Configuration: "Array feedback", Z[3..0] | Configuration: "Pin feedback", Q, S The keywords (e.g., Array feedback) may be upper or lower case as you choose, but they must be enclosed in quotation marks ("), must be followed by a comma and a list of signals, and must be spelled correctly. There are only three feedback keywords: Pin feedback Register feedback Array feedback In addition to selectable feedback, macrocells on the EP300/310 have one global asynchronous reset term and one global synchronous preset term. (Notice that one is asynchronous, the other synchronous.) These are two additional product terms coming from the array and feeding the flip-flop in each macrocell. Because the reset and preset lines are global, they are handled specially, the same way similar lines are handled in devices like the PAL22V10. To employ the additional reset and preset product terms, you must do two things in the source: 1. Code the term reset or preset (or both) at the beginning of the source followed by an internal signal name you want to use to define the reset or preset condition. PROGRAMMABLE DEVICE REFERENCE TABLES Page 49 2. Write an equation that has the internal signal name at the left and the reset or preset conditions on the right. Keep in mind that the reset or preset conditions must reduce to a single product term. Consider, for example, a six-bit counter that should be reset asynchronously when signal RESET is active and signal WAIT is inactive. The following code will do. |EP310 in:(RESET, WAIT, MODE), | io:(Q[5..0], WMODE), | clock:CLK, reset:BEGIN | | WMODE = MODE & WAIT | BEGIN = RESET & WAIT' | | Registers: CLK // Q[5..0] | Map: Q[5..0] -> Q[5..0] { n -> n+1 } In this example, Q[5..0] use registers and WMODE is combinational. Since BEGIN is defined to be a reset signal (reset:BEGIN), when BEGIN is active, all registers will be reset, regardless of the state of CLK. WMODE is combinational, so the condition of BEGIN has no effect on it. |Type EP310 |Overlay EP300 |Activity 1 | |Pins 20 |Special fuses 56 | |Group 1 (in) 2 3 4 5 6 7 8 9 11 (1) |Group 3 (io) 19 18 17 16 15 14 13 12 |Group 4 (clock) (1) |Group 6 (reset) 21 |Group 7 (preset) 22 | |Columns[-] 1 11 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 | |Rows 19(8,tR) 18(8,tR) 17(8,tR) 16(8,tR) \ | 15(8,tR) 14(8,tR) 13(8,tR) 12(8,tR) \ | 22(1*) 21(1*) | |Register bypass 19 18 17 16 15 14 13 12 EP320 series ------------ The EP320/330 is simpler than the EP300/310, lacking the selectable feedback and the global set and reset terms. Feedback is hardwired to come from the pin for combinational output and from the register for sequential output, in the typical way. On the other hand, the EP320 has special bits called turbo bits and miser bits, described in the databooks. By default, the PROGRAMMABLE DEVICE REFERENCE TABLES Page 50 PLD compiler sets the turbo bits to 0 and the miser bits to 1 in the JEDEC file, but their values can be changed in a configuration statement. For example, to set the turbo bits to 1 and the miser bits to 0, use a statement like this in the source. | Configuration: "Turbo:1 Miser:0" In this case, no list of signals follows the configuration statement, for the statement applies to the entire device, not just to specific signals. |Type EP320 |Overlay EP300 | |Activity 1 |Special fuses 324 | |Group 1 (in) 2 3 4 5 6 7 8 9 11 (1) |Group 3 (io) 19 18 17 16 15 14 13 12 |Group 4 (clock) (1) | |Columns[-] 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 | |Rows 19(8,tR) 18(8,tR) 17(8,tR) 16(8,tR) \ | 15(8,tR) 14(8,tR) 13(8,tR) 12(8,tR) | |Register bypass 19 18 17 16 15 14 13 12 |Type EP330 |Overlay EP300 | |Activity 1 |Special fuses 324 | |Group 1 (in) 2 3 4 5 6 7 8 9 11 (1) |Group 3 (io) 19 18 17 16 15 14 13 12 |Group 4 (clock) (1) | |Columns[-] 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 | |Rows 19(8,tR) 18(8,tR) 17(8,tR) 16(8,tR) \ | 15(8,tR) 14(8,tR) 13(8,tR) 12(8,tR) | |Register bypass 19 18 17 16 15 14 13 12 PROGRAMMABLE DEVICE REFERENCE TABLES Page 51 EP600 and EP900 series ---------------------- Devices in the EP600/900 class are similar in structure. Output macrocells can be configured to be combinational, D flip-flops, or T flip-flops. (The databooks also show JK flip-flops and a synchronous kind of SR flip-flops as options, but these are not hardwired; they are merely implemented as D or T flip-flops with the right kind of feedback.) Each macrocell has eight product terms, its own asynchronous reset term, and a combination clock/enable term. Feedback is selectable either from the pin or from the output of the register. Feedback directly from the array is not available. As in the EP300/310, the compiler automatically takes feedback from the pin for combinational logic and from the register for sequential logic. To override the automatic selection, the feedback keywords are used in the same way as on the EP300/310. For example, to take feedback from the pins for signals Q and S, this configuration statement is placed in the source: | Configuration: "Pin feedback", Q, S Selection of combinational, D flip-flop, or T flip-flop is made by the compiler, based on the form of the source. Either the rising edge operator (//) or the function dff will select D flip-flops, the function tff will select T flip-flops, and the absence of any such notation will select combinational output. Clocking terms can be taken either from the array (if no three-state enable term is used for the macrocell) or from a clock pin hardwired to the macrocell, as detailed in the databooks. Fuses controlling the source of the clock are configured automatically by the compiler on the basis of the name of the clock signal and the pins it is attached to. If both clock and three-state enable must come from the array, the compiler will display an error message to inform you of the problem. Three types of pins are used when describing signals at the beginning of the source, the exact assignments of which are given in the tables that follow. Keyword `in' identifies pure input pins, of which the EP600 has four and the EP900 has twelve; keyword `io' identifies input/output macrocells, of which the EP600 has sixteen and the EP900 has twenty-four; and keyword `clock' identifies clock input pins, of which both devices have two. Here is a short example of a 24-bit registered decoder (not recommended as efficient use of an EP900, but given as an illustration of how the signals are connected). The five input signals D[4..0] carry a binary number n in the range 0 to 23. This number is decoded and the nth output line Q[n] is activated on the next rising edge (provided EN is also active). |EP900c in:(D[4..0], EN), io:Q[23..0], clock:(CLK, CLK) | | n=23..0: Q[n] = EN ?? CLK // D[4..0]==n The PLD reference guide explains how such a compact indexed equation can define such a large decoder. The only thing special in this case is that the signal CLK must be attached to both clock pins; CLK is used in all 24 PROGRAMMABLE DEVICE REFERENCE TABLES Page 52 macrocells, but each clock pin only reaches 12 of the macrocells. As an alternative, the clock could be drawn from the array by attaching it to one of the input lines, but because of restrictions within the device, the three-state enable term would then be unavailable. The source would look like this: |EP900c in:(D[4..0], CLK), io:Q[23..0] | | n=23..0: Q[n] = CLK // D[4..0]==n The `c' after the name, by the way, signifies the square JLCC package rather than the dip (dual in-line package). Pin numbering differs between the two package types, which affects any test vectors. Parts in this series also have turbo bits, which by default are set to zero in the JEDEC file. Their values can be changed with a configuration statement like this: | Configuration: "Turbo:1" |Type EP600 |Overlay EP900 | |Pins 24 |Special fuses 82 | |Group 1 (in) 2 23 11 14 |Group 3 (io) 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 |Group 4 (clock) 1 13 | |Columns[-] 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 | |Rows[6400(+5),6404(+5)] \ | 22(8,rtR) 21(8,rtR) 20(8,rtR) 19(8,rtR) \ | 18(8,rtR) 17(8,rtR) 16(8,rtR) 15(8,rtR) \ | 3(8,rtR) 4(8,rtR) 5(8,rtR) 6(8,rtR) \ | 7(8,rtR) 8(8,rtR) 9(8,rtR) 10(8,rtR) PROGRAMMABLE DEVICE REFERENCE TABLES Page 53 |Type EP600c |Overlay EP900 | |Pins 28 |Special fuses 82 | |Group 1 (in) 3 27 13 17 |Group 3 (io) 4 26 5 25 6 24 7 23 8 22 9 21 10 20 12 18 |Group 4 (clock) 2 16 | |Columns[-] 3 4 5 6 7 8 9 10 12 13 17 18 20 21 22 23 24 25 26 27 | |Rows[6400(+5),6404(+5)] \ | 26(8,rtR) 25(8,rtR) 24(8,rtR) 23(8,rtR) \ | 22(8,rtR) 21(8,rtR) 20(8,rtR) 18(8,rtR) \ | 4(8,rtR) 5(8,rtR) 6(8,rtR) 7(8,rtR) \ | 8(8,rtR) 9(8,rtR) 10(8,rtR) 12(8,rtR) | |VCC 1 28 |GND 14 15 |Type EP610 |Overlay EP900 | |Pins 24 |Special fuses 82 | |Group 1 (in) 2 23 11 14 |Group 3 (io) 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 |Group 4 (clock) 1 13 | |Columns[-] 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 | |Rows[6400(+5),6404(+5)] \ | 22(8,rtR) 21(8,rtR) 20(8,rtR) 19(8,rtR) \ | 18(8,rtR) 17(8,rtR) 16(8,rtR) 15(8,rtR) \ | 3(8,rtR) 4(8,rtR) 5(8,rtR) 6(8,rtR) \ | 7(8,rtR) 8(8,rtR) 9(8,rtR) 10(8,rtR) PROGRAMMABLE DEVICE REFERENCE TABLES Page 54 |Type EP610c |Overlay EP900 | |Pins 28 |Special fuses 82 | |Group 1 (in) 3 27 13 17 |Group 3 (io) 4 26 5 25 6 24 7 23 8 22 9 21 10 20 12 18 |Group 4 (clock) 2 16 | |Columns[-] 3 4 5 6 7 8 9 10 12 13 17 18 20 21 22 23 24 25 26 27 | |Rows[6400(+5),6404(+5)] \ | 26(8,rtR) 25(8,rtR) 24(8,rtR) 23(8,rtR) \ | 22(8,rtR) 21(8,rtR) 20(8,rtR) 18(8,rtR) \ | 4(8,rtR) 5(8,rtR) 6(8,rtR) 7(8,rtR) \ | 8(8,rtR) 9(8,rtR) 10(8,rtR) 12(8,rtR) | |VCC 1 28 |GND 14 15 |Type EP630 |Overlay EP900 | |Pins 24 |Special fuses 82 | |Group 1 (in) 2 23 11 14 |Group 3 (io) 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 |Group 4 (clock) 1 13 | |Columns[-] 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 | |Rows[6400(+5),6404(+5)] \ | 22(8,rtR) 21(8,rtR) 20(8,rtR) 19(8,rtR) \ | 18(8,rtR) 17(8,rtR) 16(8,rtR) 15(8,rtR) \ | 3(8,rtR) 4(8,rtR) 5(8,rtR) 6(8,rtR) \ | 7(8,rtR) 8(8,rtR) 9(8,rtR) 10(8,rtR) PROGRAMMABLE DEVICE REFERENCE TABLES Page 55 |Type EP630c |Overlay EP900 | |Pins 28 |Special fuses 82 | |Group 1 (in) 3 27 13 17 |Group 3 (io) 4 26 5 25 6 24 7 23 8 22 9 21 10 20 12 18 |Group 4 (clock) 2 16 | |Columns[-] 3 4 5 6 7 8 9 10 12 13 17 18 20 21 22 23 24 25 26 27 | |Rows[6400(+5),6404(+5)] \ | 26(8,rtR) 25(8,rtR) 24(8,rtR) 23(8,rtR) \ | 22(8,rtR) 21(8,rtR) 20(8,rtR) 18(8,rtR) \ | 4(8,rtR) 5(8,rtR) 6(8,rtR) 7(8,rtR) \ | 8(8,rtR) 9(8,rtR) 10(8,rtR) 12(8,rtR) | |VCC 1 28 |GND 14 15 |Type EP900 |Overlay EP900 | |Pins 40 |Special fuses 122 | |Group 1 (in) 2 39 3 38 4 37 17 24 18 23 19 22 |Group 3 (io) 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 \ | 13 28 14 27 15 26 16 25 |Group 4 (clock) 1 21 | |Columns[-] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 \ | 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | |Rows[17280(+5),17284(+5)] \ | 36(8,rtR) 35(8,rtR) 34(8,rtR) 33(8,rtR) \ | 32(8,rtR) 31(8,rtR) 30(8,rtR) 29(8,rtR) \ | 28(8,rtR) 27(8,rtR) 26(8,rtR) 25(8,rtR) \ | 5(8,rtR) 6(8,rtR) 7(8,rtR) 8(8,rtR) \ | 9(8,rtR) 10(8,rtR) 11(8,rtR) 12(8,rtR) \ | 13(8,rtR) 14(8,rtR) 15(8,rtR) 16(8,rtR) PROGRAMMABLE DEVICE REFERENCE TABLES Page 56 |Type EP900c |Overlay EP900 | |Pins 44 |Special fuses 122 | |Group 1 (in) 3 43 4 42 5 41 19 27 20 26 21 25 |Group 3 (io) 6 40 7 38 8 37 9 36 10 35 11 34 12 33 13 32 \ | 14 31 15 30 16 29 18 28 |Group 4 (clock) 2 24 | |Columns[-] 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 \ | 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 41 42 43 | |Rows[17280(+5),17284(+5)] \ | 40(8,rtR) 38(8,rtR) 37(8,rtR) 36(8,rtR) \ | 35(8,rtR) 34(8,rtR) 33(8,rtR) 32(8,rtR) \ | 31(8,rtR) 30(8,rtR) 29(8,rtR) 28(8,rtR) \ | 6(8,rtR) 7(8,rtR) 8(8,rtR) 9(8,rtR) \ | 10(8,rtR) 11(8,rtR) 12(8,rtR) 13(8,rtR) \ | 14(8,rtR) 15(8,rtR) 16(8,rtR) 18(8,rtR) | |VCC 1 44 |GND 22 23 |Type EP910 |Overlay EP900 | |Pins 40 |Special fuses 122 | |Group 1 (in) 2 39 3 38 4 37 17 24 18 23 19 22 |Group 3 (io) 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 \ | 13 28 14 27 15 26 16 25 |Group 4 (clock) 1 21 | |Columns[-] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 \ | 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | |Rows[17280(+5),17284(+5)] \ | 36(8,rtR) 35(8,rtR) 34(8,rtR) 33(8,rtR) \ | 32(8,rtR) 31(8,rtR) 30(8,rtR) 29(8,rtR) \ | 28(8,rtR) 27(8,rtR) 26(8,rtR) 25(8,rtR) \ | 5(8,rtR) 6(8,rtR) 7(8,rtR) 8(8,rtR) \ | 9(8,rtR) 10(8,rtR) 11(8,rtR) 12(8,rtR) \ | 13(8,rtR) 14(8,rtR) 15(8,rtR) 16(8,rtR) PROGRAMMABLE DEVICE REFERENCE TABLES Page 57 |Type EP910c |Overlay EP900 | |Pins 44 |Special fuses 122 | |Group 1 (in) 3 43 4 42 5 41 19 27 20 26 21 25 |Group 3 (io) 6 40 7 38 8 37 9 36 10 35 11 34 12 33 13 32 \ | 14 31 15 30 16 29 18 28 |Group 4 (clock) 2 24 | |Columns[-] 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 \ | 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 41 42 43 | |Rows[17280(+5),17284(+5)] \ | 40(8,rtR) 38(8,rtR) 37(8,rtR) 36(8,rtR) \ | 35(8,rtR) 34(8,rtR) 33(8,rtR) 32(8,rtR) \ | 31(8,rtR) 30(8,rtR) 29(8,rtR) 28(8,rtR) \ | 6(8,rtR) 7(8,rtR) 8(8,rtR) 9(8,rtR) \ | 10(8,rtR) 11(8,rtR) 12(8,rtR) 13(8,rtR) \ | 14(8,rtR) 15(8,rtR) 16(8,rtR) 18(8,rtR) | |VCC 1 44 |GND 22 23 EP1800 series ------------- When the level of the EP1800 is reached, the options have increased. There are 48 macrocells divided into four quadrants, with local feedback among all members of a quadrant and global feedback among some members. The macrocells with global feedback also have a local feedback path that allows them to be used as a buried registers. All this is explained in the databooks; the purpose here is only to show how to access these features with the OrCAD PLD compiler. Inspection of the tables for the EP1800/1810/1830 series shows the three types of ports available in earlier series (in, io, and clock), but shows five additional types as well (ioa, iob, ioc, iod, and internal): Type of Number of Type of port pins signal in 12 Pure input signals. io 16 Output of global macrocells. clock 4 Input signals with clock. ioa 8 Quadrant A local macrocells. iob 8 Quadrant B local macrocells. ioc 8 Quadrant C local macrocells. iod 8 Quadrant D local macrocells. internal 16 Buried local feedback from global macrocells. PROGRAMMABLE DEVICE REFERENCE TABLES Page 58 The twelve `in' ports are easy; they represent the pure input pins. The sixteen `io' ports represent the pins attached to the macrocells with global feedback; they therefore behave like the io ports of the EP600/900 series. The four `clock' ports carry clock signals to the four quadrants, but unlike the earlier series, these clock ports also act as normal global input ports. The ports labelled `ioa', `iob', `ioc', and `iod' represent the 32 local macrocells in quadrants A, B, C, and D respectively. Their use is relatively simple, the only restriction being that any feedback such a cell provides must be used within its own quadrant. Any attempt to use local feedback outside the applicable quadrant will generate an error message. The ports labelled internal represent local internal feedback of the global macrocells (the ones whose pins are represented by `io'). If one of the signals defined as `io' is used purely as input, then an entirely different signal can be defined as `internal' in the corresponding position. The internal signal is treated as a normal signal with feedback to its local quadrant, but it is connected to no real pin. Internal node numbers in the range 69 through 84 are used instead of real pin numbers. (The EP1800/1810/1830 has 68 pins, so any pin numbers above 68 represent internal nodes.) The macrocell associated with the internal node is said to be buried. Below is a table of pin numbers associated with each type of port. As described in the PLD reference guide and in the introduction at the beginning of this material, signals attached to each type of port are assigned pin numbers from left to right. Remember that, in this device, numbers 69 through 84 represent internal nodes rather than real pins. Type Pin numbers in 14 15 16 20 21 22 48 49 50 54 55 56 io 10 11 12 13 23 24 25 26 44 45 46 47 57 58 59 60 internal 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 clock 17 19 51 53 ioa 2 3 4 5 6 7 8 9 iob 27 28 29 30 31 32 33 34 ioc 36 37 38 39 40 41 42 43 iod 61 62 63 64 65 66 67 68 As a simple example, here is the decode shown earlier, now expanded to 48 bits. (Again, this is not proposed as an efficient use of an EP1810.) The six input signals D[5..0] carry a binary number n in the range 0 to 47. This number is decoded and the nth output line Q[n] is activated on the next rising edge (provided EN is also active). PROGRAMMABLE DEVICE REFERENCE TABLES Page 59 |EP1810c in:(D[5..0], EN), | io: Q[47..32], | ioa:Q[31..24], | iob:Q[23..16], | ioc:Q[15..8], | iod:Q[7..0], | clock:(CLK, CLK, CLK, CLK) | | n=47..0: Q[n] = EN ?? CLK // D[4..0]==n The only fundamental difference between this version for the EP1810c and the version shown earlier for the EP900c is that the 48 output signals are divided among various sets of input/output ports. The only problem with locality arises with the signal CLK, which is attached to four separate clock pins to let it reach all quadrants directly. If it were not so attached, it could still reach all quadrants through the array, but the use of the enable signal EN would then be affected, since it also comes from the array. For an example using internal nodes, consider a four-bit counter with signals Q[3..0] attached to the global macrocells of Quadrant A. Suppose only a signal telling when the counter reaches zero is needed, not the actual output of the counter itself. Therefore, the pins attached to the global macrocells are not needed for output of the counter and instead can be used for input signals D[3..0] to load the counter. On each clock cycle, the counter decrements by one until it reaches zero, when it stops decrementing. The combinational output signal ZERO in Quadrant A becomes active when the counter reaches zero. When the example is coded as shown below, the compiler assigns signals D3, D2, D1, and D0 to pins 10, 11, 12, and 13, respectively, but assigns signals Q3, Q2, Q1, and Q0 to the local feedback paths of the macrocells for those same pins. |EP1810c in:(CLK, LOAD), ioa:ZERO, | io:D[3..0], internal:Q[3..0] | | ZERO = Q[3..0]==0 | | Map: Q[3..0] -> Q[3..0] | { n -> n-1, LOAD' & n>0 | n -> 0, LOAD' & n==0 | n -> D[3..0], LOAD } | | Registers: CLK // Q[3..0] PROGRAMMABLE DEVICE REFERENCE TABLES Page 60 |Type EP1800c |Overlay EP1800 | |Pins 68 |Special fuses 250 |Activity 1 | |Group 1 (in) 14 15 16 20 21 22 \ |Pure input signals. | 48 49 50 54 55 56 | |Group 4 (clock) 17 19 51 53 |Input signals with clock. | |Group 3 (ioa) 2 3 4 5 6 7 8 9 |Quadrant A local macrocells. |Group 3 (iob) 27 28 29 30 31 32 33 34 |Quadrant B local macrocells. |Group 3 (ioc) 36 37 38 39 40 41 42 43 |Quadrant C local macrocells. |Group 3 (iod) 61 62 63 64 65 66 67 68 |Quadrant D local macrocells. | |Group 3 (io) 10 11 12 13 \ |Pin output and global | 23 24 25 26 \ |feedback from global | 44 45 46 47 \ |macrocells. | 57 58 59 60 | |Group 3 (internal) 69 70 71 72 \ |Buried local feedback from | 73 74 75 76 \ |global macrocells. | 77 78 79 80 \ | 81 82 83 84 | |Columns[-] 72,73,80,81 71,74,79,82 70,75,78,83 69,76,77,84 \ | 9,27,43,61 8,28,42,62 7,29,41,63 6,30,40,64 \ | 5,31,39,65 4,32,38,66 3,33,37,67 2,34,36,68 \ | 47 46 45 44 23 24 25 26 13 12 11 10 57 58 59 60 \ | 50 49 48 20 21 22 16 15 14 54 55 56 51 19 17 53 | |Rows[42240(+5)] 2(8,rtR) 3(8,rtR) 4(8,rtR) 5(8,rtR) \ | 6(8,rtR) 7(8,rtR) 8(8,rtR) 9(8,rtR) \ | 10,69(8,rtR) 11,70(8,rtR) 12,71(8,rtR) 13,72(8,rtR) \ | 23,73(8,rtR) 24,74(8,rtR) 25,75(8,rtR) 26,76(8,rtR) \ | 27(8,rtR) 28(8,rtR) 29(8,rtR) 30(8,rtR) \ | 31(8,rtR) 32(8,rtR) 33(8,rtR) 34(8,rtR) \ | 36(8,rtR) 37(8,rtR) 38(8,rtR) 39(8,rtR) \ | 40(8,rtR) 41(8,rtR) 42(8,rtR) 43(8,rtR) \ | 44,77(8,rtR) 45,78(8,rtR) 46,79(8,rtR) 47,80(8,rtR) \ | 57,81(8,rtR) 58,82(8,rtR) 59,83(8,rtR) 60,84(8,rtR) \ | 61(8,rtR) 62(8,rtR) 63(8,rtR) 64(8,rtR) \ | 65(8,rtR) 66(8,rtR) 67(8,rtR) 68(8,rtR) | |Register bypass 2 3 4 5 6 7 8 9 10 69 11 70 12 71 13 72 \ | 23 73 24 74 25 75 26 76 27 28 29 30 31 32 33 34 \ | 36 37 38 39 40 41 42 43 44 77 45 78 46 79 47 80 \ | 57 81 58 82 59 83 60 84 61 62 63 64 65 66 67 68 | |VCC 18 52 |GND 1 35 PROGRAMMABLE DEVICE REFERENCE TABLES Page 61 |Type EP1810c |Overlay EP1800 | |Pins 68 |Special fuses 250 |Activity 1 | |Group 1 (in) 14 15 16 20 21 22 \ |Pure input signals. | 48 49 50 54 55 56 | |Group 4 (clock) 17 19 51 53 |Input signals with clock. | |Group 3 (ioa) 2 3 4 5 6 7 8 9 |Quadrant A local macrocells. |Group 3 (iob) 27 28 29 30 31 32 33 34 |Quadrant B local macrocells. |Group 3 (ioc) 36 37 38 39 40 41 42 43 |Quadrant C local macrocells. |Group 3 (iod) 61 62 63 64 65 66 67 68 |Quadrant D local macrocells. | |Group 3 (io) 10 11 12 13 \ |Pin output and global | 23 24 25 26 \ |feedback from global | 44 45 46 47 \ |macrocells. | 57 58 59 60 | |Group 3 (internal) 69 70 71 72 \ |Buried local feedback from | 73 74 75 76 \ |global macrocells. | 77 78 79 80 \ | 81 82 83 84 | |Columns[-] 72,73,80,81 71,74,79,82 70,75,78,83 69,76,77,84 \ | 9,27,43,61 8,28,42,62 7,29,41,63 6,30,40,64 \ | 5,31,39,65 4,32,38,66 3,33,37,67 2,34,36,68 \ | 47 46 45 44 23 24 25 26 13 12 11 10 57 58 59 60 \ | 50 49 48 20 21 22 16 15 14 54 55 56 51 19 17 53 | |Rows[42240(+5)] 2(8,rtR) 3(8,rtR) 4(8,rtR) 5(8,rtR) \ | 6(8,rtR) 7(8,rtR) 8(8,rtR) 9(8,rtR) \ | 10,69(8,rtR) 11,70(8,rtR) 12,71(8,rtR) 13,72(8,rtR) \ | 23,73(8,rtR) 24,74(8,rtR) 25,75(8,rtR) 26,76(8,rtR) \ | 27(8,rtR) 28(8,rtR) 29(8,rtR) 30(8,rtR) \ | 31(8,rtR) 32(8,rtR) 33(8,rtR) 34(8,rtR) \ | 36(8,rtR) 37(8,rtR) 38(8,rtR) 39(8,rtR) \ | 40(8,rtR) 41(8,rtR) 42(8,rtR) 43(8,rtR) \ | 44,77(8,rtR) 45,78(8,rtR) 46,79(8,rtR) 47,80(8,rtR) \ | 57,81(8,rtR) 58,82(8,rtR) 59,83(8,rtR) 60,84(8,rtR) \ | 61(8,rtR) 62(8,rtR) 63(8,rtR) 64(8,rtR) \ | 65(8,rtR) 66(8,rtR) 67(8,rtR) 68(8,rtR) | |Register bypass 2 3 4 5 6 7 8 9 10 69 11 70 12 71 13 72 \ | 23 73 24 74 25 75 26 76 27 28 29 30 31 32 33 34 \ | 36 37 38 39 40 41 42 43 44 77 45 78 46 79 47 80 \ | 57 81 58 82 59 83 60 84 61 62 63 64 65 66 67 68 | |VCC 18 52 |GND 1 35 PROGRAMMABLE DEVICE REFERENCE TABLES Page 62 |Type EP1830c |Overlay EP1800 | |Pins 68 |Special fuses 250 |Activity 1 | |Group 1 (in) 14 15 16 20 21 22 \ |Pure input signals. | 48 49 50 54 55 56 | |Group 4 (clock) 17 19 51 53 |Input signals with clock. | |Group 3 (ioa) 2 3 4 5 6 7 8 9 |Quadrant A local macrocells. |Group 3 (iob) 27 28 29 30 31 32 33 34 |Quadrant B local macrocells. |Group 3 (ioc) 36 37 38 39 40 41 42 43 |Quadrant C local macrocells. |Group 3 (iod) 61 62 63 64 65 66 67 68 |Quadrant D local macrocells. | |Group 3 (io) 10 11 12 13 \ |Pin output and global | 23 24 25 26 \ |feedback from global | 44 45 46 47 \ |macrocells. | 57 58 59 60 | |Group 3 (internal) 69 70 71 72 \ |Buried local feedback from | 73 74 75 76 \ |global macrocells. | 77 78 79 80 \ | 81 82 83 84 | |Columns[-] 72,73,80,81 71,74,79,82 70,75,78,83 69,76,77,84 \ | 9,27,43,61 8,28,42,62 7,29,41,63 6,30,40,64 \ | 5,31,39,65 4,32,38,66 3,33,37,67 2,34,36,68 \ | 47 46 45 44 23 24 25 26 13 12 11 10 57 58 59 60 \ | 50 49 48 20 21 22 16 15 14 54 55 56 51 19 17 53 | |Rows[42240(+5)] 2(8,rtR) 3(8,rtR) 4(8,rtR) 5(8,rtR) \ | 6(8,rtR) 7(8,rtR) 8(8,rtR) 9(8,rtR) \ | 10,69(8,rtR) 11,70(8,rtR) 12,71(8,rtR) 13,72(8,rtR) \ | 23,73(8,rtR) 24,74(8,rtR) 25,75(8,rtR) 26,76(8,rtR) \ | 27(8,rtR) 28(8,rtR) 29(8,rtR) 30(8,rtR) \ | 31(8,rtR) 32(8,rtR) 33(8,rtR) 34(8,rtR) \ | 36(8,rtR) 37(8,rtR) 38(8,rtR) 39(8,rtR) \ | 40(8,rtR) 41(8,rtR) 42(8,rtR) 43(8,rtR) \ | 44,77(8,rtR) 45,78(8,rtR) 46,79(8,rtR) 47,80(8,rtR) \ | 57,81(8,rtR) 58,82(8,rtR) 59,83(8,rtR) 60,84(8,rtR) \ | 61(8,rtR) 62(8,rtR) 63(8,rtR) 64(8,rtR) \ | 65(8,rtR) 66(8,rtR) 67(8,rtR) 68(8,rtR) | |Register bypass 2 3 4 5 6 7 8 9 10 69 11 70 12 71 13 72 \ | 23 73 24 74 25 75 26 76 27 28 29 30 31 32 33 34 \ | 36 37 38 39 40 41 42 43 44 77 45 78 46 79 47 80 \ | 57 81 58 82 59 83 60 84 61 62 63 64 65 66 67 68 | |VCC 18 52 |GND 1 35 PROGRAMMABLE DEVICE REFERENCE TABLES Page 63 11. MACH DEVICES MACH devices are the first example of a new method of configuring complex programmable logic devices. The compiler does not produce a JEDEC file directly, but rather produces a PLA file, which is in turn processed by a logic-fitting program to obtain the actual JEDEC file. The logic-fitting program, called simply the fitter, is written by the manufacturer based on specialized knowledge of the internal structure of the device. This gives the compiler an open architecture, allowing manufacturers to add parts to the compiler themselves. Use of the MACH fitter is beyond the scope of this material and is described in a separate publication (available in the future). Structure of the PLA file is described in the PLD reference guide, though for ordinary use, specifics can be ignored. The table below shows pin structures as they are on the actual part, but shows rows and columns only in abstract form. Actual row and column assignment, as well as pin assignment in most cases, is handled by the fitter. |Type MACH110 |Overlay MACH | |Pins 44 |Activity 1 |Object 2 |PLA object format | |Group 1 (in) 10 11 32 33 | |Group 3 (io) 2 3 4 5 6 7 8 9 14 15 16 17 18 19 20 21 \ | 24 25 26 27 28 29 30 31 36 37 38 39 40 41 42 43 | |Group 3 (internal) 46 47 48 49 50 51 52 53 58 59 60 61 62 63 64 65 \ | 68 69 70 71 72 73 74 75 80 81 82 83 84 85 86 87 | |Group 4 (clock) 13 35 | |Columns 2,46 3,47 4,48 5,49 6,50 7,51 8,52 9,53 10 11 \ | 13,57 14,58 15,59 16,60 17,61 18,62 19,63 20,64 21,65 \ | 24,68 25,69 26,70 27,71 28,72 29,73 30,74 31,75 32 33 \ | 35,79 36,80 37,81 38,82 39,83 40,84 41,85 42,86 43,87 | |Rows[40000(+8)] 9,53(12DT) 8,52(12DT) 7,51(12DT) 6,50(12DT) \ | 5,49(12DT) 4,48(12DT) 3,47(12DT) 2,46(12DT) \ | 14,58(12DT) 15,59(12DT) 16,60(12DT) 17,61(12DT) \ | 18,62(12DT) 19,63(12DT) 20,64(12DT) 21,65(12DT) \ | 31,75(12DT) 30,74(12DT) 29,73(12DT) 28,72(12DT) \ | 27,71(12DT) 26,70(12DT) 25,69(12DT) 24,68(12DT) \ | 36,80(12DT) 37,81(12DT) 38,82(12DT) 39,83(12DT) \ | 40,84(12DT) 41,85(12DT) 42,86(12DT) 43,87(12DT) | |GND 1 12 23 34 |VCC 22 PROGRAMMABLE DEVICE REFERENCE TABLES Page 64 12. EMITTER COUPLED DEVICES Tables in this group represent emitter-coupled programmable logic devices (National Semiconductor ECL). Dashes (-) in the table represent phantom rows and columns used by the manufacturer to achieve portability of fuse maps among devices. Because this is ECL, the enable pins represent logical-and rather than three-state logic. The two devices PAL16P4N and PAL16P8N represent devices named PAL16P4 and PAL16P8 by the manufacturer. The letter `N' is appended to make the names unique (A PAL16P8 already exists as a general 20-series device). Note that these devices were simply called PAL16N4 and PAL16N8 in versions earlier than 1.20. |Type PAL12C4 | |Group 1 (in) 1 2 23 3 22 9 16 10 15 11 14 13 |Group 2 (out) 5 20 7 18 |Group 9 (nc) 4 21 8 17 | |Columns 1 23 2 22 3 - - - - 16 9 15 10 14 11 13 |Rows -(8) -(8) 20(8) 5(8) 18(8) 7(8) -(8) -(8) | |VCC 24 |VCCO 6 19 |VEE 12 |Type PAL16P4N | |Group 1 (in) 1 2 23 3 22 4 21 8 17 9 16 10 15 11 14 13 |Group 2 (out) 5 20 7 18 | |Columns 1 23 2 22 3 21 4 17 8 16 9 15 10 14 11 13 |Rows[2048] -(8) -(8) 20(8) 5(8) 18(8) 7(8) -(8) -(8) | |VCC 24 |VCCO 6 19 |VEE 12 |Type PAL16P8N | |Group 1 (in) 1 2 23 3 22 9 16 10 15 11 14 13 |Group 2 (out) 5 20 7 18 |Group 3 (io) 4 21 8 17 | |Columns 1 23 2 22 3 21 4 17 8 16 9 15 10 14 11 13 |Rows[2048] 21(8) 4(8) 20(8) 5(8) 18(8) 7(8) 17(8) 8(8) | |VCC 24 |VCCO 6 19 |VEE 12 PROGRAMMABLE DEVICE REFERENCE TABLES Page 65 |Type PAL16RC4 | |Group 1 (in) 2 23 3 22 10 15 11 14 |Group 2 (out) 5 20 7 18 |Group 3 (io) 4 21 8 17 |Group 4 (clock) 9 16 |Group 5 (enable) 13 |Group 6 (reset) 1 | |Columns 5 23 2 22 3 21 4 17 8 20 7 15 10 14 11 18 |Rows[2048] 21(8) 4(8) 20(8R) 5(8R) 18(8R) 7(8R) 17(8) 8(8) | |VCC 24 |VCCO 6 19 |VEE 12 |Type PAL16RD4 | |Group 1 (in) 2 23 3 22 10 15 11 14 |Group 2 (out) 5 20 7 18 |Group 3 (io) 4 21 8 17 |Group 4 (clock) 9 16 |Group 5 (enable) 13 |Group 6 (reset) 1 | |Columns 5 23 2 22 3 21 4 17 8 20 7 15 10 14 11 18 |Rows[2048] 21(8) 4(8) 20(8R) 5(8R) 18(8R) 7(8R) 17(8) 8(8) | |VCC 24 |VCCO 6 19 |VEE 12 |Type PAL16RC8 | |Group 1 (in) 2 23 3 22 10 15 11 14 |Group 2 (out) 4 21 5 20 7 18 8 17 |Group 4 (clock) 9 16 |Group 5 (enable) 13 |Group 6 (reset) 1 | |Columns 5 23 2 22 3 21 4 17 8 20 7 15 10 14 11 18 |Rows[2048] 21(8R) 4(8R) 20(8R) 5(8R) 18(8R) 7(8R) 17(8R) 8(8R) | |VCC 24 |VCCO 6 19 |VEE 12 PROGRAMMABLE DEVICE REFERENCE TABLES Page 66 |Type PAL16RD8 | |Group 1 (in) 2 23 3 22 10 15 11 14 |Group 2 (out) 4 21 5 20 7 18 8 17 |Group 4 (clock) 9 16 |Group 5 (enable) 13 |Group 6 (reset) 1 | |Columns 5 23 2 22 3 21 4 17 8 20 7 15 10 14 11 18 |Rows[2048] 21(8R) 4(8R) 20(8R) 5(8R) 18(8R) 7(8R) 17(8R) 8(8R) | |VCC 24 |VCCO 6 19 |VEE 12 |Type PAL16RM4 | |Group 1 (in) 2 23 3 22 4 21 8 17 10 15 11 14 |Group 2 (out) 5 20 7 18 |Group 4 (clock) 9 16 13 |Group 6 (reset) 1 | |Columns 5 23 2 22 3 21 4 17 8 20 7 15 10 14 11 18 |Rows[2048] -(8) -(8) 20(8R) 5(8R) 18(8R) 7(8R) -(8) -(8) | |VCC 24 |VCCO 6 19 |VEE 12 PROGRAMMABLE DEVICE REFERENCE TABLES Page 67 13. EXCLUSIVE-OR DEVICES Devices in this group have hardware exclusive-or gates at the final stage, just before the output cells. If the Boolean equation has either an exclusive-or operation (##) or an exclusive-nor operation (##') at the highest level, then the hardware exclusive-or gate will be applied to it. If the Boolean equation has neither exclusive-or nor exclusive-nor at the highest level, then the exclusive-or gate will be used to select the polarity for the signal. Thus, the exclusive-or devices can be handy even if no exclusive-or operations appear in the source code. For example, the logical sum of nine terms would normally overflow the available product terms in smaller devices. However, the equation Q = A # B # C # D # E # F # G # H # I can be rephrased as Q = (A # B # C # D # E # F # G # H # I)' ## 1 which can then be written Q = (A' & B' & C' & D' & E' & F' & G' & H' & I') ## 1 which requires only one product term instead of nine. The PLD compiler will carry out the algebra automatically if the original form does not fit. |Type PAL20X4 |Activity 0 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 20 19 18 17 |Group 3 (io) 23 22 21 16 15 14 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 | |Rows 23(1t3) 22(1t3) 21(1t3) \ | 20(2x2R) 19(2x2R) 18(2x2R) 17(2x2R) \ | 16(1t3) 15(1t3) 14(1t3) PROGRAMMABLE DEVICE REFERENCE TABLES Page 68 |Type PAL20X8 |Activity 0 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 22 21 20 19 18 17 16 15 |Group 3 (io) 23 14 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 | |Rows 23(1t3) 22(2x2R) 21(2x2R) 20(2x2R) 19(2x2R) \ | 18(2x2R) 17(2x2R) 16(2x2R) 15(2x2R) 14(1t3) |Type PAL20X10 |Activity 0 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 23 22 21 20 19 18 17 16 15 14 |Group 4 (clock) 1 |Group 5 (enable) 13 | |Columns 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 |Rows 23(2x2R) 22(2x2R) 21(2x2R) 20(2x2R) 19(2x2R) \ | 18(2x2R) 17(2x2R) 16(2x2R) 15(2x2R) 14(2x2R) Following is a specialized arithmetic device. Outputs from the four exclusive-or pins (17, 16, 15, and 14) are normal, but feedback signals from those pins are combined by hard-wired combinational logic with inputs from pins 4, 5, 6, and 7, respectively. This device must be used with great care, since additional logic beyond that shown in the source code is added by the hardware. |Type PAL16X4 |Activity 0 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 17 16 15 14 |Group 3 (io) 19 18 13 12 |Group 4 (clock) 1 |Group 5 (enable) 11 | |Columns 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 |Rows 19(1t7) 18(1t7) \ | 17(4x4R) 16(4x4R) 15(4x4R) 14(4x4R) \ | 13(1t7) 12(1t7) PROGRAMMABLE DEVICE REFERENCE TABLES Page 69 14. GENERIC DEVICES The generic devices are included for compatibility with earlier versions of the compiler. They are large devices with logic arrays of over 256,000 fuses arranged in a symmetric fashion. The devices are intended for testing equations before an actual device is assigned. In recent versions of the compiler, the generic devices are largely replaced by device-free design, as described in the PLD reference guide. |Type GEN40RP40 |Pins 48 | |Group 3 (io) 1 2 3 4 5 6 7 8 9 10 \ | 11 12 13 14 15 16 17 18 19 20 \ | 21 22 23 24 25 26 27 28 29 30 \ | 31 32 33 34 35 36 37 38 39 40 | |Group 4 (clock) 41 | |GND 45 44 43 |VCC 48 47 46 | |Columns 1 2 3 4 5 6 7 8 9 10 \ | 11 12 13 14 15 16 17 18 19 20 \ | 21 22 23 24 25 26 27 28 29 30 \ | 31 32 33 34 35 36 37 38 39 40 | |Rows[256000] 1(1t79R) 2(1t79R) 3(1t79R) 4(1t79R) 5(1t79R) \ | 6(1t79R) 7(1t79R) 8(1t79R) 9(1t79R) 10(1t79R) \ | 11(1t79R) 12(1t79R) 13(1t79R) 14(1t79R) 15(1t79R) \ | 16(1t79R) 17(1t79R) 18(1t79R) 19(1t79R) 20(1t79R) \ | 21(1t79R) 22(1t79R) 23(1t79R) 24(1t79R) 25(1t79R) \ | 26(1t79R) 27(1t79R) 28(1t79R) 29(1t79R) 30(1t79R) \ | 31(1t79R) 32(1t79R) 33(1t79R) 34(1t79R) 35(1t79R) \ | 36(1t79R) 37(1t79R) 38(1t79R) 39(1t79R) 40(1t79R) | |Register bypass[256040] 1 2 3 4 5 6 7 8 9 10 \ | 11 12 13 14 15 16 17 18 19 20 \ | 21 22 23 24 25 26 27 28 29 30 \ | 31 32 33 34 35 36 37 38 39 40 PROGRAMMABLE DEVICE REFERENCE TABLES Page 70 |Type GEN20RP20 |Pins 24 | |Group 3 (io) 1 2 3 4 5 6 7 8 9 10 \ | 11 12 13 14 15 16 17 18 19 20 | |Group 4 (clock) 21 | |GND 22 |VCC 24 | |Columns 1 2 3 4 5 6 7 8 9 10 \ | 11 12 13 14 15 16 17 18 19 20 | |Rows[256000] 1(1t319R) 2(1t319R) 3(1t319R) 4(1t319R) 5(1t319R) \ | 6(1t319R) 7(1t319R) 8(1t319R) 9(1t319R) 10(1t319R) \ | 11(1t319R) 12(1t319R) 13(1t319R) 14(1t319R) 15(1t319R) \ | 16(1t319R) 17(1t319R) 18(1t319R) 19(1t319R) 20(1t319R) | |Register bypass[256040] 1 2 3 4 5 6 7 8 9 10 \ | 11 12 13 14 15 16 17 18 19 20 PROGRAMMABLE DEVICE REFERENCE TABLES Page 71 15. DEMONSTRATION DEVICE The OrCAD PLD demonstration package uses a device called PLD21D10, which is a pseudo-device for demonstration and learning. It is included here for completeness. The table represents a 24-pin chip with eleven input pins down the left-hand side, ten input/output pins down the right-hand side, power, ground, and a clock. Internally each input/output pin has 16 product terms available, one dedicated to tri-state enable, the others available for normal logic. The input/output pins can be programmed to be either active-high or active-low as well as combinational or registered. Registers are set low on power-up. The device has 6720 fuses in the main array, arranged in 10 sets of 16x42 and numbered 0 to 6719. Ten additional fuses numbered 6720 to 6729 determine the output polarity, and ten more numbered 6730 to 6739 determine the type of output [combinational or registered]. |Type PLD21D10 |Pins 24 | |Initialization L | |Group 1 (in) 1 2 3 4 5 6 7 8 9 10 11 |Group 3 (io) 23 22 21 20 19 18 17 16 15 14 |Group 4 (clock) 13 | |VCC 24 |GND 12 | |Columns 1 2 3 4 5 6 7 8 9 10 11 23 22 21 20 19 18 17 16 15 14 | |Rows[6720] 23(1t15R) 22(1t15R) 21(1t15R) 20(1t15R) 19(1t15R) \ | 18(1t15R) 17(1t15R) 16(1t15R) 15(1t15R) 14(1t15R) | |Register bypass[6730] 23 22 21 20 19 18 17 16 15 14 PROGRAMMABLE DEVICE REFERENCE TABLES Page 72 16. PROGRAMMABLE READ ONLY MEMORIES Following is a collection of PROM tables in various sizes. For purposes of the PLD compiler, the precise pin-out of a PROM is unimportant, since the .HEX file is organized by address, not by pin. Therefore, the tables here allow any PROM from 32 by 4 to 16K by 8 to be processed by the PLD compiler, regardless of its pinout. Widths of the PROMs represented are 4, 8, and 16 bits, allowing up to sixteen output signals. If two separate 8-bit PROMS are to be used to carry the sixteen signals, then a program to break the file into even and odd bytes is useful. Such programs are available with many device programming machines. In all the PROMs here, the input pins are labelled `in' and the output pins are labelled `out'. The PLD compiler accepts the keyword "Registers" with any signal in a PROM, and takes the keyword as an indication that the actual PROM either contains internal registers or that a register will be connected externally to the outputs of the PROM. The keyword "Registers" makes no difference in the .HEX file, but it does insure that the correct logic is written to the .VEC file for testing. As as example, consider a map to generate logic for a binary to sine wave converter, say for a digital power inverter. A counter external to the logic will generate step numbers that run 0, 1, 2, ..., 254, 255, 0. Given the step number n, the logic will consider it to represent an angle of (n/256)*360 degrees, and will compute the trigonometric sin of the angle (see the PLD reference guide for a description of the function isin). The result will be presented in 8 bits of precision according to the following twos-complement encoding. Binary Decimal Rational Decimal Value Value Fraction Fraction 01111111b 127 127/127 1.0 01111110b 126 126/127 .99212598... : : : . 00000001b 1 1/127 .00787401... 00000000b 0 0 .0 11111111b -1 -1/127 -.00787401... : : : -. 10000010b -126 -126/127 -.99212598... 10000001b -127 -127/127 -1.0 PROGRAMMABLE DEVICE REFERENCE TABLES Page 73 Because this logic has eight input bits and eight output bits, it requires at least a 256 x 8 PROM (the logic is too complex to fit in a PAL). The input signals become address lines, with high-order bit first. The output signals become data lines, also with high-order bit first. The following map will do. |PROM256B8 in:STEP[7~0], out:SIN[7~0] | | Map: STEP[7~0] -> SIN[7~0] { n -> isin(n, 256, 127) } | | Vectors: | { Display "127 * sin(", (STEP[7~0])d, "/256) = ", (SIN[7~0])d | Test STEP[7~0] | End } The logic tester VECTORS can process logic in a PROM, but there is no provision in the standard hexadecimal format for the test vectors themselves. Therefore, with PROMs, VECTORS is used only as a logic simulator. 32 by 4 PROM |Type PROM32B4 | |Group 1 (in) 2 3 4 5 6 |Group 2 (out) 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 |Data 23 22 21 20 32 by 8 PROM |Type PROM32B8 | |Group 1 (in) 2 3 4 5 6 |Group 2 (out) 23 22 21 20 19 18 17 16 |Group 4 (clock) 1 | |Address 2 3 4 5 6 |Data 23 22 21 20 19 18 17 16 32 by 16 PROM |Type PROM32B16 | |Group 1 (in) 2 3 4 5 6 |Group 2 (out) 23 22 21 20 19 18 17 16 15 14 13 11 10 9 8 7 |Group 4 (clock) 1 | |Address 2 3 4 5 6 |Data 23 22 21 20 19 18 17 16 15 14 13 11 10 9 8 7 PROGRAMMABLE DEVICE REFERENCE TABLES Page 74 64 by 4 PROM |Type PROM64B4 | |Group 1 (in) 2 3 4 5 6 7 |Group 2 (out) 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 |Data 23 22 21 20 64 by 8 PROM |Type PROM64B8 | |Group 1 (in) 2 3 4 5 6 7 |Group 2 (out) 23 22 21 20 19 18 17 16 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 |Data 23 22 21 20 19 18 17 16 64 by 16 PROM |Type PROM64B16 | |Group 1 (in) 2 3 4 5 6 7 |Group 2 (out) 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 |Data 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 128 by 4 PROM |Type PROM128B4 | |Group 1 (in) 2 3 4 5 6 7 8 |Group 2 (out) 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 |Data 23 22 21 20 PROGRAMMABLE DEVICE REFERENCE TABLES Page 75 128 by 8 PROM |Type PROM128B8 | |Group 1 (in) 2 3 4 5 6 7 8 |Group 2 (out) 23 22 21 20 19 18 17 16 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 |Data 23 22 21 20 19 18 17 16 128 by 16 PROM |Type PROM128B16 | |Group 1 (in) 2 3 4 5 6 7 8 |Group 2 (out) 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 |Data 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 256 by 4 PROM |Type PROM256B4 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 |Data 23 22 21 20 256 by 8 PROM |Type PROM256B8 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 23 22 21 20 19 18 17 16 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 |Data 23 22 21 20 19 18 17 16 PROGRAMMABLE DEVICE REFERENCE TABLES Page 76 256 by 16 PROM |Type PROM256B16 | |Group 1 (in) 2 3 4 5 6 7 8 9 |Group 2 (out) 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 |Data 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 512 by 4 PROM |Type PROM512B4 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 |Group 2 (out) 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 |Data 23 22 21 20 512 by 8 PROM |Type PROM512B8 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 |Group 2 (out) 23 22 21 20 19 18 17 16 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 |Data 23 22 21 20 19 18 17 16 512 by 16 PROM |Type PROM512B16 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 |Group 2 (out) 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 |Data 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 PROGRAMMABLE DEVICE REFERENCE TABLES Page 77 1K by 4 PROM |Type PROM1KB4 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 |Data 23 22 21 20 1K by 8 PROM |Type PROM1KB8 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 23 22 21 20 19 18 17 16 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 |Data 23 22 21 20 19 18 17 16 1K by 16 PROM |Type PROM1KB16 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 |Group 2 (out) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 |Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 2K by 4 PROM |Type PROM2KB4 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 13 |Group 2 (out) 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 13 |Data 23 22 21 20 PROGRAMMABLE DEVICE REFERENCE TABLES Page 78 2K by 8 PROM |Type PROM2KB8 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 13 |Group 2 (out) 23 22 21 20 19 18 17 16 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 13 |Data 23 22 21 20 19 18 17 16 2K by 16 PROM |Type PROM2KB16 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 12 |Group 2 (out) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 12 |Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 4K by 4 PROM |Type PROM4KB4 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 13 14 |Group 2 (out) 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 13 14 |Data 23 22 21 20 4K by 8 PROM |Type PROM4KB8 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 13 14 |Group 2 (out) 23 22 21 20 19 18 17 16 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 13 14 |Data 23 22 21 20 19 18 17 16 PROGRAMMABLE DEVICE REFERENCE TABLES Page 79 4K by 16 PROM |Type PROM4KB16 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 12 13 |Group 2 (out) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 12 13 |Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 8K by 4 PROM |Type PROM8KB4 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 13 14 15 |Group 2 (out) 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 13 14 15 |Data 23 22 21 20 8K by 8 PROM |Type PROM8KB8 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 13 14 15 |Group 2 (out) 23 22 21 20 19 18 17 16 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 13 14 15 |Data 23 22 21 20 19 18 17 16 8K by 16 PROM |Type PROM8KB16 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 12 13 14 |Group 2 (out) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 12 13 14 |Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 PROGRAMMABLE DEVICE REFERENCE TABLES Page 80 16K by 4 PROM |Type PROM16KB4 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 12 13 15 16 |Group 2 (out) 27 26 25 24 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 12 13 15 16 |Data 27 26 25 24 16K by 8 PROM |Type PROM16KB8 | |Group 1 (in) 2 3 4 5 6 7 8 9 10 11 12 13 15 16 |Group 2 (out) 27 26 25 24 23 22 21 20 |Group 4 (clock) 1 | |Address 2 3 4 5 6 7 8 9 10 11 12 13 15 16 |Data 27 26 25 24 23 22 21 20 PROGRAMMABLE DEVICE REFERENCE TABLES Page 81 17. INDEX TO DEVICE TYPES Within the text, related devices are grouped together. Here the devices are indexed alphabetically. If the alphabetical order seems strange in places, it is because the device types are alphabetized strictly from left to right. Therefore, the word PAL12H10 precedes the word PAL12H6, because the digit `1' alphabetically precedes the digit `6'. EP1800c, 60 PAL14H4, 10 PAL18P8, 6 PAL24R4, 26 EP1810c, 61 PAL14H8, 20 PAL18U8, 28 PAL24R6, 25 EP1830c, 62 PAL14L4, 10 PAL18U8Z, 28 PAL24R8, 25 EP310, 49 PAL14L8, 19 PAL19L8, 17 PAL6L16, 23 EP320, 50 PAL14P4, 10 PAL19R4, 17 PAL8L14, 23 EP330, 50 PAL14P8, 20 PAL19R6, 18 PLD21D10, 71 EP600, 52 PAL16C1, 11 PAL19R8, 18 PROM1KB16, 77 EP600c, 53 PAL16HD8, 6 PAL20C1, 21 PROM1KB4, 77 EP610, 53 PAL16H2, 11 PAL20H10, 22 PROM1KB8, 77 EP610c, 54 PAL16H6, 20 PAL20H2, 22 PROM128B16, 75 EP630, 54 PAL16H8, 5 PAL20H8, 12 PROM128B4, 74 EP630c, 55 PAL16LD8, 6 PAL20L10, 22 PROM128B8, 75 EP900, 55 PAL16L2, 11 PAL20L2, 21 PROM16KB4, 80 EP900c, 56 PAL16L6, 20 PAL20L8, 12 PROM16KB8, 80 EP910, 56 PAL16L8, 5 PAL20P10, 22 PROM2KB16, 78 EP910c, 57 PAL16N8, 11 PAL20P2, 22 PROM2KB4, 77 GAL16V8, 41 PAL16P2, 11 PAL20P8, 12 PROM2KB8, 78 GAL16V8A, 42 PAL16P4N, 64 PAL20RA10, 47 PROM256B16, 76 GAL16Z8, 43 PAL16P6, 20 PAL20RP10, 15 PROM256B4, 75 GAL16Z8A, 44 PAL16P8, 5 PAL20RP4, 14 PROM256B8, 75 GAL18V10, 44 PAL16P8N, 64 PAL20RP4I, 15 PROM32B16, 73 GAL20V8, 42 PAL16RA8, 47 PAL20RP6, 14 PROM32B4, 73 GAL20V8A, 43 PAL16RC4, 65 PAL20RP6I, 15 PROM32B8, 73 GAL26CV12, 45 PAL16RC8, 65 PAL20RP8, 14 PROM4KB16, 79 GEN20RP20, 70 PAL16RD4, 65 PAL20RP8I, 15 PROM4KB4, 78 GEN40RP40, 69 PAL16RD8, 66 PAL20R4, 13 PROM4KB8, 78 MACH110, 63 PAL16RM4, 66 PAL20R6, 13 PROM512B16, 76 PAL10H8, 9 PAL16RP4, 7 PAL20R8, 13 PROM512B4, 76 PAL10L8, 9 PAL16RP6, 7 PAL20X10, 68 PROM512B8, 76 PAL10P8, 9 PAL16RP8, 8 PAL20X4, 67 PROM64B16, 74 PAL12C4, 64 PAL16R4, 6 PAL20X8, 68 PROM64B4, 74 PAL12H10, 19 PAL16R6, 7 PAL22P10, 16 PROM64B8, 74 PAL12H6, 10 PAL16R8, 7 PAL22V10, 30 PROM8KB16, 79 PAL12L10, 19 PAL16X4, 68 PAL22V10X, 30 PROM8KB4, 79 PAL12L6, 9 PAL18H4, 21 PAL22V10Z, 31 PROM8KB8, 79 PAL12P10, 19 PAL18L4, 21 PAL24L10, 24 PAL12P6, 10 PAL18P4, 21 PAL24R10, 24