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Text File | 1991-07-01 | 457.5 KB | 17,454 lines

* Library of digital logic * Copyright 1989, 1990, 1991 by MicroSim Corporation * Neither this library nor any part may be copied without the express * written consent of MicroSim Corporation * Release date: July, 1991 *------------------------------------------------------------------------- * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7400 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_00 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_00 ugate ( + tplhty=11ns tplhmx=22ns + tphlty=7ns tphlmx=15ns + ) *--------- * 74AC00 Quadruple 2-input Positive-Nand Gates * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74AC00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_AC00 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC00 ugate ( + tplhmn=1ns tplhty=6ns + tplhmx=8.5ns tphlmn=1ns + tphlty=4.5ns tphlmx=7ns + ) *--------- * 74ACT00 Quadruple 2-input Positive-Nand Gates * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74ACT00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ACT00 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT00 ugate ( + tplhmn=1ns tplhty=5.5ns + tplhmx=9.5ns tphlmn=1ns + tphlty=4ns tphlmx=8ns + ) *--------- * 74ALS00A Quadruple 2-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS00A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS00A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS00A ugate ( + tplhty=7ns tphlty=5ns + tplhmn=3ns tplhmx=11ns + tphlmn=2ns tphlmx=8ns + ) *--------- * 74AS00 Quadruple 2-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74AS00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_AS00 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS00 ugate ( + tplhmn=1ns tplhmx=4.5ns + tphlmn=1ns tphlmx=4ns + ) *--------- * 74F00 Quadruple 2-input Positive-Nand Gates * * The F Logic Data Book, 1987, TI * tdn 06/24/89 Update interface and model names .subckt 74F00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_F00 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F00 ugate ( + tplhty=3.3ns tphlty=2.8ns + tplhmn=1.6ns tplhmx=6ns + tphlmn=1ns tphlmx=5.3ns + ) *--------- * 74H00 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model devices .subckt 74H00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_H00 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H00 ugate ( + tplhty=5.9ns tplhmx=10ns + tphlty=6.2ns tphlmx=10ns + ) *--------- * 74HC00 Quadruple 2-input Positive-Nand Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_HC00 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC00 ugate ( + tplhty=9ns tplhmx=23ns + tphlty=9ns tphlmx=23ns + ) *--------- * 54L00 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 54L00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_L00 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L00 ugate ( + tplhty=35ns tplhmx=60ns + tphlty=31ns tphlmx=60ns + ) *--------- * 74LS00 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS00 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS00 ugate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *--------- * 74S00 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74S00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_S00 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S00 ugate ( + tplhty=3ns tplhmx=4.5ns + tphlty=3ns tphlmx=5ns + ) *--------------------------------------------------------------------- * 7401 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7401 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_01 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_01 ugate ( + tplhty=35ns tplhmx=55ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74ALS01 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS01 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS01 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS01 ugate ( + tplhmn=23ns tplhmx=54ns + tphlmn=8ns tphlmx=28ns + ) *--------- * 74H01 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74H01 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_H01 IO_H_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H01 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=7.5ns tphlmx=12ns + ) *--------- * 74HC01 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC01 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_HC01 IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC01 ugate ( + tplhty=13ns tplhmx=31ns + tphlty=10ns tphlmx=25ns + ) *--------- * 74LS01 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS01 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS01 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS01 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *------------------------------------------------------------------------- * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7402 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_02 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_02 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74AC02 Quadruple 2-input Positive-Nor Gates * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74AC02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_AC02 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC02 ugate ( + tplhmn=1ns tplhty=4ns + tplhmx=6.5ns tphlmn=1ns + tphlty=4.5ns tphlmx=7ns + ) *--------- * 74ACT02 Quadruple 2-input Positive-Nor Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74ACT02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_ACT02 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT02 ugate ( + tplhmn=1.5ns tplhty=6.1ns + tplhmx=10.6ns tphlmn=1.5ns + tphlty=5.3ns tphlmx=8.7ns + ) *--------- * 74ALS02 Quadruple 2-input Positive-Nor Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_ALS02 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS02 ugate ( + tplhty=7ns tphlty=5ns + tplhmn=3ns tplhmx=12ns + tphlmn=3ns tphlmx=10ns + ) *--------- * 74AS02 Quadruple 2-input Positive-Nor Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74AS02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_02AS IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_02AS ugate ( + tplhmn=1ns tplhmx=4.5ns + tphlmn=1ns tphlmx=4.5ns + ) *--------- * 74F02 Quadruple 2-input Positive-Nor Gates * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names .subckt 74F02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_F02 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F02 ugate ( + tplhty=4ns tphlty=2.8ns + tplhmn=1.7ns tplhmx=6.5ns + tphlmn=1ns tphlmx=5.3ns + ) *--------- * 74HC02 Quadruple 2-input Positive-Nor Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_HC02 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC02 ugate ( + tplhty=9ns tplhmx=23ns + tphlty=9ns tphlmx=23ns + ) *--------- * 54L02 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 54L02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_L02 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L02 ugate ( + tplhty=31ns tplhmx=60ns + tphlty=35ns tphlmx=60ns + ) *--------- * 74LS02 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_LS02 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS02 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *--------- * 74S02 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74S02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_S02 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S02 ugate ( + tplhty=3.5ns tplhmx=5.5ns + tphlty=3.5ns tphlmx=5.5ns + ) *------------------------------------------------------------------------- * 7403 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7403 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_03 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_03 ugate ( + tplhty=35ns tplhmx=45ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74ALS03B Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS03B A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS03B IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS03B ugate ( + tplhty=35ns tphlty=8ns + tplhmn=20ns tplhmx=50ns + tphlmn=3ns tphlmx=13ns + ) *--------- * 74HC03 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC03 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_HC03 IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC03 ugate ( + tplhty=13ns tplhmx=31ns + tphlty=10ns tphlmx=25ns + ) *--------- * 54L03 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 54L03 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_L03 IO_L_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L03 ugate ( + tplhty=60ns tplhmx=90ns + tphlty=33ns tphlmx=60ns + ) *--------- * 74LS03 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS03 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS03 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS03 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *--------- * 74S03 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74S03 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_S03 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S03 ugate ( + tplhty=5ns tphlty=4.5ns + tplhmn=2ns tplhmx=7.5ns + tphlmn=2ns tphlmx=7ns + ) *------------------------------------------------------------------------- * 7404 Hex Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7404 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_04 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_04 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74AC04 Hex Inverters * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74AC04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_AC04 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC04 ugate ( + tplhmn=1ns tplhty=4ns + tplhmx=7.5ns tphlmn=1ns + tphlty=3.5ns tphlmx=7ns + ) *--------- * 74ACT04 Hex Inverters * * The ACL Data Manual, Signetics * cv 07/13/90 Created from LS .subckt 74ACT04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_ACT04 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT04 ugate ( + tplhmn=1.5ns tplhmx=9.7ns + tphlmn=1.5ns tphlmx=9.6ns + ) *--------- * 74ALS04B Hex Inverters * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS04B A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_ALS04B IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS04B ugate ( + tplhmn=3ns tplhmx=11ns + tphlmn=2ns tphlmx=8ns + ) *--------- * 74AS04 Hex Inverters * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74AS04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_AS04 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS04 ugate ( + tplhmn=1ns tplhmx=5ns + tphlmn=1ns tphlmx=4ns + ) *--------- * 74F04 Hex Inverters * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names .subckt 74F04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_F04 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F04 ugate ( + tplhty=3.3ns tphlty=2.8ns + tplhmn=1.6ns tplhmx=6ns + tphlmn=1ns tphlmx=5.3ns + ) *--------- * 74H04 Hex Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74H04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_H04 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H04 ugate ( + tplhty=6ns tplhmx=10ns + tphlty=6.5ns tphlmx=10ns + ) *--------- * 74HC04 Hex Inverters * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_H04C IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H04C ugate ( + tplhty=9ns tplhmx=24ns + tphlty=9ns tphlmx=24ns + ) *--------- * 74HCT04 Hex Inverters * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HCT04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_HCT04 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HCT04 ugate ( + tplhty=14ns tplhmx=25ns + tphlty=14ns tphlmx=25ns + ) *--------- * 54L04 Hex Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 54L04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_L04 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L04 ugate ( + tplhty=35ns tplhmx=60ns + tphlty=31ns tphlmx=60ns + ) *--------- * 74LS04 Hex Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_LS04 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS04 ugate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *--------- * 74S04 Hex Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74S04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_S04 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S04 ugate ( + tplhty=3ns tplhmx=4.5ns + tphlty=3ns tphlmx=5ns + ) *------------------------------------------------------------------------- * 7405 Hex Inverters with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7405 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_05 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_05 ugate ( + tplhty=40ns tplhmx=55ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74AC05 Hex Inverters with Open-Collector Outputs * * The Advanced CMOS Logic ICs Data Book, RCA * cv 07/13/90 Created from LS .subckt 74AC05 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_AC05 IO_AC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC05 ugate ( + tplhmn=2.2ns tplhmx=7.5ns + tphlmn=1.7ns tphlmx=5.9ns + ) *--------- * 74ACT05 Hex Inverters with Open-Collector Outputs * * The Advanced CMOS Logic ICs Data Book, RCA * cv 07/13/90 Created from LS .subckt 74ACT05 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_ACT05 IO_ACT_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT05 ugate ( + tphlmn=2.4ns tphlmx=8.5ns + tplhmn=2.8ns tplhmx=9.8ns + ) *--------- * 74ALS05A Hex Inverters with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS05A A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_ALS05A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS05A ugate ( + tplhty=45ns tphlty=9ns + tplhmn=23ns tplhmx=54ns + tphlmn=4ns tphlmx=14ns + ) *--------- * 74H05 Hex Inverters with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74H05 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_H05 IO_H_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H05 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=7.5ns tphlmx=12ns + ) *--------- * 74HC05 Hex Inverters with Open-Collector Outputs * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC05 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_HC05 IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC05 ugate ( + tplhty=13ns tplhmx=29ns + tphlty=9ns tphlmx=21ns + ) *--------- * 74LS05 Hex Inverters with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS05 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_LS05 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS05 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *--------- * 74S05 Hex Inverters with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74S05 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_S05 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S05 ugate ( + tplhty=5ns tphlty=4.5ns + tplhmn=2ns tplhmx=7.5ns + tphlmn=2ns tphlmx=7ns + ) *------------------------------------------------------------------------- * 7406 Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7406 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_06 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_06 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=15ns tphlmx=23ns + ) *------------------------------------------------------------------------- * 7407 Hex Buffers/Drivers with Open-Collector High-Voltage Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7407 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_07 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_07 ugate ( + tplhty=6ns tplhmx=10ns + tphlty=20ns tphlmx=30ns + ) *------------------------------------------------------------------------- * 7408 Quadruple 2-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7408 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_08 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_08 ugate ( + tplhty=17.5ns tplhmx=27ns + tphlty=12ns tphlmx=19ns + ) *--------- * 74AC08 Quadruple 2-input Positive-And Gates * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74AC08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_AC08 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC08 ugate ( + tplhmn=1ns tplhty=5.5ns + tplhmx=8.5ns tphlmn=1ns + tphlty=5.5ns tphlmx=7.5ns + ) *--------- * 74ACT08 Quadruple 2-input Positive-And Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74ACT08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_ACT08 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT08 ugate ( + tplhmn=1.5ns tplhty=5.8ns + tplhmx=9ns tphlmn=1.5ns + tphlty=5.2ns tphlmx=8.2ns + ) *--------- * 74ALS08 Quadruple 2-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_ALS08 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS08 ugate ( + tplhty=8ns tphlty=6.5ns + tplhmn=4ns tplhmx=14ns + tphlmn=3ns tphlmx=10ns + ) *--------- * 74AS08 Quadruple 2-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74AS08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_AS08 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS08 ugate ( + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=5.5ns + ) *--------- * 74F08 Quadruple 2-input Positive-And Gates * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names .subckt 74F08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_F08 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F08 ugate ( + tplhty=3.8ns tphlty=3.6ns + tplhmn=2.2ns tplhmx=6.6ns + tphlmn=1.7ns tphlmx=6.3ns + ) *--------- * 74HC08 Quadruple 2-input Positive-And Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_HC08 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC08 ugate ( + tplhty=10ns tplhmx=25ns + tphlty=10ns tphlmx=25ns + ) *--------- * 74LS08 Quadruple 2-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_LS08 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS08 ugate ( + tplhty=8ns tplhmx=15ns + tphlty=10ns tphlmx=20ns + ) *--------- * 74S08 Quadruple 2-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74S08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_S08 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S08 ugate ( + tplhty=4.5ns tplhmx=7ns + tphlty=5ns tphlmx=7.5ns + ) *------------------------------------------------------------------------- * 7409 Quadruple 2-input Positive-And Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7409 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_09 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_09 ugate ( + tplhty=21ns tplhmx=32ns + tphlty=16ns tphlmx=24ns + ) *--------- * 74ALS09 Quadruple 2-input Positive-And Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS09 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_ALS09 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS09 ugate ( + tplhmn=23ns tplhmx=54ns + tphlmn=5ns tphlmx=15ns + ) *--------- * 74HC09 Quadruple 2-input Positive-And Gates with Open-Collector Outputs * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC09 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_HC09 IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC09 ugate ( + tplhty=13ns tplhmx=31ns + tphlty=10ns tphlmx=25ns + ) *--------- * 74LS09 Quadruple 2-input Positive-And Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS09 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_LS09 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS09 ugate ( + tplhty=20ns tplhmx=35ns + tphlty=17ns tphlmx=35ns + ) *--------- * 74S09 Quadruple 2-input Positive-And Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74S09 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_S09 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S09 ugate ( + tplhty=6.5ns tplhmx=10ns + tphlty=6.5ns tphlmx=10ns + ) *------------------------------------------------------------------------- * 7410 Triple 3-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7410 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_10 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_10 ugate ( + tplhty=11ns tplhmx=22ns + tphlty=7ns tphlmx=15ns + ) *--------- * 74AC10 Triple 3-input Positive-Nand Gates * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74AC10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_AC10 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC10 ugate ( + tplhmn=1ns tplhty=4.5ns + tplhmx=8ns tphlmn=1ns + tphlty=4ns tphlmx=6.5ns + ) *--------- * 74ACT10 Triple 3-input Positive-Nand Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74ACT10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_ACT10 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT10 ugate ( + tplhmn=1.5ns tplhty=5.8ns + tplhmx=8.9ns tphlmn=1.5ns + tphlty=5.7ns tphlmx=8.2ns + ) *--------- * 74ALS10A Triple 3-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS10A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_ALS10A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS10A ugate ( + tplhmn=2ns tplhmx=11ns + tphlmn=2ns tphlmx=10ns + ) *--------- * 74AS10 Triple 3-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74AS10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_AS10 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS10 ugate ( + tplhmn=1ns tplhmx=4.5ns + tphlmn=1ns tphlmx=4.5ns + ) *--------- * 74F10 Triple 3-input Positive-Nand Gates * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names .subckt 74F10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_F10 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F10 ugate ( + tplhty=3.3ns tphlty=2.8ns + tplhmn=1.6ns tplhmx=6ns + tphlmn=1ns tphlmx=5.3ns + ) *--------- * 74H10 Triple 3-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74H10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_H10 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H10 ugate ( + tplhty=5.9ns tplhmx=10ns + tphlty=6.3ns tphlmx=10ns + ) *--------- * 74HC10 Triple 3-input Positive-Nand Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_HC10 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC10 ugate ( + tplhty=10ns tplhmx=24ns + tphlty=10ns tphlmx=24ns + ) *--------- * 74L10 Triple 3-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 54L10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_L10 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L10 ugate ( + tplhty=35ns tplhmx=60ns + tphlty=31ns tphlmx=60ns + ) *--------- * 74LS10 Triple 3-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_LS10 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS10 ugate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *--------- * 74S10 Triple 3-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74S10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_S10 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S10 ugate ( + tplhty=3ns tplhmx=4.5ns + tphlty=3ns tphlmx=5ns + ) *------------------------------------------------------------------------- * 74AC11 Triple 3-input Positive-And Gates * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74AC11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_AC11 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC11 ugate ( + tplhmn=1ns tplhty=4ns + tplhmx=8.5ns tphlmn=1ns + tphlty=4ns tphlmx=7.5ns + ) *--------- * 74ACT11 Triple 3-input Positive-And Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74ACT11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_ACT11 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT11 ugate ( + tplhty=4.7ns tphlty=6ns + ) *--------- * 74ALS11A Triple 3-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS11A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_ALS11A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS11A ugate ( + tplhmn=2ns tplhmx=13ns + tphlmn=2ns tphlmx=10ns + ) *--------- * 74AS11 Triple 3-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74AS11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_AS11 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS11 ugate ( + tplhmn=1ns tplhmx=6ns + tphlmn=1ns tphlmx=5.5ns + ) *--------- * 74F11 Triple 3-input Positive-And Gates * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names .subckt 74F11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_F11 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F11 ugate ( + tplhty=3.8ns tphlty=3.7ns + tplhmn=2.2ns tplhmx=6.6ns + tphlmn=1.7ns tphlmx=6.5ns + ) *--------- * 74H11 Triple 3-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985 * tdn 06/23/89 Update interface and model names .subckt 74H11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_H11 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H11 ugate ( + tplhty=7.6ns tplhmx=12ns + tphlty=8.8ns tphlmx=12ns + ) *--------- * 74HC11 Triple 3-input Positive-And Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/23/89 Update interface and model names .subckt 74HC11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_HC11 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC11 ugate ( + tplhty=10ns tplhmx=25ns + tphlty=10ns tphlmx=25ns + ) *--------- * 74LS11 Triple 3-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_LS11 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS11 ugate ( + tplhty=8ns tplhmx=15ns + tphlty=10ns tphlmx=20ns + ) *--------- * 74S11 Triple 3-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74S11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_S11 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S11 ugate ( + tplhty=4.5ns tplhmx=7ns + tphlty=5ns tphlmx=7.5ns + ) *-------------------------------------------------------------------------- * 7412 Triple 3-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7412 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_12 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_12 ugate ( + tplhty=35ns tplhmx=45ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74ALS12A Triple 3-input Positive-Nand Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names .subckt 74ALS12A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_ALS12A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS12A ugate ( + tplhmn=23ns tplhmx=54ns + tphlmn=5ns tphlmx=18ns + ) *--------- * 74LS12 Triple 3-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS12 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_LS12 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS12 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *------------------------------------------------------------------------- * 7413 Dual 4-input Positive-Nand Schmitt Triggers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7413 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled in the AtoD interface U1 nand(4) DPWR DGND + A B C D Y + D_13 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_13 ugate ( + tplhty=18ns tplhmx=27ns + tphlty=15ns tphlmx=22ns + ) *--------- * 74LS13 Dual 4-input Positive-Nand Schmitt Triggers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS13 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled in the AtoD interface U1 nand(4) DPWR DGND + A B C D Y + D_LS13 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS13 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=18ns tphlmx=27ns + ) *------------------------------------------------------------------------- * 7414 Hex Schmitt-Trigger Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7414 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface U1 inv DPWR DGND + A Y + D_14 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_14 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=15ns tphlmx=22ns + ) *--------- * 74AC14 Hex Schmitt-Trigger Inverters * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74AC14 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface U1 inv DPWR DGND + A Y + D_AC14 IO_AC_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC14 ugate ( + tplhty=7ns tphlty=6ns + tplhmn=1ns tplhmx=11ns + tphlmn=1ns tphlmx=9.5ns + ) *--------- * 74ACT14 Hex Schmitt-Trigger Inverters * * The Advanced CMOS Logic ICs Data Book, RCA * cv 07/13/90 Created from LS .subckt 74ACT14 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface U1 inv DPWR DGND + A Y + D_ACT14 IO_ACT_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT14 ugate ( + tplhmn=3.7ns tplhmx=13.2ns + tphlmn=2.4ns tphlmx=8.6ns + ) *--------- * 74LS14 Hex Schmitt-Trigger Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 74LS14 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface U1 inv DPWR DGND + A Y + D_LS14 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS14 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=15ns tphlmx=22ns + ) *--------- * 74HC14 Hex Schmitt-Trigger Inverters * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/26/89 Update interface and model names .subckt 74HC14 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface U1 inv DPWR DGND + A Y + D_HC14 IO_HC_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC14 ugate ( + tplhty=12ns tplhmx=31ns + tphlty=12ns tphlmx=31ns + ) *------------------------------------------------------------------------- * 74ALS15A Triple 3-input Positive-And Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS15A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_ALS15A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS15A ugate ( + tplhmn=20ns tplhmx=45ns + tphlmn=6ns tphlmx=20ns + ) *--------- * 74H15 Triple 3-input Positive-And Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74H15 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_H15 IO_H_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H15 ugate ( + tplhty=12ns tplhmx=18ns + tphlty=9ns tphlmx=13ns + ) *--------- * 74LS15 Triple 3-input Positive-And Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS15 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_LS15 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS15 ugate ( + tplhty=20ns tplhmx=35ns + tphlty=17ns tphlmx=35ns + ) *--------- * 74S15 Triple 3-input Positive-And Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74S15 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_S15 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S15 ugate ( + tplhty=5.5ns tplhmx=8.5ns + tphlty=6ns tphlmx=9ns + ) *------------------------------------------------------------------------- * 7416 Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7416 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_16 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_16 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=15ns tphlmx=23ns + ) *------------------------------------------------------------------------- * 7417 Hex Buffers/Drivers with Open-Collector High-Voltage Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7417 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_17 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_17 ugate ( + tplhty=6ns tplhmx=10ns + tphlty=20ns tphlmx=30ns + ) *------------------------------------------------------------------------- * 74LS18 Schmitt-Trigger 4-input Positive-Nand Gates with Totem-Pole Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS18 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface U1 nand(4) DPWR DGND + A B C D Y + D_LS18 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS18 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=37ns tphlmx=55ns + ) *------------------------------------------------------------------------- * 74LS19 Schmitt-Trigger Inverters with Totem-Pole Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS19 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters. * Hysteresis is modeled in the AtoD interface. U1 inv DPWR DGND + A Y + D_LS19 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS19 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=18ns tphlmx=30ns + ) *------------------------------------------------------------------------- * 7420 Dual 4-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7420 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_20 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_20 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74AC20 Dual 4-input Positive-Nand Gates * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74AC20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_AC20 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC20 ugate ( + tplhmn=1ns tplhty=5ns + tplhmx=8ns tphlmn=1ns + tphlty=4ns tphlmx=7ns + ) *--------- * 74ACT20 Dual 4-input Positive-Nand Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74ACT20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_ACT20 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT20 ugate ( + tplhmn=1.5ns tplhty=5.6ns + tplhmx=9.1ns tphlmn=1.5ns + tphlty=6.1ns tphlmx=9.2ns + ) *--------- * 74ALS20A Dual 4-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS20A A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_ALS20A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS20A ugate ( + tplhty=7ns tphlty=6ns + tplhmn=3ns tplhmx=11ns + tphlmn=3ns tphlmx=10ns + ) *--------- * 74AS20 Dual 4-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74AS20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_AS20 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS20 ugate ( + tplhmn=1ns tplhmx=5ns + tphlmn=1ns tphlmx=4.5ns + ) *--------- * 74F20 Dual 4-input Positive-Nand Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names .subckt 74F20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_F20 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F20 ugate ( + tplhty=3.3ns tphlty=2.8ns + tplhmn=1.6ns tplhmx=6ns + tphlmn=1ns tphlmx=5.3ns + ) *--------- * 74H20 Dual 4-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74H20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_H20 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H20 ugate ( + tplhty=6ns tplhmx=10ns + tphlty=7ns tphlmx=10ns + ) *--------- * 74HC20 Dual 4-input Positive-Nand Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/26/89 Update interface and model names .subckt 74HC20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_HC20 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC20 ugate ( + tplhty=14ns tplhmx=28ns + tphlty=14ns tphlmx=28ns + ) *--------- * 54L20 Dual 4-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 54L20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_L20 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L20 ugate ( + tplhty=35ns tplhmx=60ns + tphlty=31ns tphlmx=60ns + ) *--------- * 74LS20 Dual 4-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_LS20 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS20 ugate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *--------- * 74S20 Dual 4-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74S20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_S20 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S20 ugate ( + tplhty=3ns tplhmx=4.5ns + tphlty=3ns tphlmx=5ns + ) *------------------------------------------------------------------------- * 74AC21 Dual 4-input Positive-And Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74AC21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_AC21 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC21 ugate ( + tplhty=5.3ns tphlty=4.1ns + ) *--------- * 74ACT21 Dual 4-input Positive-And Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74ACT21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_ACT21 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT21 ugate ( + tplhty=6.2ns tphlty=5ns + ) *--------- * 74ALS21A Dual 4-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS21A A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_ALS21A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS21A ugate ( + tplhty=8.3ns tphlty=6.5ns + tplhmn=4ns tplhmx=15ns + tphlmn=2ns tphlmx=10ns + ) *--------- * 74AS21 Dual 4-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74AS21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_AS21 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS21 ugate ( + tplhmn=1ns tplhmx=6ns + tphlmn=1ns tphlmx=6ns + ) *--------- * 74F21 Dual 4-input Positive-And Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names .subckt 74F21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_F21 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F21 ugate ( + tplhty=4.3ns tphlty=3.8ns + ) *--------- * 74H21 Dual 4-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74H21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_H21 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H21 ugate ( + tplhty=7.6ns tplhmx=12ns + tphlty=8.8ns tphlmx=12ns + ) *--------- * 74HC21 Dual 4-input Positive-And Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/26/89 Update interface and model names .subckt 74HC21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_HC21 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC21 ugate ( + tplhty=14ns tplhmx=28ns + tphlty=14ns tphlmx=28ns + ) *--------- * 74LS21 Dual 4-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_LS21 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS21 ugate ( + tplhty=8ns tplhmx=15ns + tphlty=10ns tphlmx=20ns + ) *------------------------------------------------------------------------- * 7422 Dual 4-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7422 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_22 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_22 ugate ( + tplhty=35ns tplhmx=45ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74ALS22B Dual 4-input Positive-Nand Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS22B A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_ALS22B IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS22B ugate ( + tplhty=35ns tphlty=8ns + tplhmn=23ns tplhmx=45ns + tphlmn=4ns tphlmx=18ns + ) *--------- * 74H22 Dual 4-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74H22 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_H22 IO_H_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H22 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=7.5ns tphlmx=12ns + ) *--------- * 74LS22 Dual 4-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS22 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_LS22 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS22 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *--------- * 74S22 Dual 4-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74S22 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_S22 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S22 ugate ( + tplhty=5ns tphlty=4.5ns + tplhmn=2ns tplhmx=7.5ns + tphlmn=2ns tphlmx=7ns + ) *------------------------------------------------------------------------- * 7423 Dual 4-input Nor Gates with Strobe * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7423 1A 1B 1C 1D 1G X XBAR 1Y 2A 2B 2C 2D 2G 2Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * * The x and xbar inputs of this gate should only come from the following * gates: * '60 * * PSpice, however, will not check that it is properly connected. UIBUF bufa(2) DPWR DGND + 1G 2G 1G_BUF 2G_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + XBAR XBARC + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U11 aoi(2,5) DPWR DGND + 1A 1G_BUF + 1B 1G_BUF + 1C 1G_BUF + 1D 1G_BUF + X XBARC + 1Y + D_23 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U21 aoi(2,4) DPWR DGND + 2A 2G_BUF 2B 2G_BUF 2C 2G_BUF 2D 2G_BUF 2Y + D_23 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_23 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *------------------------------------------------------------------------- * 74LS24 Schmitt-Trigger 2-input Positive-Nand Gates w/ Totem-Pole Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS24 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled in the AtoD interface. U1 nand(2) DPWR DGND + A B Y + D_LS24 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS24 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=25ns tphlmx=40ns + ) *------------------------------------------------------------------------- * 7425 Dual 4-input Nor Gates with Strobe * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7425 A B C D G Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(4) DPWR DGND + A B C D X + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 nand(2) DPWR DGND + X G Y + D_25 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_25 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *------------------------------------------------------------------------- * 7426 High-Voltage Interface Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7426 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_26 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_26 ugate ( + tplhty=16ns tplhmx=24ns + tphlty=11ns tphlmx=17ns + ) *--------- * 74LS26 High-Voltage Interface Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS26 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS26 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS26 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *------------------------------------------------------------------------- * 7427 Triple 3-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7427 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_27 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_27 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=7ns tphlmx=11ns + ) *--------- * 74AC27 Triple 3-input Positive-Nor Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74AC27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_AC27 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC27 ugate ( + tplhmn=1.5ns tplhty=4.3ns + tplhmx=7.7ns tphlmn=1.5ns + tphlty=4.5ns tphlmx=8.1ns + ) *--------- * 74ACT27 Triple 3-input Positive-Nor Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74ACT27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_ACT27 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT27 ugate ( + tplhmn=1.5ns tplhty=5ns + tplhmx=10.1ns tphlmn=1.5ns + tphlty=6ns tphlmx=9.4ns + ) *--------- * 74ALS27 Triple 3-input Positive-Nor Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_ALS27 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS27 ugate ( + tplhmn=4ns tplhmx=15ns + tphlmn=3ns tphlmx=9ns + ) *--------- * 74AS27 Triple 3-input Positive-Nor Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74AS27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_AS27 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS27 ugate ( + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=4.5ns + ) *--------- * 74F27 Triple 3-input Positive-Nor Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names .subckt 74F27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_F27 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F27 ugate ( + tplhmn=1.2ns tphlmn=1ns + tplhty=3.1ns tplhmx=5.5ns + tphlty=2.1ns tphlmx=4.5ns + ) *--------- * 74HC27 Triple 3-input Positive-Nor Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/26/89 Update interface and model names .subckt 74HC27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_HC27 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC27 ugate ( + tplhty=10ns tplhmx=23ns + tphlty=10ns tphlmx=23ns + ) *--------- * 74LS27 Triple 3-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_LS27 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS27 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *------------------------------------------------------------------------- * 7428 Quadruple 2-input Positive-Nor Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7428 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_28 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_28 ugate ( + tplhty=6ns tplhmx=9ns + tphlty=8ns tphlmx=12ns + ) *--------- * 74ALS28A Quadruple 2-input Positive-Nor Buffers * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS28A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_ALS28A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS28A ugate ( + tplhty=4ns tphlty=4ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=7ns + ) *--------- * 74LS28 Quadruple 2-input Positive-Nor Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS28 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_LS28 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS28 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *------------------------------------------------------------------------- * 7430 8-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7430 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_30 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_30 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74AC30 8-input Positive-Nand Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74AC30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_AC30 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC30 ugate ( + tplhmn=1.5ns tplhty=4.8ns + tplhmx=7.2ns tphlmn=1.5ns + tphlty=4.8ns tphlmx=7.4ns + ) *--------- * 74ACT30 8-input Positive-Nand Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74ACT30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_ACT30 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT30 ugate ( + tplhmn=1.5ns tplhty=5.4ns + tplhmx=8.5ns tphlmn=1.5ns + tphlty=5.9ns tphlmx=8.7ns + ) *--------- * 74ALS30A 8-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS30A A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_ALS30A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS30A ugate ( + tplhmn=3ns tplhmx=10ns + tphlmn=3ns tphlmx=12ns + ) *--------- * 74AS30 8-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74AS30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_AS30 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS30 ugate ( + tplhmn=1ns tplhmx=5ns + tphlmn=1ns tphlmx=4.5ns + ) *--------- * 74F30 8-input Positive-Nand Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names .subckt 74F30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_F30 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F30 ugate ( + tplhty=3.1ns tphlty=2.6ns + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=5ns + ) *--------- * 74H30 8-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74H30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_H30 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H30 ugate ( + tplhty=6.8ns tplhmx=10ns + tphlty=8.9ns tphlmx=12ns + ) *--------- * 74HC30 8-input Positive-Nand Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/26/89 Update interface and model names .subckt 74HC30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_HC30 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC30 ugate ( + tplhty=15ns tplhmx=33ns + tphlty=15ns tphlmx=33ns + ) *--------- * 54L30 8-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 54L30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_L30 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L30 ugate ( + tplhty=35ns tplhmx=60ns + tphlty=70ns tphlmx=100ns + ) *--------- * 74LS30 8-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_LS30 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS30 ugate ( + tplhty=8ns tplhmx=15ns + tphlty=13ns tphlmx=20ns + ) *--------- * 74S30 8-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74S30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_S30 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S30 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=4.5ns tphlmx=7ns + ) *------------------------------------------------------------------------- * 74LS31 Delay Elements * * The TTL Data Book, Vol 2, 1985, TI * tdn 8/10/89 Update interface and model names .subckt 74LS31 1A 2A 3A 3B 1Y 2Y 3Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: In this IC, there are 2 inverting, & 2 non-inverting delay gates, and * 2 2-input NAND gates. However, the model here only contains 1 gate per type. * If more gates are needed, please call the SUBCKT twice. U1 inv DPWR DGND + 1A 1Y + D_LS31_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf DPWR DGND + 2A 2Y + D_LS31_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 nand(2) DPWR DGND + 3A 3B 3Y + D_LS31_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS31_1 ugate ( + tplhmn=22ns tplhty=32ns + tplhmx=65ns tphlmn=13ns + tphlty=23ns tphlmx=45ns + ) .model D_LS31_2 ugate ( + tplhmn=31ns tplhty=45ns + tplhmx=80ns tphlmn=30ns + tphlty=48ns tphlmx=95ns + ) .model D_LS31_3 ugate ( + tplhmn=2ns tplhty=6ns + tplhmx=15ns tphlmn=2ns + tphlty=6ns tphlmx=15ns + ) *------------------------------------------------------------------------- * 7432 Quadruple 2-input Positive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7432 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_32 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_32 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=14ns tphlmx=22ns + ) *--------- * 74AC32 Quadruple 2-input Positive-Or Gates * * The FACT Data Book, 1987, Fairchild * cv 06/21/90 Created from LS .subckt 74AC32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_AC32 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC32 ugate ( + tplhmn=1ns tplhty=5.5ns + tplhmx=8.5ns tphlmn=1ns + tphlty=5ns tphlmx=7.5ns + ) *--------- * 74ACT32 Quadruple 2-input Positive-Or Gates * * The Advanced CMOS Logic Data Book, 1987, TI * cv 06/21/90 Created from LS .subckt 74ACT32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_ACT32 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT32 ugate ( + tplhty=6ns tphlty=4.5ns + ) *--------- * 74ALS32 Quadruple 2-input Positive-Or Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_ALS32 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS32 ugate ( + tplhty=8.8ns tphlty=6.8ns + tplhmn=3ns tplhmx=14ns + tphlmn=3ns tphlmx=12ns + ) *--------- * 74AS32 Quadruple 2-input Positive-Or Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74AS32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_AS32 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS32 ugate ( + tplhmn=1ns tplhmx=5.8ns + tphlmn=1ns tphlmx=5.8ns + ) *--------- * 74F32 Quadruple 2-input Positive-Or Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names .subckt 74F32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_F32 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F32 ugate ( + tplhty=3.8ns tphlty=3.6ns + tplhmn=2.2ns tplhmx=6.6ns + tphlmn=2.2ns tphlmx=6.3ns + ) *--------- * 74HC32 Quadruple 2-input Positive-Or Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/26/89 Update interface and model names .subckt 74HC32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_HC32 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC32 ugate ( + tplhty=10ns tplhmx=25ns + tphlty=10ns tphlmx=25ns + ) *--------- * 74LS32 Quadruple 2-input Positive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_LS32 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS32 ugate ( + tplhty=14ns tplhmx=22ns + tphlty=14ns tphlmx=22ns + ) *--------- * 74S32 Quadruple 2-input Positive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74S32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_S32 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S32 ugate ( + tplhty=4ns tplhmx=7ns + tphlty=4ns tphlmx=7ns + ) *------------------------------------------------------------------------- * 7433 Quadruple 2-input Positive-Nor Buffers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7433 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_33 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_33 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=12ns tphlmx=18ns + ) *--------- * 74ALS33A Quadruple 2-input Positive-Nor Buffers w/ Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS33A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_ALS33A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS33A ugate ( + tplhty=18ns tphlty=7ns + tplhmn=10ns tplhmx=33ns + tphlmn=2ns tphlmx=12ns + ) *--------- * 74LS33 Quadruple 2-input Positive-Nor Buffers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS33 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_LS33 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS33 ugate ( + tplhty=20ns tplhmx=32ns + tphlty=18ns tphlmx=28ns + ) *------------------------------------------------------------------------- * 74ALS34 Hex Noninverters * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS34 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_ALS34 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS34 ugate ( + tplhty=9.4ns tphlty=5ns + tplhmn=4ns tplhmx=15ns + tphlmn=1ns tphlmx=10ns + ) *--------- * 74AS34 Hex Noninverters * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74AS34 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_AS34 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS34 ugate ( + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=6ns + ) *------------------------------------------------------------------------- * 74ALS35A Hex Noninverters with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS35A A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_ALS35A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS35A ugate ( + tplhty=34ns tphlty=9ns + tplhmn=20ns tplhmx=50ns + tphlmn=2ns tphlmx=14ns + ) *--------- * 74HC35 Hex Noninverters with Open-Collector Outputs * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/26/89 Update interface and model names .subckt 74HC35 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_HC35 IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC35 ugate ( + tplhmx=28ns tphlmx=28ns + ) *--------- * 74HCT35 Hex Noninverters with Open-Collector Outputs * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/26/89 Update interface and model names .subckt 74HCT35 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_HCT35 IO_HCT_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HCT35 ugate ( + tplhmx=30ns tphlmx=30ns + ) *------------------------------------------------------------------------- * 74F36 Quadruple 2-input Positive-Nor Gate * * The F Logic Data Book, 1987, TI * tdn 08/10/89 Update interface and model names .subckt 74F36 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_F36 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F36 ugate ( + tplhmn=1.7ns tplhty=4ns + tplhmx=6.5ns tphlmn=1ns + tphlty=2.8ns tphlmx=5.3ns + ) *--------- * 74HC36 Quadruple 2-input Positive-Nor Gate * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 08/10/89 Update interface and model names .subckt 74HC36 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_HC36 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC36 ugate ( + tphlty=10ns tphlmx=25ns + tplhty=10ns tplhmx=25ns + ) *------------------------------------------------------------------------- * 7437 Quadruple 2-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7437 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_37 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_37 ugate ( + tplhty=13ns tphlty=8ns + tplhmx=22ns tphlmx=15ns + ) *--------- * 74ALS37A Quadruple 2-input Positive-Nand Buffers * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS37A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS37A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS37A ugate ( + tplhty=4ns tphlty=5ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=7ns + ) *--------- * 74LS37 Quadruple 2-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS37 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS37 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS37 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *--------- * 74S37 Quadruple 2-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74S37 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_S37 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S37 ugate ( + tplhty=4ns tplhmx=6.5ns + tphlty=4ns tphlmx=6.5ns + ) *------------------------------------------------------------------------- * 7438 Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7438 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_38 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_38 ugate ( + tplhty=14ns tplhmx=22ns + tphlty=11ns tphlmx=18ns + ) *--------- * 74ALS38A Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS38A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS38A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS38A ugate ( + tplhty=18ns tphlty=7ns + tplhmn=10ns tplhmx=33ns + tphlmn=2ns tphlmx=12ns + ) *--------- * 74F38 Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs * * (c) 1988 National Semiconductor. Updated 8/20/90 .subckt 74F38 A B OBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B OBAR + D_74F38 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_74F38 ugate ( + tplhmn=6.5ns tplhty=9.7ns + tplhmx=13ns tphlmn=1ns + tphlty=2.1ns tphlmx=5.5ns + ) *--------- * 74LS38 Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS38 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS38 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS38 ugate ( + tplhty=20ns tplhmx=32ns + tphlty=18ns tphlmx=28ns + ) *--------- * 74S38 Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74S38 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_S38 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S38 ugate ( + tplhty=6.5ns tplhmx=10ns + tphlty=6.5ns tphlmx=10ns + ) *------------------------------------------------------------------------- * 7439 Quadruple 2-input Positive Nand Buffers with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/10/89 Update interface and model names .subckt 7439 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_39 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_39 ugate ( + tphlmx=18ns tplhmx=22ns + ) *------------------------------------------------------------------------- * 7440 Dual 4-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7440 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_40 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_40 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74ALS40A Dual 4-input Positive-Nand Buffers * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names .subckt 74ALS40A A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_ALS40A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS40A ugate ( + tplhty=5ns tphlty=5ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=7ns + ) *--------- * 74H40 Dual 4-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74H40 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_H40 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H40 ugate ( + tplhty=8.5ns tplhmx=12ns + tphlty=6.5ns tphlmx=12ns + ) *--------- * 74LS40 Dual 4-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74LS40 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_LS40 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS40 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *--------- * 74S40 Dual 4-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 74S40 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_S40 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S40 ugate ( + tplhty=4ns tplhmx=6.5ns + tphlty=4ns tphlmx=6.5ns + ) *------------------------------------------------------------------------- * 7442A 4-line to 10-line Decoders (1-of-10) * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7442A A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D0_GATE IO_STD U2 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_42A_1 IO_STD MNTYMXDLY={MNTYMXDLY} U3 nanda(4,10) DPWR DGND + PBAR QBAR RBAR SBAR + P QBAR RBAR SBAR + PBAR Q RBAR SBAR + P Q RBAR SBAR + PBAR QBAR R SBAR + P QBAR R SBAR + PBAR Q R SBAR + P Q R SBAR + PBAR QBAR RBAR S + P QBAR RBAR S + Y0 Y1 Y2 Y3 Y4 + Y5 Y6 Y7 Y8 Y9 + D_42A_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_42A_1 ugate ( + tplhty=3ns tplhmx=5ns + tphlty=7ns tphlmx=5ns + ) .model D_42A_2 ugate ( + tplhty=10ns tplhmx=25ns + tphlty=14ns tphlmx=25ns + ) *--------- * 74HC42 4-line to 10-line Decoders(1-of-10) * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/27/89 Update interface and model names .subckt 74HC42 A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U1 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D0_GATE IO_HC U2 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D0_GATE IO_HC U3 nanda(4,10) DPWR DGND + PBAR QBAR RBAR SBAR + P QBAR RBAR SBAR + PBAR Q RBAR SBAR + P Q RBAR SBAR + PBAR QBAR R SBAR + P QBAR R SBAR + PBAR Q R SBAR + P Q R SBAR + PBAR QBAR RBAR S + P QBAR RBAR S + Y0 Y1 Y2 Y3 Y4 + Y5 Y6 Y7 Y8 Y9 + D_HC42 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC42 ugate ( + tplhty=18ns tplhmx=38ns + tphlty=18ns tphlmx=38ns + ) *--------- * 54L42 4-line to 10-line Decoders(1-of-10) * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 54L42 A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D0_GATE IO_L U2 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_L42_1 IO_L MNTYMXDLY={MNTYMXDLY} U3 nanda(4,10) DPWR DGND + PBAR QBAR RBAR SBAR + P QBAR RBAR SBAR + PBAR Q RBAR SBAR + P Q RBAR SBAR + PBAR QBAR R SBAR + P QBAR R SBAR + PBAR Q R SBAR + P Q R SBAR + PBAR QBAR RBAR S + P QBAR RBAR S + Y0 Y1 Y2 Y3 Y4 + Y5 Y6 Y7 Y8 Y9 + D_L42_2 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L42_1 ugate ( + tplhty=2ns tplhmx=10ns + tphlty=18ns tphlmx=20ns + ) .model D_L42_2 ugate ( + tplhmn=10ns tplhty=34ns + tplhmx=50ns tphlmn=10ns + tphlty=44ns tphlmx=60ns + ) *--------- * 74LS42 4-line to 10-line Decoders(1-of-10) * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74LS42 A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D0_GATE IO_LS U2 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_LS42_1 IO_LS MNTYMXDLY={MNTYMXDLY} U3 nanda(4,10) DPWR DGND + PBAR QBAR RBAR SBAR + P QBAR RBAR SBAR + PBAR Q RBAR SBAR + P Q RBAR SBAR + PBAR QBAR R SBAR + P QBAR R SBAR + PBAR Q R SBAR + P Q R SBAR + PBAR QBAR RBAR S + P QBAR RBAR S + Y0 Y1 Y2 Y3 Y4 + Y5 Y6 Y7 Y8 Y9 + D_LS42_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS42_1 ugate ( + tplhty=5ns tplhmx=5ns + tphlty=5ns tphlmx=5ns + ) .model D_LS42_2 ugate ( + tplhty=15ns tplhmx=25ns + tphlty=15ns tphlmx=25ns + ) *------------------------------------------------------------------------- * 7443A 4-line to 10-line Decoders(Gray-inputs) * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/21/89 Update interface and model names .subckt 7443A A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D0_GATE IO_STD U3 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_43A_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 nanda(4,10) DPWR DGND + P Q RBAR SBAR + PBAR QBAR R SBAR + P QBAR R SBAR + PBAR Q R SBAR + P Q R SBAR + PBAR QBAR RBAR S + P QBAR RBAR S + PBAR Q RBAR S + P Q RBAR S + PBAR QBAR R S + Y0 Y1 Y2 Y3 Y4 + Y5 Y6 Y7 Y8 Y9 + D_43A_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_43A_1 ugate ( + tplhty=3ns tplhmx=5ns + tphlty=7ns tphlmx=5ns + ) .model D_43A_2 ugate ( + tplhty=10ns tplhmx=25ns + tphlty=14ns tphlmx=25ns + ) *--------- * 74L43 4-line to 10-line Decoders(Gray-inputs) * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/21/89 Update interface and model names .subckt 54L43 A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U2 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D0_GATE IO_L U3 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_L43_1 IO_L MNTYMXDLY={MNTYMXDLY} U4 nanda(4,10) DPWR DGND + P Q RBAR SBAR + PBAR QBAR R SBAR + P QBAR R SBAR + PBAR Q R SBAR + P Q R SBAR + PBAR QBAR RBAR S + P QBAR RBAR S + PBAR Q RBAR S + P Q RBAR S + PBAR QBAR R S + Y0 Y1 Y2 Y3 Y4 + Y5 Y6 Y7 Y8 Y9 + D_L43_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L43_1 ugate ( + tplhty=2ns tplhmx=10ns + tphlty=18ns tphlmx=20ns + ) .model D_L43_2 ugate ( + tplhmn=10ns tplhty=34ns + tplhmx=50ns tphlmn=10ns + tphlty=44ns tphlmx=60ns + ) *------------------------------------------------------------------------- * 7444A 4-line to 10-line Decoders(Gray-inputs) * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/21/89 Update interface and model names .subckt 7444A A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D0_GATE IO_STD U3 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_44A_A IO_STD MNTYMXDLY={MNTYMXDLY} U4 nanda(4,10) DPWR DGND + PBAR Q RBAR SBAR + PBAR Q R SBAR + P Q R SBAR + P QBAR R SBAR + PBAR QBAR R SBAR + PBAR QBAR R S + P QBAR R S + P Q R S + PBAR Q R S + PBAR Q RBAR S + Y0 Y1 Y2 Y3 Y4 + Y5 Y6 Y7 Y8 Y9 + D_44A_B IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_44A_A ugate ( + tplhty=3ns tplhmx=5ns + tphlty=7ns tphlmx=5ns + ) .model D_44A_B ugate ( + tplhty=10ns tplhmx=25ns + tphlty=14ns tphlmx=25ns + ) *--------- * 74L44 4-line to 10-line Decoders(Gray-inputs) * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/21/89 Update interface and model names .subckt 54L44 A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U2 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D0_GATE IO_L U3 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_L44_A IO_L MNTYMXDLY={MNTYMXDLY} U4 nanda(4,10) DPWR DGND + PBAR Q RBAR SBAR + PBAR Q R SBAR + P Q R SBAR + P QBAR R SBAR + PBAR QBAR R SBAR + PBAR QBAR R S + P QBAR R S + P Q R S + PBAR Q R S + PBAR Q RBAR S + Y0 Y1 Y2 Y3 Y4 + Y5 Y6 Y7 Y8 Y9 + D_L44_B IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L44_A ugate ( + tplhty=2ns tplhmx=10ns + tphlty=18ns tphlmx=20ns + ) .model D_L44_B ugate ( + tplhmn=10ns tplhty=34ns + tplhmx=50ns tphlmn=10ns + tphlty=44ns tphlmx=60ns + ) *------------------------------------------------------------------------- * 7445 BCD-to-Decimal Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7445 A B C D OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF A_BUFBAR B_BUFBAR C_BUFBAR D_BUFBAR + D0_GATE IO_STD U2 nanda(4,10) DPWR DGND + A_BUFBAR B_BUFBAR C_BUFBAR D_BUFBAR + A_BUF B_BUFBAR C_BUFBAR D_BUFBAR + A_BUFBAR B_BUF C_BUFBAR D_BUFBAR + A_BUF B_BUF C_BUFBAR D_BUFBAR + A_BUFBAR B_BUFBAR C_BUF D_BUFBAR + A_BUF B_BUFBAR C_BUF D_BUFBAR + A_BUFBAR B_BUF C_BUF D_BUFBAR + A_BUF B_BUF C_BUF D_BUFBAR + A_BUFBAR B_BUFBAR C_BUFBAR D_BUF + A_BUF B_BUFBAR C_BUFBAR D_BUF + OUT0 OUT1 OUT2 OUT3 OUT4 + OUT5 OUT6 OUT7 OUT8 OUT9 + D_45 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_45 ugate ( + tplhmx=50ns tphlmx=50ns + ) *------------------------------------------------------------------------- * 7446A BCD-to-Seven-Segment Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7446A INA INB INC IND RBIBAR LTBAR BIBAR OUTA OUTB OUTC OUTD OUTE OUTF + OUTG + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + LTBAR BIBAR LTBAR_BUF BIBAR_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1A nanda(2,3) DPWR DGND + INA LTBAR_BUF INB LTBAR_BUF INC LTBAR_BUF TA1 TB1 TC1 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1V inva(2) DPWR DGND + IND RBIBAR TD1 RBI + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U201 nand(6) DPWR DGND + TA1 TB1 TC1 TD1 RBI LTBAR_BUF BIBARD + D0_GATE IO_STD U202 buf DPWR DGND + BIBARD BIBAR + D_46A_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2A nanda(2,4) DPWR DGND + TA1 BIBAR_BUF + TB1 BIBAR_BUF + TC1 BIBAR_BUF + TD1 BIBAR_BUF + TA2 TB2 TC2 TD2 + D0_GATE IO_STD UA ao(4,3) DPWR DGND + TB2 TD2 $D_HI $D_HI + TA1 TC2 $D_HI $D_HI + TA2 TB1 TC1 TD1 + OUTA + D_46A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB ao(3,3) DPWR DGND + TB2 TD2 $D_HI + TA2 TB1 TC2 + TA1 TB2 TC2 + OUTB + D_46A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC ao(3,2) DPWR DGND + TC2 TD2 $D_HI TA1 TB2 TC1 OUTC + D_46A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD ao(3,3) DPWR DGND + TA2 TB1 TC1 + TA1 TB1 TC2 + TA2 TB2 TC2 + OUTD + D_46A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE ao(2,2) DPWR DGND + TB1 TC2 TA2 $D_HI OUTE + D_46A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF ao(3,3) DPWR DGND + TA2 TB2 $D_HI + TB2 TC1 $D_HI + TA2 TC1 TD1 + OUTF + D_46A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UG ao(4,2) DPWR DGND + TA2 TB2 TC2 $D_HI TB1 TC1 TD1 LTBAR_BUF OUTG + D_46A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_46A_1 ugate ( + tplhmn=6ns tphlmn=6ns + ) .model D_46A_2 ugate ( + tplhmx=100ns tphlmx=100ns + ) *--------- * 74L46 BCD-TO-Seven-Segment Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74L46 INA INB INC IND RBIBAR LTBAR BIBAR OUTA OUTB OUTC OUTD OUTE OUTF + OUTG + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + LTBAR BIBAR LTBAR_BUF BIBAR_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1A nanda(2,3) DPWR DGND + INA LTBAR_BUF INB LTBAR_BUF INC LTBAR_BUF TA1 TB1 TC1 + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1V inva(2) DPWR DGND + IND RBIBAR TD1 RBI + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U201 nand(6) DPWR DGND + TA1 TB1 TC1 TD1 RBI LTBAR_BUF BIBARD + D0_GATE IO_L U202 buf DPWR DGND + BIBARD BIBAR + D_L46_1 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2A nanda(2,4) DPWR DGND + TA1 BIBAR_BUF + TB1 BIBAR_BUF + TC1 BIBAR_BUF + TD1 BIBAR_BUF + TA2 TB2 TC2 TD2 + D0_GATE IO_L UA ao(4,3) DPWR DGND + TB2 TD2 $D_HI $D_HI + TA1 TC2 $D_HI $D_HI + TA2 TB1 TC1 TD1 + OUTA + D_L46_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB ao(3,3) DPWR DGND + TB2 TD2 $D_HI + TA2 TB1 TC2 + TA1 TB2 TC2 + OUTB + D_L46_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC ao(3,2) DPWR DGND + TC2 TD2 $D_HI TA1 TB2 TC1 OUTC + D_L46_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD ao(3,3) DPWR DGND + TA2 TB1 TC1 + TA1 TB1 TC2 + TA2 TB2 TC2 + OUTD + D_L46_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE ao(2,2) DPWR DGND + TB1 TC2 $D_HI TA2 OUTE + D_L46_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF ao(3,3) DPWR DGND + TA2 TB2 $D_HI + TB2 TC1 $D_HI + TA2 TC1 TD1 + OUTF + D_L46_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UG ao(4,2) DPWR DGND + TA2 TB2 TC2 $D_HI TB1 TC1 TD1 LTBAR_BUF OUTG + D_L46_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L46_1 ugate ( + tplhmn=20ns tphlmn=20ns + ) .model D_L46_2 ugate ( + tplhmx=200ns tphlmx=200ns + ) *------------------------------------------------------------------------- * 7447A BCD-to-Seven-Segment Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7447A INA INB INC IND RBIBAR LTBAR BIBAR OUTA OUTB OUTC OUTD OUTE OUTF + OUTG + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + LTBAR BIBAR LTBAR_BUF BIBAR_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1A nanda(2,3) DPWR DGND + INA LTBAR_BUF INB LTBAR_BUF INC LTBAR_BUF TA1 TB1 TC1 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1V inva(2) DPWR DGND + IND RBIBAR TD1 RBI + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 nand(6) DPWR DGND + TA1 TB1 TC1 TD1 RBI LTBAR_BUF BIBARD + D0_GATE IO_STD U21 buf DPWR DGND + BIBARD BIBAR + D_47A_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2A nanda(2,4) DPWR DGND + TA1 BIBAR_BUF + TB1 BIBAR_BUF + TC1 BIBAR_BUF + TD1 BIBAR_BUF + TA2 TB2 TC2 TD2 + D0_GATE IO_STD UA ao(4,3) DPWR DGND + TB2 TD2 $D_HI $D_HI + TA1 TC2 $D_HI $D_HI + TA2 TB1 TC1 TD1 + OUTA + D_47A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB ao(3,3) DPWR DGND + TB2 TD2 $D_HI + TA2 TB1 TC2 + TA1 TB2 TC2 + OUTB + D_47A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC ao(3,2) DPWR DGND + TC2 TD2 $D_HI TA1 TB2 TC1 OUTC + D_47A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD ao(3,3) DPWR DGND + TA2 TB1 TC1 + TA1 TB1 TC2 + TA2 TB2 TC2 + OUTD + D_47A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE ao(2,2) DPWR DGND + TB1 TC2 $D_HI TA2 OUTE + D_47A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF ao(3,3) DPWR DGND + TA2 TB2 $D_HI + TB2 TC1 $D_HI + TA2 TC1 TD1 + OUTF + D_47A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UG ao(4,2) DPWR DGND + TA2 TB2 TC2 $D_HI TB1 TC1 TD1 LTBAR_BUF OUTG + D_47A_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_47A_1 ugate ( + tplhmn=6ns tphlmn=6ns + ) .model D_47A_2 ugate ( + tplhmx=100ns tphlmx=100ns + ) *--------- * 74L47 BCD-to-Seven-Segment Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74L47 INA INB INC IND RBIBAR LTBAR BIBAR OUTA OUTB OUTC OUTD OUTE OUTF + OUTG + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + LTBAR BIBAR LTBAR_BUF BIBAR_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1A nanda(2,3) DPWR DGND + INA LTBAR_BUF INB LTBAR_BUF INC LTBAR_BUF TA1 TB1 TC1 + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1V inva(2) DPWR DGND + IND RBIBAR TD1 RBI + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U2 nand(6) DPWR DGND + TA1 TB1 TC1 TD1 RBI LTBAR_BUF BIBARD + D0_GATE IO_L U21 buf DPWR DGND + BIBARD BIBAR + D_L47_1 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2A nanda(2,4) DPWR DGND + TA1 BIBAR_BUF + TB1 BIBAR_BUF + TC1 BIBAR_BUF + TD1 BIBAR_BUF + TA2 TB2 TC2 TD2 + D0_GATE IO_L UA ao(4,3) DPWR DGND + TB2 TD2 $D_HI $D_HI + TA1 TC2 $D_HI $D_HI + TA2 TB1 TC1 TD1 + OUTA + D_L47_2 IO_L_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB ao(3,3) DPWR DGND + TB2 TD2 $D_HI + TA2 TB1 TC2 + TA1 TB2 TC2 + OUTB + D_L47_2 IO_L_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC ao(3,2) DPWR DGND + TC2 TD2 $D_HI TA1 TB2 TC1 OUTC + D_L47_2 IO_L_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD ao(3,3) DPWR DGND + TA2 TB1 TC1 + TA1 TB1 TC2 + TA2 TB2 TC2 + OUTD + D_L47_2 IO_L_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE ao(2,2) DPWR DGND + TB1 TC2 $D_HI TA2 OUTE + D_L47_2 IO_L_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF ao(3,3) DPWR DGND + TA2 TB2 $D_HI + TB2 TC1 $D_HI + TA2 TC1 TD1 + OUTF + D_L47_2 IO_L_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UG ao(4,2) DPWR DGND + TA2 TB2 TC2 $D_HI TB1 TC1 TD1 LTBAR_BUF OUTG + D_L47_2 IO_L_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L47_1 ugate ( + tplhmn=20ns tphlmn=20ns + ) .model D_L47_2 ugate ( + tplhmx=200ns tphlmx=200ns + ) *--------- * 74LS47 BCD-to-Seven-Segment Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74LS47 INA INB INC IND RBIBAR LTBAR BIBAR OUTA OUTB OUTC OUTD OUTE + OUTF OUTG + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + LTBAR BIBAR LTBAR_BUF BIBAR_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1A nanda(2,3) DPWR DGND + INA LTBAR_BUF INB LTBAR_BUF INC LTBAR_BUF TA1 TB1 TC1 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1V inva(2) DPWR DGND + IND RBIBAR TD1 RBI + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 nand(6) DPWR DGND + TA1 TB1 TC1 TD1 RBI LTBAR_BUF BIBARD + D0_GATE IO_LS U21 buf DPWR DGND + BIBARD BIBAR + D_LS47_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2A nanda(2,4) DPWR DGND + TA1 BIBAR_BUF + TB1 BIBAR_BUF + TC1 BIBAR_BUF + TD1 BIBAR_BUF + TA2 TB2 TC2 TD2 + D0_GATE IO_LS UA ao(4,3) DPWR DGND + TB2 TD2 $D_HI $D_HI + TA1 TC2 $D_HI $D_HI + TA2 TB1 TC1 TD1 + OUTA + D_LS47_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB ao(3,3) DPWR DGND + TB2 TD2 $D_HI + TA2 TB1 TC2 + TA1 TB2 TC2 + OUTB + D_LS47_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC ao(3,2) DPWR DGND + TC2 TD2 $D_HI TA1 TB2 TC1 OUTC + D_LS47_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD ao(3,3) DPWR DGND + TA2 TB1 TC1 + TA1 TB1 TC2 + TA2 TB2 TC2 + OUTD + D_LS47_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE ao(2,2) DPWR DGND + TB1 TC2 $D_HI TA2 OUTE + D_LS47_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF ao(3,3) DPWR DGND + TA2 TB2 $D_HI + TB2 TC1 $D_HI + TA2 TC1 TD1 + OUTF + D_LS47_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UG ao(4,2) DPWR DGND + TA2 TB2 TC2 $D_HI TB1 TC1 TD1 LTBAR_BUF OUTG + D_LS47_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS47_1 ugate ( + tplhmn=20ns tphlmn=20ns + ) .model D_LS47_2 ugate ( + tplhmx=100ns tphlmx=100ns + ) *------------------------------------------------------------------------- * 7448 BCD-to-Seven-Segment Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7448 INA INB INC IND RBIBAR LTBAR BIBAR OUTA OUTB OUTC OUTD OUTE OUTF + OUTG + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + LTBAR BIBAR LTBAR_BUF BIBAR_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1A nanda(2,3) DPWR DGND + INA LTBAR_BUF INB LTBAR_BUF INC LTBAR_BUF TA1 TB1 TC1 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1V inva(2) DPWR DGND + IND RBIBAR TD1 RBI + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 nand(6) DPWR DGND + TA1 TB1 TC1 TD1 RBI LTBAR_BUF BIBARD + D0_GATE IO_STD U21 buf DPWR DGND + BIBARD BIBAR + D_48_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2A nanda(2,4) DPWR DGND + TA1 BIBAR_BUF + TB1 BIBAR_BUF + TC1 BIBAR_BUF + TD1 BIBAR_BUF + TA2 TB2 TC2 TD2 + D0_GATE IO_STD UA ao(4,3) DPWR DGND + TB2 TD2 $D_HI $D_HI + TA1 TC2 $D_HI $D_HI + TA2 TB1 TC1 TD1 + OUTA + D_48_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB ao(3,3) DPWR DGND + TB2 TD2 $D_HI + TA2 TB1 TC2 + TA1 TB2 TC2 + OUTB + D_48_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC ao(3,2) DPWR DGND + TC2 TD2 $D_HI TA1 TB2 TC1 OUTC + D_48_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD ao(3,3) DPWR DGND + TA2 TB1 TC1 + TA1 TB1 TC2 + TA2 TB2 TC2 + OUTD + D_48_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE ao(2,2) DPWR DGND + TB1 TC2 $D_HI TA2 OUTE + D_48_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF ao(3,3) DPWR DGND + TA2 TB2 $D_HI + TB2 TC1 $D_HI + TA2 TC1 TD1 + OUTF + D_48_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UG ao(4,2) DPWR DGND + TA2 TB2 TC2 $D_HI TB1 TC1 TD1 LTBAR_BUF OUTG + D_48_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_48_1 ugate ( + tplhmn=6ns tphlmn=6ns + ) .model D_48_2 ugate ( + tplhmx=100ns tphlmx=100ns + ) *--------- * 74LS48 BCD-to-Seven-Segment Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74LS48 INA INB INC IND RBIBAR LTBAR BIBAR OUTA OUTB OUTC OUTD OUTE + OUTF OUTG + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + LTBAR BIBAR LTBAR_BUF BIBAR_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1A nanda(2,3) DPWR DGND + INA LTBAR_BUF INB LTBAR_BUF INC LTBAR_BUF TA1 TB1 TC1 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1V inva(2) DPWR DGND + IND RBIBAR TD1 RBI + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 nand(6) DPWR DGND + TA1 TB1 TC1 TD1 RBI LTBAR_BUF BIBARD + D0_GATE IO_LS U21 buf DPWR DGND + BIBARD BIBAR + D_LS48_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2A nanda(2,4) DPWR DGND + TA1 BIBAR_BUF + TB1 BIBAR_BUF + TC1 BIBAR_BUF + TD1 BIBAR_BUF + TA2 TB2 TC2 TD2 + D0_GATE IO_LS UA ao(4,3) DPWR DGND + TB2 TD2 $D_HI $D_HI + TA1 TC2 $D_HI $D_HI + TA2 TB1 TC1 TD1 + OUTA + D_LS48_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB ao(3,3) DPWR DGND + TB2 TD2 $D_HI + TA2 TB1 TC2 + TA1 TB2 TC2 + OUTB + D_LS48_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC ao(3,2) DPWR DGND + TC2 TD2 $D_HI TA1 TB2 TC1 OUTC + D_LS48_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD ao(3,3) DPWR DGND + TA2 TB1 TC1 + TA1 TB1 TC2 + TA2 TB2 TC2 + OUTD + D_LS48_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE ao(2,2) DPWR DGND + TB1 TC2 $D_HI TA2 OUTE + D_LS48_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF ao(3,3) DPWR DGND + TA2 TB2 $D_HI + TB2 TC1 $D_HI + TA2 TC1 TD1 + OUTF + D_LS48_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UG ao(4,2) DPWR DGND + TA2 TB2 TC2 $D_HI TB1 TC1 TD1 LTBAR_BUF OUTG + D_LS48_2 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS48_1 ugate ( + tplhmn=20ns tphlmn=20ns + ) .model D_LS48_2 ugate ( + tplhmx=100ns tphlmx=100ns + ) *------------------------------------------------------------------------- * 7449 BCD-to-Seven-Segment Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7449 INA INB INC IND BIBAR OUTA OUTB OUTC OUTD OUTE OUTF OUTG + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + BIBAR BIBAR_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1V inva(4) DPWR DGND + INA INB INC IND TA1 TB1 TC1 TD1 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2A nanda(2,4) DPWR DGND + TA1 BIBAR_BUF + TB1 BIBAR_BUF + TC1 BIBAR_BUF + TD1 BIBAR_BUF + TA2 TB2 TC2 TD2 + D0_GATE IO_STD UA ao(4,3) DPWR DGND + TB2 TD2 $D_HI $D_HI + TA1 TC2 $D_HI $D_HI + TA2 TB1 TC1 TD1 + OUTA + D_49 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB ao(3,3) DPWR DGND + TB2 TD2 $D_HI + TA2 TB1 TC2 + TA1 TB2 TC2 + OUTB + D_49 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC ao(3,2) DPWR DGND + TC2 TD2 $D_HI TA1 TB2 TC1 OUTC + D_49 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD ao(3,3) DPWR DGND + TA2 TB1 TC1 + TA1 TB1 TC2 + TA2 TB2 TC2 + OUTD + D_49 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE ao(2,2) DPWR DGND + TB1 TC2 $D_HI TA2 OUTE + D_49 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF ao(3,3) DPWR DGND + TA2 TB2 $D_HI + TB2 TC1 $D_HI + TA2 TC1 TD1 + OUTF + D_49 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UG ao(3,2) DPWR DGND + TA2 TB2 TC2 TB1 TC1 TD1 OUTG + D_49 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_49 ugate ( + tplhmx=100ns tphlmx=100ns + ) *--------- * 74LS49 BCD-to-Seven-Segment Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74LS49 INA INB INC IND BIBAR OUTA OUTB OUTC OUTD OUTE OUTF OUTG + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + BIBAR BIBAR_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1V inva(4) DPWR DGND + INA INB INC IND TA1 TB1 TC1 TD1 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2A nanda(2,4) DPWR DGND + TA1 BIBAR_BUF + TB1 BIBAR_BUF + TC1 BIBAR_BUF + TD1 BIBAR_BUF + TA2 TB2 TC2 TD2 + D0_GATE IO_LS UA ao(4,3) DPWR DGND + TB2 TD2 $D_HI $D_HI + TA1 TC2 $D_HI $D_HI + TA2 TB1 TC1 TD1 + OUTA + D_LS49 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB ao(3,3) DPWR DGND + TB2 TD2 $D_HI + TA2 TB1 TC2 + TA1 TB2 TC2 + OUTB + D_LS49 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC ao(3,2) DPWR DGND + TC2 TD2 $D_HI TA1 TB2 TC1 OUTC + D_LS49 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD ao(3,3) DPWR DGND + TA2 TB1 TC1 + TA1 TB1 TC2 + TA2 TB2 TC2 + OUTD + D_LS49 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE ao(2,2) DPWR DGND + TB1 TC2 $D_HI TA2 OUTE + D_LS49 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF ao(3,3) DPWR DGND + TA2 TB2 $D_HI + TB2 TC1 $D_HI + TA2 TC1 TD1 + OUTF + D_LS49 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UG ao(3,2) DPWR DGND + TA2 TB2 TC2 TB1 TC1 TD1 OUTG + D_LS49 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS49 ugate ( + tplhmx=100ns tphlmx=100ns + ) *------------------------------------------------------------------------- * 7450 Dual 2-wide 2-input And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7450 1A 1B 1C 1D X XBAR 1Y 2A 2B 2C 2D 2Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * The x and xbar inputs of gate 1 of this chip can only come from the * following gates: * '50 * '60 * PSpice, however, will not check that these are properly connected. U1V inv DPWR DGND + XBAR XBARC + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 aoi(2,3) DPWR DGND + 1A 1B 1C 1D X XBARC 1Y + D_50_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 aoi(2,2) DPWR DGND + 2A 2B 2C 2D 2Y + D_50_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_50_1 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74H50 Dual 2-wide 2-input And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74H50 1A 1B 1C 1D X XBAR 1Y 2A 2B 2C 2D 2Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * The x and xbar inputs of gate 1 of this chip can only come from the * following gates: * 'H50 * 'H60 * 'H62 * PSpice, however, will not check that these are properly connected. U1V inv DPWR DGND + XBAR XBARC + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U1 aoi(2,3) DPWR DGND + 1A 1B 1C 1D X XBARC 1Y + D_H50_1 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 aoi(2,2) DPWR DGND + 2A 2B 2C 2D 2Y + D_H50_1 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H50_1 ugate ( + tplhty=6.8ns tplhmx=11ns + tphlty=6.2ns tphlmx=11ns + ) *------------------------------------------------------------------------- * 7451 And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7451 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + A B C D Y + D_51 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_51 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74H51 And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74H51 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + A B C D Y + D_H51 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H51 ugate ( + tplhty=6.8ns tplhmx=11ns + tphlty=6.2ns tphlmx=11ns + ) *--------- * 75HC51 And-Or-Invert Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/27/89 Update interface and model names .subckt 74HC51 A1 B1 C1 D1 E1 F1 Y1 A2 B2 C2 D2 Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(3,2) DPWR DGND + A1 B1 C1 D1 E1 F1 Y1 + D_HC51_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 aoi(2,2) DPWR DGND + A2 B2 C2 D2 Y2 + D_HC51_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC51_1 ugate ( + tplhty=15ns tplhmx=35ns + tphlty=15ns tphlmx=35ns + ) *--------- * 74L51 And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74L51 1A 1B 1C 1D 1E 1F 1Y 2A 2B 2C 2D 2Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(3,2) DPWR DGND + 1A 1B 1C 1D 1E 1F 1Y + D_L51 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 aoi(2,2) DPWR DGND + 2A 2B 2C 2D 2Y + D_L51 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L51 ugate ( + tplhty=50ns tplhmx=90ns + tphlty=35ns tphlmx=60ns + ) *--------- * 74LS51 And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74LS51 1A 1B 1C 1D 1E 1F 1Y 2A 2B 2C 2D 2Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(3,2) DPWR DGND + 1A 1B 1C 1D 1E 1F 1Y + D_LS51 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 aoi(2,2) DPWR DGND + 2A 2B 2C 2D 2Y + D_LS51 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS51 ugate ( + tplhty=12ns tplhmx=20ns + tphlty=12.5ns tphlmx=20ns + ) *--------- * 74S51 And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74S51 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + A B C D Y + D_S51 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S51 ugate ( + tplhty=3.5ns tplhmx=5.5ns + tphlty=3.5ns tphlmx=5.5ns + ) *------------------------------------------------------------------------- * 74H52 Expandable 4-wide And-Or Gates N package pin configuration * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74H52 A B C D E F G H I X Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * The x input of this gate should only come from the following gates: * 'H61 * PSpice, however, will not check that they are properly connected. U1 ao(3,5) DPWR DGND + A B $D_HI + C D E + F G $D_HI + H I $D_HI + X $D_HI $D_HI + Y + D_H52 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H52 ugate ( + tplhty=10.6ns tplhmx=15ns + tphlty=9.2ns tphlmx=15ns + ) *------------------------------------------------------------------------- * 7453 Expandable 4-wide And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7453 A B C D E F G H X XBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * The x and xbar inputs of this gate should only come from the following * chips: * '60 * '62 * PSpice, however, will not check that these are properly connected. U1 inv DPWR DGND + XBAR XBARC + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 aoi(2,5) DPWR DGND + A B + C D + E F + G H + X XBARC + Y + D_53 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_53 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74H53 Expandable 4-wide And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74H53 A B C D E F G H I X XBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * The x and xbar inputs of this gate should only come from the following * chips: * 'H60 * 'H62 * PSpice, however, will not check that these are properly connected. U1 inv DPWR DGND + XBAR XBARC + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 aoi(3,5) DPWR DGND + A B $D_HI + C D $D_HI + E F G + H I $D_HI + X XBARC $D_HI + Y + D_H53 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H53 ugate ( + tplhty=7ns tplhmx=11ns + tphlty=6.2ns tphlmx=11ns + ) *------------------------------------------------------------------------- * 7454 4-wide And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7454 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,4) DPWR DGND + A B C D E F G H Y + D_54 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_54 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- * 74H54 4-wide And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74H54 A B C D E F G H I Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(3,4) DPWR DGND + A B $D_HI + C D $D_HI + E F G + H I $D_HI + Y + D_H54 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H54 ugate ( + tplhty=7ns tplhmx=11ns + tphlty=6.2ns tphlmx=11ns + ) *--------- * 74L54 4-wide And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74L54 A B C D E F G H I J Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(3,4) DPWR DGND + A B $D_HI + C D E + F G H + I J $D_HI + Y + D_L54 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L54 ugate ( + tplhty=50ns tplhmx=90ns + tphlty=35ns tphlmx=60ns + ) *--------- * 74LS54 4-wide And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74LS54 A B C D E F G H I J Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(3,4) DPWR DGND + A B $D_HI + C D E + F G H + I J $D_HI + Y + D_LS54 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS54 ugate ( + tplhty=12ns tplhmx=20ns + tphlty=12.5ns tphlmx=20ns + ) *------------------------------------------------------------------------- * 74L55 2-wide 4-input And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74L55 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(4,2) DPWR DGND + A B C D E F G H Y + D_L55 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L55 ugate ( + tplhty=50ns tplhmx=90ns + tphlty=35ns tphlmx=60ns + ) *--------- * 74LS55 2-wide 4-input And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74LS55 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(4,2) DPWR DGND + A B C D E F G H Y + D_LS55 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS55 ugate ( + tplhty=12ns tplhmx=20ns + tphlty=12.5ns tphlmx=20ns + ) *--------- * 74H55 Expandable 2-wide 4-input And-Or-Invrt Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 74H55 A B C D E F G H X XBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * The x and xbar inputs of this gate should only come from the following * gates: * 'H60 * 'H62 * PSpice, however, will not check that these are properly connected. U1 inv DPWR DGND + XBAR XBARC + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 aoi(4,3) DPWR DGND + A B C D + E F G H + X XBARC $D_HI $D_HI + Y + D_H55 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H55 ugate ( + tplhty=7ns tplhmx=11ns + tphlty=6.5ns tphlmx=11ns + ) *------------------------------------------------------------------------- * 74LS56 Frequency Dividers(5 to 1, 5 to 1, and 10 to 1) * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/10/89 Update interface and model names .subckt 74LS56 CLR CLKA CLKB QA QB QC + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + CLKA CLKB CLKA_BUF CLKB_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + CLR CLRB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} X1 CLRB CLKA_BUF QAD DPWR DGND 56DIV5 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 CLRB CLKB_BUF QBD DPWR DGND 56DIV5 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3 CLRB QB1 QC DPWR DGND 56DIV2 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + QBD QBD QB QB1 + D_LS56_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 buf DPWR DGND + QAD QA + D_LS56_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 56DIV5 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(2) DPWR DGND + $D_HI CLR CLK + QB Q1 QB Q1 + Q1 Q2 $D_NC $D_NC + D_LS56_3 IO_LS MNTYMXDLY={MNTYMXDLY} UE2 jkff(1) DPWR DGND + $D_HI CLR CLK EN EN Q QB + D_LS56_4 IO_LS MNTYMXDLY={MNTYMXDLY} U3 ao(2,2) DPWR DGND + Q1 Q2 Q $D_HI EN + D0_GATE IO_LS .ends .subckt 56DIV2 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(1) DPWR DGND + $D_HI CLR CLK $D_HI $D_HI Q $D_NC + D_LS56_5 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS56_1 ugate ( + tplhty=5ns tplhmx=5ns + tphlty=5ns tphlmx=5ns + ) .model D_LS56_2 ugate ( + tplhty=9ns tplhmx=10ns + tphlty=5ns tphlmx=5ns + ) .model D_LS56_3 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=12ns + tppcqhlmx=25ns tpclkqhlty=1ns + tpclkqhlmx=1ns tpclkqlhty=1ns + tpclkqlhmx=1ns + ) .model D_LS56_4 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=12ns + tppcqhlmx=25ns tpclkqlhty=3ns + tpclkqlhmx=10ns tpclkqhlty=9ns + tpclkqhlmx=20ns + ) .model D_LS56_5 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=17ns + tppcqhlmx=30ns tpclkqlhty=4ns + tpclkqlhmx=5ns tpclkqhlty=10ns + tpclkqhlmx=10ns + ) *------------------------------------------------------------------------- * 74LS57 Frequency Dividers(6 to 1, 5 to 1, and 10 to 1) * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/10/89 Update interface and model names .subckt 74LS57 CLR CLKA CLKB QA QB QC + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + CLKA CLKB CLKA_BUF CLKB_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + CLR CLRB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} X1 CLRB CLKA_BUF QA DPWR DGND 57DIV6 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 CLRB CLKB_BUF QBD DPWR DGND 57DIV5 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3 CLRB QB1 QC DPWR DGND 57DIV2 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + QBD QBD QB QB1 + D_LS57_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 57DIV5 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(2) DPWR DGND + $D_HI CLR CLK + QB Q1 QB Q1 + Q1 Q2 $D_NC $D_NC + D_LS57_2 IO_LS MNTYMXDLY={MNTYMXDLY} UE2 jkff(1) DPWR DGND + $D_HI CLR CLK EN EN Q QB + D_LS57_3 IO_LS MNTYMXDLY={MNTYMXDLY} U3 ao(2,2) DPWR DGND + Q1 Q2 Q $D_HI EN + D0_GATE IO_LS .ends .subckt 57DIV2 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(1) DPWR DGND + $D_HI CLR CLK $D_HI $D_HI Q $D_NC + D_LS57_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 57DIV6 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(2) DPWR DGND + $D_HI CLR CLK + $D_HI J2 $D_HI J2 + Q1 Q2 $D_NC $D_NC + D_LS57_2 IO_LS MNTYMXDLY={MNTYMXDLY} UE3 jkff(1) DPWR DGND + $D_HI CLR CLK EN EN Q QB + D_LS57_5 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 ao(2,2) DPWR DGND + QB Q2 Q1 $D_HI J2 + D0_GATE IO_LS U2 ao(2,2) DPWR DGND + Q1 Q2 QB Q2 EN + D0_GATE IO_LS .ends .model D_LS57_1 ugate ( + tplhty=5ns tplhmx=5ns + tphlty=5ns tphlmx=5ns + ) .model D_LS57_2 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=17ns + tppcqhlmx=25ns tpclkqhlty=1ns + tpclkqhlmx=1ns tpclkqlhty=1ns + tpclkqlhmx=1ns + ) .model D_LS57_3 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=12ns + tppcqhlmx=25ns tpclkqlhty=3ns + tpclkqlhmx=10ns tpclkqhlty=9ns + tpclkqhlmx=20ns + ) .model D_LS57_4 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=17ns + tppcqhlmx=30ns tpclkqlhty=4ns + tpclkqlhmx=5ns tpclkqhlty=10ns + tpclkqhlmx=10ns + ) .model D_LS57_5 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=17ns + tppcqhlmx=30ns tpclkqlhty=14ns + tpclkqlhmx=25ns tpclkqhlty=18ns + tpclkqhlmx=30ns + ) *------------------------------------------------------------------------- * 7460 Dual 4-input Expanders * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7460 A B C D X XBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * this gate should only be connected to the following expandable gates: * '23 * '50 * '53 * connected by both x and xbar connections * PSpice, however, will not check that these are correctly connected. * ALSO this gate has no propagation delay. * There is a total propagation delay in the last level NOR gate in the * above chips, so when properly connected, the expanded combination will * work correctly. U1 and(4) DPWR DGND + A B C D X + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + X XBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} .ends *--------- * 74H60 Dual 4-input Expander * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74H60 A B C D X XBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * this gate should only be connected to the following expandable gates: * 'H50 * 'H53 * 'H55 * connected by both x and xbar connections * PSpice, however, will not check that these are correctly connected. * ALSO this gate has no propagation delay. * There is a total propagation delay in the last level NOR gate in the * above chips, so when properly connected, the expanded combination will * work correctly. * U1 and(4) DPWR DGND + A B C D X + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + X XBAR + D0_GATE IO_H IO_LEVEL={IO_LEVEL} .ends *------------------------------------------------------------------------- * 74H61 Triple 3-input Expanders * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74H61 A B C X + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * This gate should only be connected to the following expandable gates: * 'H52 * PSpice, however, will not check that these are properly connected. * ALSO this gate has no propagation delay. * There is a total propagation delay in the last level OR gate in the * above chip, so when properly connected, the expanded combination * will work correctly. U1 and(3) DPWR DGND + A B C X + D0_GATE IO_H IO_LEVEL={IO_LEVEL} .ends *------------------------------------------------------------------------- * 74H62 4-wide And-Or Expanders N package pin configuration * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74H62 A B C D E F G H I J X XBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * this gate should only be connected to the following expandable gates: * 'H50 * 'H53 * 'H55 * connected by both x and xbar connections * PSpice, however, will not check that these are properly connected. * ALSO this gate has no propagation delay. * There is a total propagation delay in the last level NOR gate in the * above chips, so when properly connected, the expanded combination will * work correctly. U1 ao(3,4) DPWR DGND + A B $D_HI + C D E + F G H + I J $D_HI + X + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + X XBAR + D0_GATE IO_H IO_LEVEL={IO_LEVEL} .ends *------------------------------------------------------------------------ * 74F64 4-2-3-2 Input And-Or-Invert Gates * * (c) 1988 National Semiconductor. Updated 8/20/90 .subckt 74F64 A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 D0 OBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(4,4) DPWR DGND + A0 B0 C0 D0 + A2 B2 $D_HI $D_HI + A1 B1 C1 $D_HI + B3 A3 $D_HI $D_HI + OBAR + D_F64 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F64 ugate ( + tplhmn=2.5ns tplhty=4.6ns + tplhmx=7.5ns tplhmn=1.5ns + tphlty=3.2ns tphlmx=5.5ns + ) *--------- * 74S64 4-2-3-2 Input And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74S64 A B C D E F G H I J K Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(4,4) DPWR DGND + A B C D + E F $D_HI $D_HI + G H I $D_HI + J K $D_HI $D_HI + Y + D_S64 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S64 ugate ( + tplhty=3.5ns tplhmx=5.5ns + tphlty=3.5ns tphlmx=5.5ns + ) *------------------------------------------------------------------------- * 74S65 4-2-3-2 Input And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74S65 A B C D E F G H I J K Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(4,4) DPWR DGND + A B C D + E F $D_HI $D_HI + G H I $D_HI + J K $D_HI $D_HI + Y + D_S65 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S65 ugate ( + tplhty=2ns tplhmx=7.5ns + tphlty=2ns tphlmx=8.5ns + ) *------------------------------------------------------------------------- * 74LS68 Dual 4-bit Decade Counter * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/11/89 Update interface and model names .subckt 74LS68 1CLRBAR 1CLKA 1CLKB 1QA 1QB 1QC 1QD 2CLRBAR 2CLK 2QA 2QB 2QC + 2QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + 1CLRBAR 2CLRBAR 1CLKB 1CLRB 2CLRB 1CLKBB + D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE1A jkff(1) DPWR DGND + $D_HI 1CLRB 1CLKA $D_HI $D_HI 1QA $D_NC + D_LS68_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE1B jkff(1) DPWR DGND + $D_HI 1CLRB 1CLK1 $D_HI $D_HI 1QBD 1QBB + D_LS68_2 IO_LS MNTYMXDLY={MNTYMXDLY} UE1C jkff(1) DPWR DGND + $D_HI 1CLRB 1QBD $D_HI $D_HI 1QC 1QCB + D_LS68_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE1D jkff(1) DPWR DGND + $D_HI 1CLRB 1CLK3 $D_HI $D_HI 1QD 1QDB + D_LS68_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE2A jkff(1) DPWR DGND + $D_HI 2CLRB 2CLK $D_HI $D_HI 2QAD $D_NC + D_LS68_5 IO_LS MNTYMXDLY={MNTYMXDLY} UE2B jkff(1) DPWR DGND + $D_HI 2CLRB 2CLK1 $D_HI $D_HI 2QBD 2QBB + D_LS68_6 IO_LS MNTYMXDLY={MNTYMXDLY} UE2C jkff(1) DPWR DGND + $D_HI 2CLRB 2QBD $D_HI $D_HI 2QC 2QCB + D_LS68_7 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE2D jkff(1) DPWR DGND + $D_HI 2CLRB 2CLK3 $D_HI $D_HI 2QD 2QDB + D_LS68_8 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 aoi(2,2) DPWR DGND + 1QB1 1QDB 1QDB 1QCB EN1 + D0_GATE IO_LS U3 aoi(2,2) DPWR DGND + 2QB1 2QDB 2QDB 2QCB EN2 + D0_GATE IO_LS U4 anda(2,4) DPWR DGND + 1CLKBB EN1 + 1CLKBB 1QDB + 2QAD EN2 + 2QAD 2QDB + 1CLK3 1CLK1 2CLK3 2CLK1 + D0_GATE IO_LS U5 bufa(5) DPWR DGND + 1QBD 1QBB 2QAD 2QBD 2QBB + 1QB 1QB1 2QA 2QB 2QB1 + D_LS68_9 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS68_1 ueff ( + twclkhmn=10ns twclklmn=10ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=20ns tppcqhlmx=30ns + tpclkqlhty=7ns tpclkqlhmx=11ns + tpclkqhlty=14ns tpclkqhlmx=21ns + ) .model D_LS68_2 ueff ( + twclkhmn=25ns twclklmn=25ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=15ns tppcqhlmx=25ns + tpclkqlhty=3ns tpclkqlhmx=7ns + tpclkqhlty=7ns tpclkqhlmx=13ns + ) .model D_LS68_3 ueff ( + twclkhmn=25ns twclklmn=25ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=20ns tppcqhlmx=30ns + tpclkqlhty=8ns tpclkqlhmx=10ns + tpclkqhlty=14ns tpclkqhlmx=19ns + ) .model D_LS68_4 ueff ( + twclkhmn=25ns twclklmn=25ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=20ns tppcqhlmx=30ns + tpclkqlhty=8ns tpclkqlhmx=12ns + tpclkqhlty=13ns tpclkqhlmx=20ns + ) .model D_LS68_5 ueff ( + twclkhmn=13ns twclklmn=13ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=15ns tppcqhlmx=25ns + tpclkqlhty=2ns tpclkqlhmx=6ns + tpclkqhlty=9ns tpclkqhlmx=16ns + ) .model D_LS68_6 ueff ( + twclkhmn=13ns twclklmn=13ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=15ns tppcqhlmx=25ns + tpclkqlhty=2ns tpclkqlhmx=3ns + tpclkqhlty=5ns tpclkqhlmx=8ns + ) .model D_LS68_7 ueff ( + twclkhmn=13ns twclklmn=13ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=20ns tppcqhlmx=30ns + tpclkqlhty=9ns tpclkqlhmx=11ns + tpclkqhlty=13ns tpclkqhlmx=16ns + ) .model D_LS68_8 ueff ( + twclkhmn=13ns twclklmn=13ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=20ns tppcqhlmx=30ns + tpclkqlhty=7ns tpclkqlhmx=8ns + tpclkqhlty=10ns tpclkqhlmx=13ns + ) .model D_LS68_9 ugate ( + tplhty=5ns tplhmx=5ns + tphlty=5ns tphlmx=5ns + ) *------------------------------------------------------------------------- * 74LS69 Dual 4-bit Binary Counter * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/11/89 Update interface and model names .subckt 74LS69 1CLRBAR 1CLKA 1CLKB 1QA 1QB 1QC 1QD 2CLRBAR 2CLKA 2QA 2QB 2QC + 2QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + 1CLRBAR 2CLRBAR 1CLRB 2CLRB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UE1A jkff(1) DPWR DGND + $D_HI 1CLRB 1CLKA $D_HI $D_HI 1QA $D_NC + D_LS69_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE1B jkff(1) DPWR DGND + $D_HI 1CLRB 1CLKB $D_HI $D_HI 1QBD $D_NC + D_LS69_2 IO_LS MNTYMXDLY={MNTYMXDLY} UE1C jkff(1) DPWR DGND + $D_HI 1CLRB 1QBD $D_HI $D_HI 1QCD $D_NC + D_LS69_3 IO_LS MNTYMXDLY={MNTYMXDLY} UE1D jkff(1) DPWR DGND + $D_HI 1CLRB 1CLKD $D_HI $D_HI 1QD $D_NC + D_LS69_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12B bufa(7) DPWR DGND + 1QBD 1QCD 1QCD 2QAD 2QBD 2QCD 2QCD + 1QB 1QC 1CLKD 2QA 2QB 2QC 2CLKD + D_LS69_5 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE2A jkff(1) DPWR DGND + $D_HI 2CLRB 2CLKA $D_HI $D_HI 2QAD $D_NC + D_LS69_6 IO_LS MNTYMXDLY={MNTYMXDLY} UE2B jkff(1) DPWR DGND + $D_HI 2CLRB 2CLKB $D_HI $D_HI 2QBD $D_NC + D_LS69_7 IO_LS MNTYMXDLY={MNTYMXDLY} UE2C jkff(1) DPWR DGND + $D_HI 2CLRB 2QBD $D_HI $D_HI 2QCD $D_NC + D_LS69_8 IO_LS MNTYMXDLY={MNTYMXDLY} UE2D jkff(1) DPWR DGND + $D_HI 2CLRB 2CLKD $D_HI $D_HI 2QD $D_NC + D_LS69_9 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2B buf DPWR DGND + 2QAD 2CLKB + D_LS69_10 IO_LS MNTYMXDLY={MNTYMXDLY} .model D_LS69_1 ueff ( + twclkhmn=10ns twclklmn=10ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=20ns tppcqhlmx=30ns + tpclkqlhty=7ns tpclkqlhmx=11ns + tpclkqhlty=14ns tpclkqhlmx=21ns + ) .model D_LS69_2 ueff ( + twclkhmn=20ns twclklmn=20ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=15ns tppcqhlmx=25ns + tpclkqlhty=2ns tpclkqlhmx=6ns + tpclkqhlty=9ns tpclkqhlmx=16ns + ) .model D_LS69_3 ueff ( + twclkhmn=20ns twclklmn=20ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=15ns tppcqhlmx=25ns + tpclkqlhty=2ns tpclkqlhmx=3ns + tpclkqhlty=7ns tpclkqhlmx=11ns + ) .model D_LS69_4 ueff ( + twclkhmn=20ns twclklmn=20ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=20ns tppcqhlmx=30ns + tpclkqlhty=4ns tpclkqlhmx=6ns + tpclkqhlty=9ns tpclkqhlmx=13ns + ) .model D_LS69_5 ugate ( + tphlty=5ns tphlmx=5ns + tplhty=5ns tplhmx=5ns + ) .model D_LS69_6 ueff ( + twclkhmn=10ns twclklmn=10ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=15ns tppcqhlmx=25ns + tpclkqlhty=2ns tpclkqlhmx=6ns + tpclkqhlty=9ns tpclkqhlmx=16ns + ) .model D_LS69_7 ueff ( + twclkhmn=10ns twclklmn=10ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=15ns tppcqhlmx=25ns + tpclkqhlty=5ns tpclkqhlmx=8ns + ) .model D_LS69_8 ueff ( + twclkhmn=10ns twclklmn=10ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=15ns tppcqhlmx=25ns + tpclkqlhty=4ns tpclkqlhmx=6ns + tpclkqhlty=8ns tpclkqhlmx=11ns + ) .model D_LS69_9 ueff ( + twclkhmn=10ns twclklmn=10ns + tsupcclkhmn=25ns twpclmn=15ns + tppcqhlty=20ns tppcqhlmx=30ns + tpclkqlhty=5ns tpclkqlhmx=8ns + tpclkqhlty=9ns tpclkqhlmx=14ns + ) .model D_LS69_10 ugate ( + tplhty=5ns tplhmx=5ns + ) .ends *------------------------------------------------------------------------- * 7470 And-Gated J-K Positive-Edge-Triggered Flip-Flops with Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7470 CLK PREBAR CLRBAR J1 J2 JBAR K1 K2 KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1V inva(3) DPWR DGND + CLK JBAR KBAR CLKBAR J3 K3 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2A anda(3,2) DPWR DGND + J3 J1 J2 K3 K1 K2 J K + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 jkff(1) DPWR DGND + PREBAR CLRBAR CLKBAR J K Q QBAR + D_70 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_70 ueff ( + tppcqlhmx=50ns tppcqhlmx=50ns + tpclkqlhty=27ns tpclkqlhmx=50ns + tpclkqhlty=18ns tpclkqhlmx=50ns + twclkhmx=20ns twclkhty=20ns + twclklmx=30ns twclklty=30ns + twpclmx=25ns twpclty=25ns + tsudclkmx=20ns tsudclkmn=20ns + thdclkmx=5ns thdclkmn=5ns + ) *------------------------------------------------------------------------- * 74H71 And-Or Gated J-K Master-Slave Flip-Flops with Preset * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/11/89 Update interface and model names .subckt 74H71 PREBAR CLK J1A J1B J2A J2B K1A K1B K2A K2B Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 buf DPWR DGND + PREBAR PREB + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + CLK CLK_BUF + D_H71_1 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 ao(2,2) DPWR DGND + J1A J1B J2A J2B J + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U3 ao(2,2) DPWR DGND + K1A K1B K2A K2A K + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U4 inva(3) DPWR DGND + J K CLK_BUF JB KB CLKB + D0_GATE IO_H UF1 srff(1) DPWR DGND + PREB $D_HI CLK_BUF W1 W2 Y YB + D_H71_2 IO_H MNTYMXDLY={MNTYMXDLY} UF2 srff(1) DPWR DGND + PREB $D_HI CLKB Y YB Q1 QB1 + D_H71_3 IO_H MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J K QBD J KB $D_HI W1 + D_H71_4 IO_H U6 ao(3,2) DPWR DGND + J K QD JB K $D_HI W2 + D_H71_4 IO_H U7 bufa(4) DPWR DGND + Q1 Q1 QB1 QB1 Q QD QBAR QBD + D_H71_4 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H71_1 ugate ( + tplhty=3ns tplhmx=3ns + ) .model D_H71_2 ugff ( + twghmn=12ns twpclmn=16ns + ) .model D_H71_3 ugff ( + twghmn=28ns twpclmn=16ns + tppcqhlty=3ns tppcqhlmx=10ns + tppcqlhty=9ns tppcqlhmx=21ns + tpgqlhty=11ns tpgqlhmx=18ns + tpgqhlty=19ns tpgqhlmx=24ns + ) .model D_H71_4 ugate ( + tphlty=3ns tphlmx=3ns + tplhty=3ns tplhmx=3ns + ) *--------- * 54L71 And Gated J-K Master-Slave Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/11/89 Update interface and model names .subckt 54L71 PREBAR CLRBAR CLK S1 S2 S3 R1 R2 R3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + PREBAR CLRBAR CLK PREB CLRB CLK_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U2 anda(3,2) DPWR DGND + S1 S2 S3 R1 R2 R3 S R + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U3 inva(3) DPWR DGND + CLK_BUF PREB CLRB CLKB PRE CLR + D0_GATE IO_L UF1 srff(1) DPWR DGND + PREB CLRB CLK_BUF S R Y YB + D_L71_1 IO_L MNTYMXDLY={MNTYMXDLY} UF2 srff(1) DPWR DGND + PREB CLRB CLKB Y YB Q1 QB1 + D_L71_2 IO_L MNTYMXDLY={MNTYMXDLY} X1 Q1 PREB PRE CLRB CLR CLKB CLK_BUF Q DPWR DGND L71SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 QB1 PREB PRE CLRB CLR CLKB CLK_BUF QBAR DPWR DGND L71SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt L71SUB IN P PB C CB CLKB CLK OUT DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 or(2) DPWR DGND + P C PC + D0_GATE IO_L U1 anda(3,2) DPWR DGND + PB CB IN PC CLK IN OUT1 OUT2 + D0_GATE IO_L U2 and(3) DPWR DGND + PC CLKB IN OUT3 + D_L71_3 IO_L MNTYMXDLY={MNTYMXDLY} U3 or(3) DPWR DGND + OUT1 OUT2 OUT3 OUT + D_L71_4 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L71_1 ugff ( + twghmn=200ns twpclmn=100ns + ) .model D_L71_2 ugff ( + twghmn=200ns twpclmn=100ns + ) .model D_L71_3 ugate ( + tphlty=1ps tphlmx=50ns + ) .model D_L71_4 ugate ( + tplhmn=10ns tplhty=35ns + tplhmx=75ns tphlmn=10ns + tphlty=60ns tphlmx=150ns + ) *------------------------------------------------------------------------- * 7472 And Gated J-K Master-Slave Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/11/89 Update interface and model names .subckt 7472 PREBAR CLRBAR CLK J1 J2 J3 K1 K2 K3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + PREBAR CLRBAR PREB CLRB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 buf DPWR DGND + CLK CLK_BUF + D_72_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 anda(3,2) DPWR DGND + J1 J2 J3 K1 K2 K3 J K + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U4 inva(3) DPWR DGND + J K CLK_BUF JB KB CLKB + D0_GATE IO_STD UF1 srff(1) DPWR DGND + PREB CLRB CLK_BUF W1 W2 Y YB + D_72_2 IO_STD MNTYMXDLY={MNTYMXDLY} UF2 srff(1) DPWR DGND + PREB CLRB CLKB Y YB Q1 QB1 + D_72_3 IO_STD MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J K QBD J KB $D_HI W1 + D_72_4 IO_STD U6 ao(3,2) DPWR DGND + J K QD JB K $D_HI W2 + D_72_4 IO_STD U7 bufa(4) DPWR DGND + Q1 Q1 QB1 QB1 Q QD QBAR QBD + D_72_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_72_1 ugate ( + tplhty=6ns tplhmx=6ns + ) .model D_72_2 ugff ( + twghmn=20ns twpclmn=25ns + ) .model D_72_3 ugff ( + twghmn=47ns twpclmn=25ns + tppcqhlty=19ns tppcqhlmx=34ns + tppcqlhty=10ns tppcqlhmx=19ns + tpgqlhty=10ns tpgqlhmx=19ns + tpgqhlty=19ns tpgqhlmx=34ns + ) .model D_72_4 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *--------- * 74H72 And Gated J-K Master-Slave Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/11/89 Update interface and model names .subckt 74H72 PREBAR CLRBAR CLK J1 J2 J3 K1 K2 K3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + PREBAR CLRBAR PREB CLRB + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 buf DPWR DGND + CLK CLK_BUF + D_H72_1 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 anda(3,2) DPWR DGND + J1 J2 J3 K1 K2 K3 J K + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U4 inva(3) DPWR DGND + J K CLK_BUF JB KB CLKB + D0_GATE IO_H UF1 srff(1) DPWR DGND + PREB CLRB CLK_BUF W1 W2 Y YB + D_H72_2 IO_H MNTYMXDLY={MNTYMXDLY} UF2 srff(1) DPWR DGND + PREB CLRB CLKB Y YB Q1 QB1 + D_H72_3 IO_H MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J K QBD J KB $D_HI W1 + D_H72_4 IO_H U6 ao(3,2) DPWR DGND + J K QD JB K $D_HI W2 + D_H72_4 IO_H U7 bufa(4) DPWR DGND + Q1 Q1 QB1 QB1 Q QD QBAR QBD + D_H72_4 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H72_1 ugate ( + tplhty=3ns tplhmx=3ns + ) .model D_H72_2 ugff ( + twghmn=12ns twpclmn=16ns + ) .model D_H72_3 ugff ( + twghmn=28ns twpclmn=16ns + tppcqhlty=3ns tppcqhlmx=10ns + tppcqlhty=9ns tppcqlhmx=21ns + tpgqlhty=11ns tpgqlhmx=18ns + tpgqhlty=19ns tpgqhlmx=24ns + ) .model D_H72_4 ugate ( + tphlty=3ns tphlmx=3ns + tplhty=3ns tplhmx=3ns + ) *--------- * 54L72 And Gated J-K Master-Slave Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/11/89 Update interface and model names .subckt 54L72 PREBAR CLRBAR CLK J1 J2 J3 K1 K2 K3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + PREBAR CLRBAR PREB CLRB + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U2 anda(3,2) DPWR DGND + J1 J2 J3 K1 K2 K3 J K + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U3 inva(3) DPWR DGND + CLK_BUF J K CLKB JB KB + D0_GATE IO_L U4 buf DPWR DGND + CLK CLK_BUF + D_L72_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UF1 srff(1) DPWR DGND + PREB CLRB CLK_BUF W1 W2 Y YB + D_L72_1 IO_L MNTYMXDLY={MNTYMXDLY} UF2 srff(1) DPWR DGND + PREB CLRB CLKB Y YB Q1 QB1 + D_L72_2 IO_L MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J K QBD J KB $D_HI W1 + D_L72_4 IO_H U6 ao(3,2) DPWR DGND + J K QD JB K $D_HI W2 + D_L72_4 IO_H U7 bufa(4) DPWR DGND + Q1 Q1 QB1 QB1 Q QD QBAR QBD + D_L72_4 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L72_1 ugff ( + twghmn=200ns twpclmn=100ns + ) .model D_L72_2 ugff ( + twghmn=200ns twpclmn=100ns + tppcqhlty=40ns tppcqhlmx=180ns + tppcqlhty=15ns tppcqlhmx=55ns + tpgqlhty=15ns tpgqlhmx=55ns + tpgqhlty=40ns tpgqhlmx=130ns + ) .model D_L72_3 ugate ( + tplhty=20ns tplhmx=20ns + ) .model D_L72_4 ugate ( + tplhmn=10ns tplhty=20ns + tplhmx=20ns tphlmn=10ns + tphlty=20ns tphlmx=20ns + ) *------------------------------------------------------------------------- * 7473 Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7473 CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + CLRBAR J K CLRBAR_BUF J_BUF K_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2BUF buf DPWR DGND + CLK CLK_BUF + D_73_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + CLK_BUF J_BUF K_BUF CLKBAR JB KB + D0_GATE IO_STD U2A ao(3,2) DPWR DGND + J_BUF QBAR_BUFD K_BUF J_BUF KB $D_HI W1 + D_73_3 IO_STD MNTYMXDLY={MNTYMXDLY} U2B ao(3,2) DPWR DGND + J_BUF K_BUF Q_BUFD $D_HI JB K_BUF W2 + D_73_3 IO_STD MNTYMXDLY={MNTYMXDLY} U3 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLK_BUF W1 W2 Y YB + D_73_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLKBAR Y YB QBUF QBAR_BUF + D_73_2 IO_STD MNTYMXDLY={MNTYMXDLY} UOBUF bufa(2) DPWR DGND + QBUF QBAR_BUF Q QBAR + D_73_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UBUF bufa(2) DPWR DGND + QBUF QBAR_BUF Q_BUFD QBAR_BUFD + D_73_3 IO_STD MNTYMXDLY={MNTYMXDLY} .ends .model D_73_1 ugff ( + twghmx=14ns twghty=14ns + twpclmx=25ns twpclty=25ns + ) .model D_73_2 ugff ( + tppcqlhty=10ns tppcqlhmx=19ns + tppcqhlty=19ns tppcqhlmx=34ns + tpgqlhty=10ns tpgqlhmx=19ns + tpgqhlty=19ns tpgqhlmx=34ns + twghmx=47ns twghty=47ns + twpclmx=25ns twpclty=25ns + ) .model D_73_3 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) .model D_73_4 ugate ( + tplhmn=6ns tplhmx=6ns + ) *--------- * 74H73 Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74H73 CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + CLRBAR J K CLRBAR_BUF J_BUF K_BUF + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2BUF buf DPWR DGND + CLK CLK_BUF + D_H73_4 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + CLK_BUF J_BUF K_BUF CLKBAR JB KB + D0_GATE IO_H U2A ao(3,2) DPWR DGND + J_BUF QBAR_BUFD K_BUF J_BUF KB $D_HI W1 + D_H73_3 IO_H MNTYMXDLY={MNTYMXDLY} U2B ao(3,2) DPWR DGND + J_BUF QBUFD K_BUF JB K_BUF $D_HI W2 + D_H73_3 IO_H MNTYMXDLY={MNTYMXDLY} U3 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLK_BUF W1 W2 Y YB + D_H73_1 IO_H MNTYMXDLY={MNTYMXDLY} U4 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLKBAR Y YB QBUF QBAR_BUF + D_H73_2 IO_H MNTYMXDLY={MNTYMXDLY} UOBUF bufa(2) DPWR DGND + QBUF QBAR_BUF Q QBAR + D_H73_3 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UBUF bufa(2) DPWR DGND + QBUF QBAR_BUF QBUFD QBAR_BUFD + D_73_3 IO_H MNTYMXDLY={MNTYMXDLY} .ends .model D_H73_1 ugff ( + twghmx=6ns twghty=6ns + twpclmx=16ns twpclty=16ns + ) .model D_H73_2 ugff ( + tppcqlhty=2ns tppcqlhmx=9ns + tppcqhlty=8ns tppcqhlmx=20ns + tpgqlhty=10ns tpgqlhmx=17ns + tpgqhlty=18ns tpgqhlmx=23ns + twghmx=28ns twghty=28ns + twpclmx=16ns twpclty=16ns + ) .model D_H73_3 ugate ( + tplhty=4ns tplhmx=4ns + tphlty=4ns tphlmx=4ns + ) .model D_H73_4 ugate ( + tplhmn=6ns tplhmx=6ns + ) *--------- * 74HC73 Dual J-K Flip-Flops with Clear * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/28/89 Update interface and model names .subckt 74HC73 CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + $D_HI CLRBAR CLK J K Q QBAR + D_HC73 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC73 ueff ( + tppcqlhty=16ns tppcqlhmx=39ns + tppcqhlty=16ns tppcqhlmx=39ns + tpclkqlhty=13ns tpclkqlhmx=32ns + tpclkqhlty=13ns tpclkqhlmx=32ns + twclkhmx=20ns twclkhty=20ns + twclklmx=20ns twclklty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=30ns tsudclkty=30ns + tsupcclkhmx=30ns tsupcclkhty=30ns + ) *--------- * 74LS73A Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74LS73A CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + $D_HI CLRBAR CLK J K Q QBAR + D_LS73A IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS73A ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=20ns tsudclkty=20ns + ) *------------------------------------------------------------------------- * 7474 Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7474 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_74 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_74 ueff ( + twpclmn=30ns twclklmn=37ns + twclkhmn=30ns tsudclkmn=20ns + thdclkmn=5ns tppcqlhmx=25ns + tppcqhlmx=40ns tpclkqlhty=14ns + tpclkqlhmx=25ns tpclkqhlty=20ns + tpclkqhlmx=40ns + ) *--------- * 74AC74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The FACT Data Book, 1987, Fairchild * cv 06/22/90 Created from LS .subckt 74AC74 CD1BAR D1 CP1 SD1BAR Q1 Q1BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF11 dff(1) DPWR DGND + SD1BAR CD1BAR CP1 D1 Q1 Q1BAR + D_AC74 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC74 ueff ( + twpclmn=5ns twclklmn=5ns + twclkhmn=5ns tsudclkmn=3ns + tsupcclkhmn=0ns thdclkmn=0ns + tppcqlhmn=1ns tppcqlhty=6ns + tppcqlhmx=10ns tppcqhlmn=1ns + tppcqhlty=8ns tppcqhlmx=10.5ns + tpclkqlhmn=1ns tpclkqlhty=6ns + tpclkqlhmx=10.5ns tpclkqhlmn=1ns + tpclkqhlty=6ns tpclkqhlmx=10.5ns + ) *--------- * 74ACT74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The FACT Data Book, 1987, Fairchild * cv 06/22/90 Created from LS .subckt 74ACT74 CD1BAR D1 CP1 SD1BAR Q1 Q1BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF11 dff(1) DPWR DGND + SD1BAR CD1BAR CP1 D1 Q1 Q1BAR + D_ACT74 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT74 ueff ( + twpclmn=6ns twclklmn=6ns + twclkhmn=6ns tsudclkmn=3.5ns + tsupcclkhmn=0ns thdclkmn=1ns + tppcqlhmn=1ns tppcqlhty=5.5ns + tppcqlhmx=10.5ns tppcqhlmn=1ns + tppcqhlty=6ns tppcqhlmx=11.5ns + tpclkqlhmn=1ns tpclkqlhty=7.5ns + tpclkqlhmx=13ns tpclkqhlmn=1ns + tpclkqhlty=6ns tpclkqhlmx=11.5ns + ) *--------- * 74ALS74A Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The ALS/AS Data Book, 1986, TI * tdn 06/28/89 Update interface and model names .subckt 74ALS74A 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_ALS74A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS74A ueff ( + twpclmn=15ns twclklmn=14.5ns + twclkhmn=14.5ns tsudclkmn=15ns + tsupcclkhmn=10ns thdclkmn=0ns + tppcqlhmn=3ns tppcqlhmx=13ns + tppcqhlmn=5ns tppcqhlmx=15ns + tpclkqlhmn=5ns tpclkqlhmx=16ns + tpclkqhlmn=5ns tpclkqhlmx=18ns + ) *--------- * 74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The ALS/AS Data Book, 1986, TI * tdn 06/28/89 Update interface and model names .subckt 74AS74 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_AS74 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS74 ueff ( + twpclmn=4ns twclklmn=5.5ns + twclkhmn=4ns tsudclkmn=4.5ns + tsupcclkhmn=2ns tppcqlhmn=3.00ns + tppcqlhmx=7.5ns tppcqhlmn=3.50ns + tppcqhlmx=10.5ns tpclkqlhmn=3.5ns + tpclkqlhmx=8ns tpclkqhlmn=4.5ns + tpclkqhlmx=9ns + ) *--------- * 74F74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The F Logic Data Book, 1987, TI * tdn 06/28/89 Update interface and model names .subckt 74F74 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_F74 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F74 ueff ( + twpclmn=4ns twclklmn=5ns + twclkhmn=4ns tsudclkmn=3ns + tsupcclkhmn=2ns thdclkmn=1ns + tppcqlhmn=2.40ns tppcqlhmx=7.1ns + tppcqhlmn=2.70ns tppcqhlmx=10.5ns + tpclkqlhmn=3.00ns tpclkqlhmx=7.8ns + tpclkqhlmn=3.6ns tpclkqhlmx=9.2ns + ) *--------- * 74H74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74H74 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + 1D 1DBUF + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + 1DBUF 1DBAR + D_H74_2 IO_H MNTYMXDLY={MNTYMXDLY} U2 nxor DPWR DGND + 1DBUF 1DBAR T1 + D0_GATE IO_H U3 and(2) DPWR DGND + T1 X T2 + D0_GATE IO_H U4 xor DPWR DGND + 1DBUF T2 DOUT + D0_GATE IO_H UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK DOUT 1Q 1QBAR + D_H74_1 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H74_2 ugate ( + tplhmn=1ns tphlmn=6ns + ) .model D_H74_1 ueff ( + twpclmn=25ns twclklmn=13.5ns + twclkhmn=15ns tsudclkmn=9ns + thdclkmn=5ns tppcqlhmx=20ns + tppcqhlmx=30ns tpclkqlhty=8.5ns + tpclkqlhmx=15ns tpclkqhlty=13.0ns + tpclkqhlmx=20ns + ) *--------- * 74HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/28/89 Update interface and model names .subckt 74HC74 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_HC74 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC74 ueff ( + twpclmn=25ns twclklmn=20ns + twclkhmn=20ns tsudclkmn=25ns + tsupcclkhmn=6ns thdclkmn=0ns + tppcqlhty=20ns tppcqlhmx=58ns + tppcqhlty=20ns tppcqhlmx=58ns + tpclkqlhty=20ns tpclkqlhmx=44ns + tpclkqhlty=20ns tpclkqhlmx=44ns + ) *--------- * 74HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/28/89 Update interface and model names .subckt 74HCT74 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_HCT74 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HCT74 ueff ( + twpclmn=20ns twclklmn=23ns + twclkhmn=23ns tsudclkmn=15ns + tsupcclkhmn=0ns thdclkmn=0ns + tppcqlhty=21ns tppcqlhmx=44ns + tppcqhlty=21ns tppcqhlmx=44ns + tpclkqlhty=20ns tpclkqlhmx=35ns + tpclkqhlty=20ns tpclkqhlmx=35ns + ) *--------- * 74L74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74L74 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_L74 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L74 ueff ( + twpclmn=100ns twclklmn=200ns + twclkhmn=200ns tsudclkmn=50ns + thdclkmn=15ns tppcqlhty=50ns + tppcqlhmx=75ns tppcqhlty=80ns + tppcqhlmx=150ns tpclkqlhmn=15ns + tpclkqlhty=65ns tpclkqlhmx=100ns + tpclkqhlmn=15ns tpclkqhlty=65ns + tpclkqhlmx=150ns + ) *--------- * 74LS74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74LS74A 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_LS74 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS74 ueff ( + twpclmn=25ns twclkhmn=25ns + tsudclkmn=20ns thdclkmn=5ns + tppcqlhmx=25ns tppcqlhty=13ns + tppcqhlmx=40ns tppcqhlty=25ns + tpclkqlhty=13ns tpclkqlhmx=25ns + tpclkqhlty=25ns tpclkqhlmx=40ns + ) *--------- * 74S74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74S74 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_S74 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S74 ueff ( + twpclmn=7ns twclklmn=7.3ns + twclkhmn=6ns tsudclkmn=3ns + thdclkmn=2ns tppcqlhty=4ns + tppcqlhmx=6ns tppcqhlty=9ns + tppcqhlmx=13.5ns tpclkqlhty=6ns + tpclkqlhmx=9ns tpclkqhlty=6ns + tpclkqhlmx=9ns + ) *------------------------------------------------------------------------- * 7475 4-bit bistable latches (dual 2-bit common clock) * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7475 1D 2D C 1Q 1QBAR 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + 1D 2D C 1D_BUF 2D_BUF C_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U12 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF 1Q 2Q $D_NC $D_NC + D_75_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12B dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF $D_NC $D_NC 1QBAR 2QBAR + D_75_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_75_1 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=16ns + tpdqlhmx=30ns tpdqhlty=14ns + tpdqhlmx=25ns + ) .model D_75_2 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=24ns + tpdqlhmx=40ns tpdqhlty=7ns + tpdqhlmx=15ns + ) *--------- * 74HC75 4-bit bistable latches (dual 2-bit common clock) * * The High-Speed CMOS Logic Data Book, 1988, TI * muw 12/05/89 Created .subckt 74HC75 1D 2D C 1Q 1QBAR 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + 1D 2D C 1D_BUF 2D_BUF C_BUF + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U12 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF 1Q 2Q $D_NC $D_NC + D_HC75_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC75_1 ugff ( + twghmx=100ns tsudgmx=125ns + thdgmx=5ns tpgqlhty=44ns + tpgqlhmx=165ns tpgqhlty=44ns + tpgqhlmx=165ns tpdqlhty=40ns + tpdqlhmx=150ns tpdqhlty=40ns + tpdqhlmx=150ns + ) *--------- * 74L75 4-bit bistable latches (dual 2-bit common clock) * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74L75 1D 2D C 1Q 1QBAR 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + 1D 2D C 1D_BUF 2D_BUF C_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U12 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF 1Q 2Q $D_NC $D_NC + D_L75_1 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12B dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF $D_NC $D_NC 1QBAR 2QBAR + D_L75_2 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L75_1 ugff ( + twghmx=100ns tsudgmx=40ns + thdgmx=10ns tpgqlhty=32ns + tpgqlhmx=60ns tpgqhlty=14ns + tpgqhlmx=30ns tpdqlhty=32ns + tpdqlhmx=60ns tpdqhlty=28ns + tpdqhlmx=50ns + ) .model D_L75_2 ugff ( + twghmx=100ns tsudgmx=40ns + thdgmx=10ns tpgqlhty=32ns + tpgqlhmx=60ns tpgqhlty=14ns + tpgqhlmx=30ns tpdqlhty=48ns + tpdqlhmx=80ns tpdqhlty=14ns + tpdqhlmx=30ns + ) *--------- * 74LS75 4-bit bistable latches (dual 2-bit common clock) * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74LS75 1D 2D C 1Q 1QBAR 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + 1D 2D C 1D_BUF 2D_BUF C_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U12 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF 1Q 2Q $D_NC $D_NC + D_LS75_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12B dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF $D_NC $D_NC 1QBAR 2QBAR + D_LS75_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS75_1 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=15ns + tpgqlhmx=27ns tpgqhlty=14ns + tpgqhlmx=25ns tpdqlhty=15ns + tpdqlhmx=27ns tpdqhlty=9ns + tpdqhlmx=17ns + ) .model D_LS75_2 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=12ns + tpdqlhmx=20ns tpdqhlty=7ns + tpdqhlmx=15ns + ) *------------------------------------------------------------------------- * 7476 Dual J-K Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * .subckt 7476 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --NOTE-- * The standard Flip-Flops are pulse triggered * UIBUF bufa(4) DPWR DGND + PREBAR CLRBAR J K PREBAR_BUF CLRBAR_BUF J_BUF K_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 srff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLK_BUF W1 W2 Y YB + D_76_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 srff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR Y YB Q2 QB2 + D_76_2 IO_STD MNTYMXDLY={MNTYMXDLY} U2BUF buf DPWR DGND + CLK CLK_BUF + D_76_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inva(3) DPWR DGND + CLK_BUF J_BUF K_BUF CLKBAR JB KB + D0_GATE IO_STD U4 ao(3,2) DPWR DGND + J_BUF K_BUF QB2D J_BUF KB $D_HI W1 + D_76_3 IO_STD MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J_BUF K_BUF Q2D JB K_BUF $D_HI W2 + D_76_3 IO_STD MNTYMXDLY={MNTYMXDLY} UBUF bufa(2) DPWR DGND + Q2 QB2 Q2D QB2D + D_76_3 IO_STD MNTYMXDLY={MNTYMXDLY} UOBUF bufa(2) DPWR DGND + Q2 QB2 Q QBAR + D_76_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_76_1 ugff ( + twghmx=14ns twghty=14ns + twpclmx=25ns twpclty=25ns + ) .model D_76_2 ugff ( + tppcqlhty=10ns tppcqlhmx=19ns + tppcqhlty=19ns tppcqhlmx=34ns + tpgqlhty=10ns tpgqlhmx=19ns + tpgqhlty=19ns tpgqhlmx=34ns + twghmx=47ns twghty=47ns + twpclmx=25ns twpclty=25ns + ) .model D_76_3 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) .model D_76_4 ugate ( + tplhmn=6ns tplhmx=6ns + ) *--------- * 74H76 Dual J_K Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74H76 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 *--NOTE-- * These Flip-Flops are pulse triggered UIBUF bufa(4) DPWR DGND + PREBAR CLRBAR J K PREBAR_BUF CLRBAR_BUF J_BUF K_BUF + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U1 srff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLK_BUF W1 W2 Y YB + D_H76_1 IO_H MNTYMXDLY={MNTYMXDLY} U2 srff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR Y YB Q2 QB2 + D_H76_2 IO_H MNTYMXDLY={MNTYMXDLY} U2BUF buf DPWR DGND + CLK CLK_BUF + D_H76_4 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inva(3) DPWR DGND + CLK_BUF J_BUF K_BUF CLKBAR JB KB + D0_GATE IO_H U4 ao(3,2) DPWR DGND + J_BUF K_BUF QB2D J_BUF KB $D_HI W1 + D_H76_3 IO_H MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J_BUF K_BUF Q2D JB K_BUF $D_HI W2 + D_H76_3 IO_H MNTYMXDLY={MNTYMXDLY} UOBUF bufa(2) DPWR DGND + Q2 QB2 Q QBAR + D_H76_3 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UBUF bufa(2) DPWR DGND + Q2 QB2 Q2D QB2D + D_H76_3 IO_H MNTYMXDLY={MNTYMXDLY} .ends .model D_H76_1 ugff ( + twghmx=8ns twghty=8ns + twpclmx=16ns twpclty=16ns + ) .model D_H76_2 ugff ( + tppcqlhty=2ns tppcqlhmx=9ns + tppcqhlty=8ns tppcqhlmx=20ns + tpgqlhty=10ns tpgqlhmx=17ns + tpgqhlty=18ns tpgqhlmx=23ns + twghmx=28ns twghty=28ns + twpclmx=16ns twpclty=16ns + ) .model D_H76_3 ugate ( + tplhty=4ns tphlmx=4ns + tphlty=4ns tphlmx=4ns + ) .model D_H76_4 ugate ( + tplhmn=4ns tplhmx=4ns + ) *--------- * 74HC76 Dual J-K Flip-Flops with Preset and Clear * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/28/89 Update interface and model names .subckt 74HC76 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 *--NOTE-- * These Flip-Flops are negative-edge-triggered U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLK J K Q QBAR + D_HC76 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC76 ueff ( + tppcqlhty=16ns tppcqlhmx=39ns + tppcqhlty=16ns tppcqhlmx=39ns + tpclkqlhty=19ns tpclkqlhmx=36ns + tpclkqhlty=19ns tpclkqhlmx=36ns + twclkhmn=20ns twclklmn=20ns + twpclmn=25ns tsudclkmn=38ns + tsupcclkhmn=25ns + ) *--------- * 74LS76A Dual J-K Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74LS76A CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 *--NOTE-- * These Flip-Flops are negative-edge-triggered U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLK J K Q QBAR + D_LS76 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS76 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmn=20ns twpclmn=20ns + tsudclkmn=20ns + ) *------------------------------------------------------------------------- * 7477 4-bit bistable latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7477 1D 2D C 1Q 2Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * There are actually 2 2-bit latches(per 1 control) in the real IC. The model * here for the IC contains only 1 2-bit latches. If 4-bit latches is needed, * please use the SUBCKT twice. UIBUF buf DPWR DGND + C C_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D 2D 1Q 2Q $D_NC $D_NC + D_77 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_77 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=16ns + tpdqlhmx=30ns tpdqhlty=14ns + tpdqhlmx=25ns + ) *--------- * 74L77 4-bit bistable latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74L77 1D 2D C 1Q 2Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + C C_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D 2D 1Q 2Q $D_NC $D_NC + D_L77 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L77 ugff ( + twghmx=100ns tsudgmx=40ns + thdgmx=10ns tpgqlhty=32ns + tpgqlhmx=60ns tpgqhlty=14ns + tpgqhlmx=30ns tpdqlhty=32ns + tpdqlhmx=60ns tpdqhlty=28ns + tpdqhlmx=50ns + ) *--------- * 74LS77 4-bit bistable latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74LS77 1D 2D C 1Q 2Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + C C_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D 2D 1Q 2Q $D_NC $D_NC + D_LS77 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS77 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=10ns + tpgqlhmx=18ns tpgqhlty=10ns + tpgqhlmx=18ns tpdqlhty=11ns + tpdqlhmx=19ns tpdqhlty=9ns + tpdqhlmx=17ns + ) *------------------------------------------------------------------------- * 74H78 Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74H78 CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + CLRBAR CLRBAR_BUF + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2BUF buf DPWR DGND + CLK CLK_BUF + D_H78_4 IO_H IO_LEVEL={IO_LEVEL} X1 CLK_BUF CLRBAR_BUF 1PREBAR 1J 1K 1Q 1QBAR DPWR DGND 74H78_SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 CLK_BUF CLRBAR_BUF 2PREBAR 2J 2K 2Q 2QBAR DPWR DGND 74H78_SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 74H78_SUB CLK CLRBAR PREBAR J K Q QBAR DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 srff(1) DPWR DGND + PREBAR CLRBAR CLK W1 W2 Y YB + D_H78_1 IO_H MNTYMXDLY={MNTYMXDLY} U2 srff(1) DPWR DGND + PREBAR CLRBAR CLKBAR Y YB Q1 QB1 + D_H78_2 IO_H MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + CLK J K CLKBAR JB KB + D0_GATE IO_H UB bufa(2) DPWR DGND + Q1 QB1 QD QBD + D_H78_3 IO_H MNTYMXDLY={MNTYMXDLY} UOB bufa(2) DPWR DGND + Q1 QB1 Q QBAR + D_H78_5 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + J QBD K J KB $D_HI W1 + D_H78_3 IO_H MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + JB K $D_HI J K QD W2 + D_H78_3 IO_H MNTYMXDLY={MNTYMXDLY} .ends .model D_H78_1 ugff ( + twghmx=12ns twghty=12ns + twpclmx=16ns twpclty=16ns + ) .model D_H78_2 ugff ( + tpgqlhty=8ns tpgqlhmx=8ns + tpgqhlty=10ns tpgqhlmx=3ns + twghmx=28ns twghty=28ns + twpclmx=16ns twpclty=16ns + ) .model D_H78_3 ugate ( + tphlty=3ns tplhmx=3ns + tplhty=3ns tphlmx=3ns + ) .model D_H78_4 ugate ( + tplhmn=3ns tplhmx=3ns + ) .model D_H78_5 ugate ( + tplhty=6ns tplhmx=13ns + tphlty=12ns tphlmx=24ns + ) *--------- * 74HC78 Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/28/89 Update interface and model names .subckt 74HC78 CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + CLK CLRBAR 1PREBAR 2PREBAR CLK_BUF CLRBAR_BUF 1PREB 2PREB + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + 1PREB CLRBAR_BUF CLK_BUF 1J 1K 1Q 1QBAR + D_HC78 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + 2PREB CLRBAR_BUF CLK_BUF 2J 2K 2Q 2QBAR + D_HC78 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC78 ueff ( + tppcqlhty=16ns tppcqlhmx=39ns + tppcqhlty=16ns tppcqhlmx=39ns + tpCLKqlhty=13ns tpCLKqlhmx=32ns + tpCLKqhlty=13ns tpCLKqlhmx=32ns + twclkhmx=20ns twclkhty=20ns + twclklmx=20ns twclklty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=30ns tsudclkty=30ns + tsupcclkhmx=30ns tsupcclkhty=30ns + ) *--------- * 74LS78A Dual J-K Flip-Flops with Preset, Common Clear and Common Clock * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 74LS78A CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + CLK CLRBAR 1PREBAR 2PREBAR CLK_BUF CLRBAR_BUF 1PREB 2PREB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + 1PREB CLRBAR_BUF CLK_BUF 1J 1K 1Q 1QBAR + D_LS78 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + 2PREB CLRBAR_BUF CLK_BUF 2J 2K 2Q 2QBAR + D_LS78 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS78 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=20ns tsudclkty=20ns + ) *------------------------------------------------------------------------- * 7482 2-bit Binary Full Adders * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 7482 C0 A1 B1 A2 B2 SUM1 SUM2 C2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + C0 A1 B1 CC0 AA1 BB1 + D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + A2 B2 AA2BAR1 BB2BAR1 + D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 ao(3,4) DPWR DGND + CC0 C1 $D_HI + AA1 C1 $D_HI + BB1 C1 $D_HI + CC0 AA1 BB1 + SUM1 + D_82_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 aoi(2,3) DPWR DGND + CC0 AA1 CC0 BB1 BB1 AA1 C1 + D_82_4 IO_STD MNTYMXDLY={MNTYMXDLY} U5 aoi(3,4) DPWR DGND + C1 C2D $D_HI + AA2BAR1 C2D $D_HI + BB2BAR1 C2D $D_HI + C1 AA2BAR1 BB2BAR1 + SUM2 + D_82_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(2,3) DPWR DGND + C1 AA2BAR1 C1 BB2BAR1 AA2BAR1 BB2BAR1 C2D + D0_GATE IO_STD U7 buf DPWR DGND + C2D C2 + D_82_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_82_1 ugate ( + tplhmx=34ns + tphlmx=40ns + ) .model D_82_2 ugate ( + tplhmx=40ns + tphlmx=35ns + ) .model D_82_3 ugate ( + tplhty=12ns tplhmx=19ns + tphlty=17ns tphlmx=27ns + ) .model D_82_4 ugate ( + tplhmn=3ns tplhmx=3ns + tphlmn=2ns tphlmx=2ns + ) *------------------------------------------------------------------------- * 7483A 4-bit Binary Full Adders with Fast Carry * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 7483A C0 A1 A2 A3 A4 B1 B2 B3 B4 C4 SUM1 SUM2 SUM3 SUM4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(9) DPWR DGND + A1 B1 A2 B2 A3 B3 A4 B4 C0 + A1B B1B A2B B2B A3B B3B A4B B4B C0B + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} US1 nanda(2,4) DPWR DGND + A1B B1B + A2B B2B + A3B B3B + A4B B4B + BB1 BB2 BB3 BB4 + D0_GATE IO_STD US2 nora(2,4) DPWR DGND + AA1 BBB1 + AA2 BBB2 + AA3 BBB3 + AA4 BBB4 + SUM1AB SUM2AB SUM3AB SUM4AB + D0_GATE IO_STD US3 ora(2,4) DPWR DGND + AA1 BBB1 + AA2 BBB2 + AA3 BBB3 + AA4 BBB4 + SUM1ABB SUM2ABB SUM3ABB SUM4ABB + D0_GATE IO_STD US4 anda(5,14) DPWR DGND + A1B B1B $D_HI $D_HI $D_HI + A2B B2B $D_HI $D_HI $D_HI + A3B B3B $D_HI $D_HI $D_HI + A4B B4B $D_HI $D_HI $D_HI + AA3 BB4 $D_HI $D_HI $D_HI + AA2 BB4 BB3 $D_HI $D_HI + AA1 BB4 BB3 BB2 $D_HI + BB4 BB3 BB2 BB1 C0BAR + AA2 BB3 $D_HI $D_HI $D_HI + AA1 BB3 BB2 $D_HI $D_HI + BB3 BB2 BB1 C0BAR $D_HI + AA1 BB2 $D_HI $D_HI $D_HI + BB2 BB1 C0BAR $D_HI $D_HI + BB1 C0BAR $D_HI $D_HI $D_HI + BBB1 BBB2 BBB3 BBB4 C41 C42 C43 + C44 C31 C32 C33 C21 C22 C11 + D0_GATE IO_STD US5 nora(4,7) DPWR DGND + A1B B1B $D_LO $D_LO + A2B B2B $D_LO $D_LO + A3B B3B $D_LO $D_LO + A4B B4B $D_LO $D_LO + AA3 C31 C32 C33 + AA2 C21 C22 $D_LO + AA1 C11 $D_LO $D_LO + AA1 AA2 AA3 AA4 C3 C2 C1 + D0_GATE IO_STD UV inv DPWR DGND + C0B C0BAR + D0_GATE IO_STD UC4 nor(5) DPWR DGND + AA4 C41 C42 C43 C44 C4 + D_83A_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3O ora(4,3) DPWR DGND + AA3 C31 C32 C33 + AA2 C21 C22 $D_LO + AA1 C11 $D_LO $D_LO + C3B C2B C1B + D0_GATE IO_STD U40 ao(2,2) DPWR DGND + SUM4AB C3B SUM4ABB C3 S4 + D_83A_2 IO_STD MNTYMXDLY={MNTYMXDLY} U30 ao(2,2) DPWR DGND + SUM3AB C2B SUM3ABB C2 S3 + D_83A_2 IO_STD MNTYMXDLY={MNTYMXDLY} U20 ao(2,2) DPWR DGND + SUM2AB C1B SUM2ABB C1 S2 + D_83A_2 IO_STD MNTYMXDLY={MNTYMXDLY} U10 ao(2,2) DPWR DGND + SUM1AB C0BAR SUM1ABB C0B S1 + D_83A_2 IO_STD MNTYMXDLY={MNTYMXDLY} UO1 buf3a(4) DPWR DGND + S1 S2 S3 S4 EN1 SUM1 SUM2 SUM3 SUM4 + D_83A_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UO2 buf3a(4) DPWR DGND + S1 S2 S3 S4 EN2 SUM1 SUM2 SUM3 SUM4 + D_83A_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UX1 buf DPWR DGND + C0BAR C0E + D_83A_5 IO_STD MNTYMXDLY={MNTYMXDLY} UX2 nxor DPWR DGND + C0BAR C0E EN1 + D0_GATE IO_STD UX3 xor DPWR DGND + C0BAR C0E EN2 + D0_GATE IO_STD .ends .model D_83A_1 ugate ( + tplhty=9ns tplhmx=14ns + tphlty=11ns tphlmx=16ns + ) .model D_83A_2 ugate ( + tplhmn=.1ns tphlmn=.1ns + ) .model D_83A_3 utgate ( + tplhty=15.9ns tplhmx=23.9ns + tphlty=15.9ns tphlmx=23.9ns + ) .model D_83A_4 utgate ( + tplhty=13.9ns tplhmx=20.9ns + tphlty=11.9ns tphlmx=20.9ns + ) .model D_83A_5 ugate ( + tphlmn=21ns tplhmn=21ns + ) *--------- * 74LS83A 4-bit Binary Full Adders with Fast Carry * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74LS83A C0 A1 A2 A3 A4 B1 B2 B3 B4 C4 SUM1 SUM2 SUM3 SUM4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(9) DPWR DGND + A1 A2 A3 A4 B1 B2 B3 B4 C0 + A1B A2B A3B A4B B1B B2B B3B B4B C0D + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1S nanda(2,4) DPWR DGND + A1B B1B + A2B B2B + A3B B3B + A4B B4B + BB1 BB2 BB3 BB4 + D0_GATE IO_LS U2S nora(2,8) DPWR DGND + A1B B1B + A2B B2B + A3B B3B + A4B B4B + AA1 BBB1 + AA2 BBB2 + AA3 BBB3 + AA4 BBB4 + AA1 AA2 AA3 AA4 SUM1AB SUM2AB SUM3AB SUM4AB + D0_GATE IO_LS U3S inva(4) DPWR DGND + BB1 BB2 BB3 BB4 BBB1 BBB2 BBB3 BBB4 + D0_GATE IO_LS U4S ora(2,4) DPWR DGND + AA1 BBB1 + AA2 BBB2 + AA3 BBB3 + AA4 BBB4 + SUM1ABB SUM2ABB SUM3ABB SUM4ABB + D0_GATE IO_LS UV inv DPWR DGND + C0D C0B + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UB buf DPWR DGND + C0B C0BC + D_LS83A_1 IO_LS MNTYMXDLY={MNTYMXDLY} UC4A aoi(5,5) DPWR DGND + AA3 BB4 $D_HI $D_HI $D_HI + AA2 BB4 BB3 $D_HI $D_HI + AA1 BB4 BB3 BB2 $D_HI + BB4 BB3 BB2 BB1 C0BC + AA4 $D_HI $D_HI $D_HI $D_HI + C4 + D_LS83A_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3A aoi(4,4) DPWR DGND + AA2 BB3 $D_HI $D_HI + AA1 BB3 BB2 $D_HI + BB3 BB2 BB1 C0B + AA3 $D_HI $D_HI $D_HI + C3 + D0_GATE IO_LS U3B ao(4,4) DPWR DGND + AA2 BB3 $D_HI $D_HI + AA1 BB3 BB2 $D_HI + BB3 BB2 BB1 C0B + AA3 $D_HI $D_HI $D_HI + C3B + D0_GATE IO_LS U2A aoi(3,3) DPWR DGND + AA1 BB2 $D_HI + BB2 BB1 C0B + AA2 $D_HI $D_HI + C2 + D0_GATE IO_LS U2B ao(3,3) DPWR DGND + AA1 BB2 $D_HI + BB2 BB1 C0B + AA2 $D_HI $D_HI + C2B + D0_GATE IO_LS U1A aoi(2,2) DPWR DGND + BB1 C0B AA1 $D_HI C1 + D0_GATE IO_LS U1B ao(2,2) DPWR DGND + BB1 C0B AA1 $D_HI C1B + D0_GATE IO_LS U10 ao(2,2) DPWR DGND + SUM1AB C0B SUM1ABB C0D S1 + D_LS83A_3 IO_LS MNTYMXDLY={MNTYMXDLY} U20 ao(2,2) DPWR DGND + SUM2AB C1B SUM2ABB C1 S2 + D_LS83A_3 IO_LS MNTYMXDLY={MNTYMXDLY} U30 ao(2,2) DPWR DGND + SUM3AB C2B SUM3ABB C2 S3 + D_LS83A_3 IO_LS MNTYMXDLY={MNTYMXDLY} U40 ao(2,2) DPWR DGND + SUM4AB C3B SUM4ABB C3 S4 + D_LS83A_3 IO_LS MNTYMXDLY={MNTYMXDLY} U1O buf3a(4) DPWR DGND + S1 S2 S3 S4 EN1 SUM1 SUM2 SUM3 SUM4 + D_LS83A_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2O buf3a(4) DPWR DGND + S1 S2 S3 S4 EN2 SUM1 SUM2 SUM3 SUM4 + D_LS83A_5 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1X buf DPWR DGND + C0D C0E + D_LS83A_6 IO_LS MNTYMXDLY={MNTYMXDLY} U2X nxor DPWR DGND + C0D C0E EN1 + D0_GATE IO_LS U3X xor DPWR DGND + C0D C0E EN2 + D0_GATE IO_LS .ends .model D_LS83A_1 ugate ( + tplhty=3ns tplhmx=5ns + ) .model D_LS83A_2 ugate ( + tplhty=11ns tplhmx=17ns + tphlty=12ns tphlmx=17ns + ) .model D_LS83A_3 ugate ( + tplhmn=.1ns tphlmn=.1ns + ) .model D_LS83A_4 utgate ( + tplhty=14.9ns tplhmx=23.9ns + tphlty=14.9ns tphlmx=23.9ns + ) .model D_LS83A_5 utgate ( + tplhty=15.9ns tplhmx=23.9ns + tphlty=14.9ns tphlmx=23.9ns + ) .model D_LS83A_6 ugate ( + tphlmn=24ns tplhmn=24ns + ) *------------------------------------------------------------------------- * 7485 4-bit Magnitude Comparators * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 7485 A3 A2 A1 A0 B3 B2 B1 B0 AGBIN AEBIN ALBIN AGBOUT AEBOUT ALBOUT + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * AGBin = A GREATER THAN B * ALBin = A LESS THAN B * AEBin = A EQUALS B * These are outputs from previous stage comparator UIBUF bufa(9) DPWR DGND + A0 A1 A2 A3 B0 B1 B2 B3 AEBin + A0_BUF A1_BUF A2_BUF A3_BUF B0_BUF B1_BUF B2_BUF B3_BUF AEB_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 nanda(2,4) DPWR DGND + A3_BUF B3_BUF + A2_BUF B2_BUF + A1_BUF B1_BUF + A0_BUF B0_BUF + Y13GL Y12GL Y11GL Y10GL + D_85_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 nanda(2,4) DPWR DGND + A3_BUF B3_BUF + A2_BUF B2_BUF + A1_BUF B1_BUF + A0_BUF B0_BUF + Y13E Y12E Y11E Y10E + D0_GATE IO_STD U3GL aoi(2,2) DPWR DGND + A3_BUF Y13GL Y13GL B3_BUF Y23GL + D_85_2 IO_STD MNTYMXDLY={MNTYMXDLY} U2GL aoi(2,2) DPWR DGND + A2_BUF Y12GL Y12GL B2_BUF Y22GL + D_85_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1GL aoi(2,2) DPWR DGND + A1_BUF Y11GL Y11GL B1_BUF Y21GL + D_85_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U0GL aoi(2,2) DPWR DGND + A0_BUF Y10GL Y10GL B0_BUF Y20GL + D_85_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3E aoi(2,2) DPWR DGND + A3_BUF Y13E Y13E B3_BUF Y23E + D_85_3 IO_STD MNTYMXDLY={MNTYMXDLY} U2E aoi(2,2) DPWR DGND + A2_BUF Y12E Y12E B2_BUF Y22E + D_85_3 IO_STD MNTYMXDLY={MNTYMXDLY} U1E aoi(2,2) DPWR DGND + A1_BUF Y11E Y11E B1_BUF Y21E + D_85_3 IO_STD MNTYMXDLY={MNTYMXDLY} U0E aoi(2,2) DPWR DGND + A0_BUF Y10E Y10E B0_BUF Y20E + D_85_3 IO_STD MNTYMXDLY={MNTYMXDLY} U3G aoi(5,6) DPWR DGND + B3_BUF Y13GL $D_HI $D_HI $D_HI + B2_BUF Y12GL Y23GL $D_HI $D_HI + B1_BUF Y11GL Y23GL Y22GL $D_HI + B0_BUF Y10GL Y23GL Y22GL Y21GL + Y23GL Y22GL Y21GL Y20GL ALBin + Y23GL Y22GL Y21GL Y20GL AEB_BUF + AGBout + D_85_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3L aoi(5,6) DPWR DGND + A3_BUF Y13GL $D_HI $D_HI $D_HI + A2_BUF Y12GL Y23GL $D_HI $D_HI + A1_BUF Y11GL Y23GL Y22GL $D_HI + A0_BUF Y10GL Y23GL Y22GL Y21GL + Y23GL Y21GL Y22GL Y20GL AGBin + Y23GL Y22GL Y21GL Y20GL AEB_BUF + ALBout + D_85_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3EO and(5) DPWR DGND + Y23E Y22E AEBin Y21E Y20E AEBout + D_85_5 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_85_1 ugate ( + tplhty=5ns tplhmx=7.5ns + tphlty=5ns tphlmx=6.5ns + ) .model D_85_2 ugate ( + tphlty=5ns tphlmx=7.5ns + tplhty=4ns tplhmx=6.5ns + ) .model D_85_3 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=9ns tphlmx=13ns + ) .model D_85_4 ugate ( + tplhty=7ns tplhmx=11ns + tphlty=11ns tphlmx=17ns + ) .model D_85_5 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=11ns tphlmx=17ns + ) *--------- * 74HC85A 4-bit Magnitude Comparators * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/29/89 Update interface and model names .subckt 74HC85A P3 P2 P1 P0 Q3 Q2 Q1 Q0 PGQ PEQ PLQ YPGQ YPEQ YPLQ + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * PGQ = P GREATER THAN Q * PLQ = P LESS THAN Q * PEQ = P EQUALS Q * output gate level and-or-invert U1 buf DPWR DGND + PEQ PEQB + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U1PQ bufa(8) DPWR DGND + P3 P2 P1 P0 Q3 Q2 Q1 Q0 + P3D P2D P1D P0D Q3D Q2D Q1D Q0D + D_HC85_2 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2PQ inva(8) DPWR DGND + P3D P2D P1D P0D Q3D Q2D Q1D Q0D + P3BAR P2BAR P1BAR P0BAR Q3BAR Q2BAR Q1BAR Q0BAR + D0_GATE IO_HC UPEQ nxora(4) DPWR DGND + P3D Q3D + P2D Q2D + P1D Q1D + P0D Q0D + PEQ3 PEQ2 PEQ1 PEQ0 + D0_GATE IO_HC U3 anda(3,5) DPWR DGND + PEQ3 PEQ2 $D_HI + PEQ3 PEQ2 PEQ1 + PLQ PEQ0 $D_HI + PEQB PEQ0 $D_HI + PGQ PEQ0 $D_HI + 2MSBE 3MSBE PLQE PEQE PGQED + D0_GATE IO_HC UPEQEDL bufa(2) DPWR DGND + PEQE PGQED PEQEDL PGQE + D_HC85_3 IO_HC MNTYMXDLY={MNTYMXDLY} XPGQ P3BAR Q3D P2BAR Q2D PEQ3 PLQE 3MSBE P1BAR Q1D 2MSBE 3MSBE PEQE P0BAR Q0 + 3MSBE YPGQ DPWR DGND HC85AOI + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XPLQ Q3BAR P3D Q2BAR P2D PEQ3 PGQE 3MSBE Q1BAR P1D 2MSBE 3MSBE PEQEDL Q0BAR P0 + 3MSBE YPLQ DPWR DGND HC85AOI + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 bufa(2) DPWR DGND + 3MSBE PEQ0 3MSBED PEQ0D + D_HC85_5 IO_HC MNTYMXDLY={MNTYMXDLY} UPEQEDE and(2) DPWR DGND + PEQB PEQ0D PEQEDE + D0_GATE IO_HC UYPEQ and(2) DPWR DGND + 3MSBED PEQEDE YPEQ + D_HC85_7 IO_HC .ends .subckt HC85AOI A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 OUT DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA12 aoi(3,6) DPWR DGND + A1 A2 $D_HI + A3 A4 A5 + B1 B2 $D_HI + B3 B4 B5 + C1 C2 $D_HI + C3 C4 C5 + OUT + D_HC85_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC85_1 ugate ( + tplhty=21ns tplhmx=50ns + tphlty=21ns tphlmx=50ns + ) .model D_HC85_2 ugate ( + tplhty=5ns tplhmx=8ns + tphlty=5ns tphlmx=8ns + ) .model D_HC85_3 ugate ( + tplhty=3ns tphlty=3ns + ) .model D_HC85_5 ugate ( + tplhmx=5ns tphlmx=5ns + ) .model D_HC85_7 ugate ( + tplhty=17ns tplhmx=37ns + tphlty=17ns tphlmx=37ns + ) *--------- * 54L85 4-bit Magnitude Comparators * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 54L85 A3 A2 A1 A0 B3 B2 B1 B0 AGBIN AEBIN ALBIN AGBOUT AEBOUT ALBOUT + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * AGBin = A GREATER THAN B * AEBin = A EQUALS B * ALBin = A LESS THAN B * These are outputs from previous comparator stage UIBUF bufa(8) DPWR DGND + A3 A2 A1 A0 B3 B2 B1 B0 + A3_BUF A2_BUF A1_BUF A0_BUF B3_BUF B2_BUF B1_BUF B0_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U2 inva(8) DPWR DGND + A3_BUF A2_BUF A1_BUF A0_BUF B3_BUF B2_BUF B1_BUF B0_BUF + A3B A2B A1B A0B B3B B2B B1B B0B + D0_GATE IO_L X3 A3_BUF B3_BUF A3B B3B $D_HI $D_HI $D_HI ALB3 AEB3 AGB3 DPWR DGND L85BITCOMP + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 A2_BUF B2_BUF A2B B2B AEB3 $D_HI $D_HI ALB2 AEB2 AGB2 DPWR DGND L85BITCOMP + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X1 A1_BUF B1_BUF A1B B1B AEB3 AEB2 $D_HI ALB1 AEB1 AGB1 DPWR DGND L85BITCOMP + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X0 A0_BUF B0_BUF A0B B0B AEB3 AEB2 AEB1 ALB0 AEB0 AGB0 DPWR DGND L85BITCOMP + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UED bufa(4) DPWR DGND + AEB3 AEB2 AEB1 AEB0 AEB3D AEB2D AEB1D AEB0D + D_L85_1 IO_L MNTYMXDLY={MNTYMXDLY} UGL anda(5,2) DPWR DGND + AEB3D AEB2D AEB1D AEB0D AGBin + AEB3D AEB2D AEB1D AEB0D ALBin + AGB4 ALB5 + D0_GATE IO_L UEQ and(5) DPWR DGND + AEB3D AEB2D AEB1D AEB0D AEBin AEBout + D_L85_2 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UGRO ora(5,2) DPWR DGND + AGB3 AGB2 AGB1 AGB0 AGB4 + ALB3 ALB2 ALB1 ALB0 ALB5 + AGBout ALBout + D_L85_2 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * bit-by-bit comparison * .subckt L85BITCOMP A B ABAR BBAR EN1 EN2 EN3 ALB AEB AGB DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 ULE anda(5,2) DPWR DGND + EN1 EN2 EN3 B ABAR + EN1 EN2 EN3 BBAR A + XALB XAGB + D0_GATE IO_L ULD bufa(2) DPWR DGND + XALB XAGB ALB AGB + D_L85_1 IO_L MNTYMXDLY={MNTYMXDLY} UEQ nxor DPWR DGND + A B AEB + D0_GATE IO_L .ends .model D_L85_1 ugate ( + tplhty=15ns tplhmx=0ns + tphlty=20ns tphlmx=50ns + ) .model D_L85_2 ugate ( + tplhty=75ns tplhmx=150ns + tphlty=55ns tphlmx=100ns + ) *--------- * 74LS85 4-bit Magnitude Comparators * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74LS85 A3 A2 A1 A0 B3 B2 B1 B0 AGBIN AEBIN ALBIN AGBOUT AEBOUT ALBOUT + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * AGBin = A GREATER THAN B * ALBin = A LESS THAN B * AEBin = A EQUALS B * first gate level nand to agb and alb outputs UIBUF bufa(9) DPWR DGND + A3 A2 A1 A0 B3 B2 B1 B0 AEBin + A3_BUF A2_BUF A1_BUF A0_BUF B3_BUF B2_BUF B1_BUF B0_BUF AEB_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1GL nanda(2,4) DPWR DGND + A3_BUF B3_BUF + A2_BUF B2_BUF + A1_BUF B1_BUF + A0_BUF B0_BUF + Y13GL Y12GL Y11GL Y10GL + D_LS85_1 IO_LS MNTYMXDLY={MNTYMXDLY} U1E nanda(2,4) DPWR DGND + A3_BUF B3_BUF + A2_BUF B2_BUF + A1_BUF B1_BUF + A0_BUF B0_BUF + Y13E Y12E Y11E Y10E + D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} U23GL aoi(2,2) DPWR DGND + A3_BUF Y13GL Y13GL B3_BUF Y23GL + D_LS85_2 IO_LS MNTYMXDLY={MNTYMXDLY} U22GL aoi(2,2) DPWR DGND + A2_BUF Y12GL Y12GL B2_BUF Y22GL + D_LS85_2 IO_LS MNTYMXDLY={MNTYMXDLY} U21GL aoi(2,2) DPWR DGND + A1_BUF Y11GL Y11GL B1_BUF Y21GL + D_LS85_2 IO_LS MNTYMXDLY={MNTYMXDLY} U20GL aoi(2,2) DPWR DGND + A0_BUF Y10GL Y10GL B0_BUF Y20GL + D_LS85_2 IO_LS MNTYMXDLY={MNTYMXDLY} U23E aoi(2,2) DPWR DGND + A3_BUF Y13E Y13E B3_BUF Y23E + D_LS85_3 IO_LS MNTYMXDLY={MNTYMXDLY} U22E aoi(2,2) DPWR DGND + A2_BUF Y12E Y12E B2_BUF Y22E + D_LS85_3 IO_LS MNTYMXDLY={MNTYMXDLY} U21E aoi(2,2) DPWR DGND + A1_BUF Y11E Y11E B1_BUF Y21E + D_LS85_3 IO_LS MNTYMXDLY={MNTYMXDLY} U20E aoi(2,2) DPWR DGND + A0_BUF Y10E Y10E B0_BUF Y20E + D_LS85_3 IO_LS MNTYMXDLY={MNTYMXDLY} U3G aoi(5,6) DPWR DGND + B3_BUF Y13GL $D_HI $D_HI $D_HI + B2_BUF Y12GL Y23GL $D_HI $D_HI + B1_BUF Y11GL Y23GL Y22GL $D_HI + B0_BUF Y10GL Y23GL Y22GL Y21GL + Y23GL Y22GL Y21GL Y20GL ALBin + Y23GL Y22GL Y21GL Y20GL AEB_BUF + AGBout + D_LS85_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3L aoi(5,6) DPWR DGND + A3_BUF Y13GL $D_HI $D_HI $D_HI + A2_BUF Y12GL Y23GL $D_HI $D_HI + A1_BUF Y11GL Y23GL Y22GL $D_HI + A0_BUF Y10GL Y23GL Y22GL Y21GL + Y23GL Y21GL Y22GL Y20GL AGBin + Y23GL Y22GL Y21GL Y20GL AEB_BUF + ALBout + D_LS85_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3E and(5) DPWR DGND + Y23E Y22E AEB_BUF Y21E Y20E AEBout + D_LS85_5 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS85_1 ugate ( + tplhty=5ns tplhmx=7ns + tphlty=5ns tphlmx=6.5ns + ) .model D_LS85_2 ugate ( + tphlty=5ns tphlmx=7ns + tplhty=4ns tplhmx=6.5ns + ) .model D_LS85_3 ugate ( + tplhty=14ns tplhmx=25ns + tphlty=10ns tphlmx=19ns + ) .model D_LS85_4 ugate ( + tplhty=14ns tplhmx=22ns + tphlty=11ns tphlmx=17ns + ) .model D_LS85_5 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=13ns tphlmx=26ns + ) *--------- * 74S85 4-bit Magnitude Comparators * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74S85 A3 A2 A1 A0 B3 B2 B1 B0 AGBIN AEBIN ALBIN AGBOUT AEBOUT ALBOUT + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * AGBin = A GREATER THAN B * ALBin = A LESS THAN B * AEBin = A EQUALS B UIBUF bufa(9) DPWR DGND + A3 A2 A1 A0 B3 B2 B1 B0 AEBin + A3_BUF A2_BUF A1_BUF A0_BUF B3_BUF B2_BUF B1_BUF B0_BUF AEB_BUF + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U1GL nanda(2,4) DPWR DGND + A3_BUF B3_BUF + A2_BUF B2_BUF + A1_BUF B1_BUF + A0_BUF B0_BUF + Y13GL Y12GL Y11GL Y10GL + D_S85_1 IO_S MNTYMXDLY={MNTYMXDLY} U1E nanda(2,4) DPWR DGND + A3_BUF B3_BUF + A2_BUF B2_BUF + A1_BUF B1_BUF + A0_BUF B0_BUF + Y13E Y12E Y11E Y10E + D0_GATE IO_S MNTYMXDLY={MNTYMXDLY} U23GL aoi(2,2) DPWR DGND + A3_BUF Y13GL Y13GL B3_BUF Y23GL + D_S85_2 IO_S MNTYMXDLY={MNTYMXDLY} U22GL aoi(2,2) DPWR DGND + A2_BUF Y12GL Y12GL B2_BUF Y22GL + D_S85_2 IO_S MNTYMXDLY={MNTYMXDLY} U21GL aoi(2,2) DPWR DGND + A1_BUF Y11GL Y11GL B1_BUF Y21GL + D_S85_2 IO_S MNTYMXDLY={MNTYMXDLY} U20GL aoi(2,2) DPWR DGND + A0_BUF Y10GL Y10GL B0_BUF Y20GL + D_S85_2 IO_S MNTYMXDLY={MNTYMXDLY} U23E aoi(2,2) DPWR DGND + A3_BUF Y13E Y13E B3_BUF Y23E + D_S85_3 IO_S MNTYMXDLY={MNTYMXDLY} U22E aoi(2,2) DPWR DGND + A2_BUF Y12E Y12E B2_BUF Y22E + D_S85_3 IO_S MNTYMXDLY={MNTYMXDLY} U21E aoi(2,2) DPWR DGND + A1_BUF Y11E Y11E B1_BUF Y21E + D_S85_3 IO_S MNTYMXDLY={MNTYMXDLY} U20E aoi(2,2) DPWR DGND + A0_BUF Y10E Y10E B0_BUF Y20E + D_S85_3 IO_S MNTYMXDLY={MNTYMXDLY} U3G aoi(5,6) DPWR DGND + B3_BUF Y13GL $D_HI $D_HI $D_HI + B2_BUF Y12GL Y23GL $D_HI $D_HI + B1_BUF Y11GL Y23GL Y22GL $D_HI + B0_BUF Y10GL Y23GL Y22GL Y21GL + Y23GL Y22GL Y21GL Y20GL ALBin + Y23GL Y22GL Y21GL Y20GL AEB_BUF + AGBout + D_S85_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3L aoi(5,6) DPWR DGND + A3_BUF Y13GL $D_HI $D_HI $D_HI + A2_BUF Y12GL Y23GL $D_HI $D_HI + A1_BUF Y11GL Y23GL Y22GL $D_HI + A0_BUF Y10GL Y23GL Y22GL Y21GL + Y23GL Y21GL Y22GL Y20GL AGBin + Y23GL Y22GL Y21GL Y20GL AEB_BUF + ALBout + D_S85_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3E and(5) DPWR DGND + Y23E Y22E AEB_BUF Y21E Y20E AEBout + D_S85_5 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S85_1 ugate ( + tplhty=3ns tplhmx=4.25ns + tphlty=4ns tphlmx=4ns + ) .model D_S85_2 ugate ( + tphlty=2.5ns tphlmx=4.25ns + tplhty=1.5ns tplhmx=4ns + ) .model D_S85_3 ugate ( + tplhty=5ns tplhmx=7.5ns + tphlty=6ns tphlmx=9ns + ) .model D_S85_4 ugate ( + tplhty=5ns tplhmx=7.5ns + tphlty=5.5ns tphlmx=8.5ns + ) .model D_S85_5 ugate ( + tplhty=7ns tplhmx=10.5ns + tphlty=5ns tphlmx=7.5ns + ) *------------------------------------------------------------------------- * 7486 Quadruple 2-input Exclusive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 7486 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_86_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_86_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_86_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_86_1 ugate ( + tplhty=9ns tplhmx=17ns + tphlty=5ns tphlmx=11ns + ) .model D_86_2 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=7ns tphlmx=16ns + ) .model D_86_3 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) *--------- * 74AC86 Quadruple 2-input Exclusive-Or Gates * * The Advanced CMOS Logic ICs Data Book, RCA * CV 07/13/90 Created from S .subckt 74AC86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_AC86 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC86 ugate ( + tplhmn=2.8ns tplhmx=9.8ns + tphlmn=2.8ns tphlmx=9.8ns + ) *--------- * 74ACT86 Quadruple 2-input Exclusive-Or Gates * * The Advanced CMOS Logic ICs Data Book, RCA * CV 07/13/90 Created from S .subckt 74ACT86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_ACT86 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT86 ugate ( + tplhmn=3.8ns tplhmx=13.3ns + tphlmn=3.8ns tphlmx=13.3ns + ) *--------- * 74ALS86 Quadruple 2-input Exclusive-Or Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/29/89 Update interface and model names .subckt 74ALS86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_ALS86_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_ALS86_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_ALS86_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS86_1 ugate ( + tplhmn=1ns tplhmx=15ns + tphlmn=0ns tphlmx=10ns + ) .model D_ALS86_2 ugate ( + tplhmn=1ns tplhmx=15ns + tphlmn=0ns tphlmx=8ns + ) .model D_ALS86_3 ugate ( + tplhmn=2ns tplhmx=2ns + tphlmn=2ns tphlmx=2ns + ) *--------- * 74AS86 Quadruple 2-input Exclusive-Or Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/29/89 Update interface and model names .subckt 74AS86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_AS86 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS86 ugate ( + tplhty=3.6ns tphlty=3.5ns + ) *--------- * 74F86 Quadruple 2-input Exclusive-Or Gates * * (c) 1988 National Semiconductor. Updated 8/20/90 .subckt 74F86 A B O + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_74F86_1 IO_F MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_74F86_2 IO_F MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D O + D_74F86_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_74F86_1 ugate ( + tplhmn=2ns tplhty=3ns + tplhmx=5.5ns tphlmn=2ns + tphlty=3.2ns tphlmx=5.5ns + ) .model D_74F86_2 ugate ( + tplhmn=2ns tplhty=3.7ns + tplhmx=7ns tphlmn=2.5ns + tphlty=4.3ns tphlmx=6.5ns + ) .model D_74F86_3 ugate ( + tplhmn=1ns tplhty=1ns + tplhmx=1ns tphlmn=1ns + tphlty=1ns tphlmx=1ns + ) *--------- * 74HC86 Quadruple 2-input Exclusive-Or Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/29/89 Update interface and model names .subckt 74HC86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_HC86 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC86 ugate ( + tplhty=12ns tplhmx=25ns + tphlty=12ns tphlmx=25ns + ) *--------- * 54L86 Quadruple 2-input Exclusive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 54L86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_L86_1 IO_L MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_L86_2 IO_L MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_L86_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L86_1 ugate ( + tplhty=75ns tplhmx=150ns + tphlty=25ns tphlmx=90ns + ) .model D_L86_2 ugate ( + tplhty=50ns tplhmx=90ns + ) .model D_L86_3 ugate ( + tphlty=35ns tphlmx=60ns + ) *------- * 74L86 Quadruple 2-input Exclusive-Or Gates * * (c) 1984 National Semiconductor. Updated 8/20/90 .subckt 74L86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_74L86_1 IO_L MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_74L86_2 IO_L MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_74L86_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_74L86_1 ugate ( + tplhty=30ns tplhmx=53ns + tphlty=14ns tphlmx=53ns + ) .model D_74L86_2 ugate ( + tplhty=18ns tplhmx=53ns + tphlty=28ns tphlmx=53ns + ) .model D_74L86_3 ugate ( + tplhty=7ns tplhmx=7ns + tphlty=7ns tphlmx=7ns + ) *--------- * 74LS86 Quadruple 2-input Exclusive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74LS86A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_LS86_1 IO_LS MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_LS86_2 IO_LS MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_LS86_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS86_1 ugate ( + tplhty=12ns tplhmx=23ns + ) .model D_LS86_2 ugate ( + tplhty=20ns tplhmx=30ns + tphlty=3ns tphlmx=5ns + ) .model D_LS86_3 ugate ( + tphlty=10ns tphlmx=17ns + ) *--------- * 74S86 Quadruple 2-input Exclusive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74S86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_S86 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S86 ugate ( + tplhty=7ns tplhmx=10.5ns + tphlty=6.5ns tphlmx=10ns + ) *------------------------------------------------------------------------- * 74H87 4-bit True/Complement, Zero/One Elements * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74H87 A1 A2 A3 A4 B C Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + C C_BUF + D_H87_1 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + B B_BAR + D_H87_1 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X1 A1 B_BAR C_BUF Y1 DPWR DGND SUB87 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 A2 B_BAR C_BUF Y2 DPWR DGND SUB87 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3 A3 B_BAR C_BUF Y3 DPWR DGND SUB87 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X4 A4 B_BAR C_BUF Y4 DPWR DGND SUB87 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt SUB87 A B C Y DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B D + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 xor DPWR DGND + D C Y + D_H87_2 IO_H MNTYMXDLY={MNTYMXDLY} .ends .model D_H87_1 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=3ns tphlmx=5ns + ) .model D_H87_2 ugate ( + tplhty=14ns tplhmx=20ns + tphlty=13ns tphlmx=19ns + ) *------------------------------------------------------------------------- * 7490A 4-bit Binary Counter * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 7490A R91 R92 CKA CKB R01 R02 QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + CKB CKB_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UR0_9 nanda(2,2) DPWR DGND + R01 R02 R91 R92 R0 R9 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UR09 and(2) DPWR DGND + R0 R9 R09 + D0_GATE IO_STD US and(2) DPWR DGND + QB1 QC1 S + D0_GATE IO_STD UJKA jkff(1) DPWR DGND + R9 R0 CKA $D_HI $D_HI QA $D_NC + D_90A_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UJKB jkff(1) DPWR DGND + $D_HI R09 CKB_BUF QDBAR1 $D_HI QBS $D_NC + D_90A_2 IO_STD MNTYMXDLY={MNTYMXDLY} UJKC jkff(1) DPWR DGND + $D_HI R09 QB1 $D_HI $D_HI QCS $D_NC + D_90A_4 IO_STD MNTYMXDLY={MNTYMXDLY} UJKD jkff(1) DPWR DGND + R9 R0 CKB_BUF S QD1 QDS QDBAR + D_90A_3 IO_STD MNTYMXDLY={MNTYMXDLY} UQS bufa(7) DPWR DGND + QBS QCS QDS QBS QCS QDS QDBAR + QB QC QD QB1 QC1 QD1 QDBAR1 + D_90A_5 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_90A_1 ueff ( + twclklmx=15ns twclkhmx=15ns + twpclmx=15ns tsupcclkhmx=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tppcqlhty=20ns tppcqlhmx=30ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=12ns tpclkqhlmx=18ns + ) .model D_90A_2 ueff ( + twclklmx=30ns twclkhmx=30ns + twpclmx=15ns tsupcclkhmx=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=4ns tpclkqlhmx=10ns + tpclkqhlty=8ns tpclkqhlmx=15ns + ) .model D_90A_3 ueff ( + twclklmx=30ns twclkhmx=30ns + twpclmx=15ns tsupcclkhmx=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tppcqlhty=14ns tppcqlhmx=24ns + tpclkqlhty=15ns tpclkqlhmx=26ns + tpclkqhlty=17ns tpclkqhlmx=29ns + ) .model D_90A_4 ueff ( + twclklmx=30ns twclkhmx=30ns + twpclmx=15ns tsupcclkhmx=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=1ns tpclkqlhmx=5ns + tpclkqhlty=3ns tpclkqhlmx=8ns + ) .model D_90A_5 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) *--------- * 74L90 4-bit Binary Counter * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74L90 R91 R92 CKA CKB R01 R02 QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + CKB CKB_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} UR0_9 nanda(2,2) DPWR DGND + R01 R02 R91 R92 R0 R9 + D0_GATE IO_L IO_LEVEL={IO_LEVEL} UR09 and(2) DPWR DGND + R0 R9 R09 + D0_GATE IO_L US and(2) DPWR DGND + QB1 QC1 S + D0_GATE IO_L UJKA jkff(1) DPWR DGND + R9 R0 CKA $D_HI $D_HI QA $D_NC + D_L90_1 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UJKB jkff(1) DPWR DGND + $D_HI R09 CKB_BUF QDBAR1 $D_HI QBS $D_NC + D_L90_1 IO_L MNTYMXDLY={MNTYMXDLY} UJKC jkff(1) DPWR DGND + $D_HI R09 QB1 $D_HI $D_HI QCS $D_NC + D_L90_1 IO_L MNTYMXDLY={MNTYMXDLY} UJKD jkff(1) DPWR DGND + R9 R0 CKB_BUF S QD1 QDS QDBAR + D_L90_2 IO_L MNTYMXDLY={MNTYMXDLY} UQS bufa(7) DPWR DGND + QBS QCS QDS QBS QCS QDS QDBAR + QB QC QD QB1 QC1 QD1 QDBAR1 + D_L90_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L90_1 ueff ( + twclklmx=200ns twclkhmx=200ns + twpclmx=200ns tpclkqlhty=20ns + tpclkqlhmx=20ns tpclkqhlty=20ns + tpclkqhlmx=20ns + ) .model D_L90_2 ueff ( + twclklmx=200ns twclkhmx=200ns + twpclmx=200ns tpclkqlhty=210ns + tpclkqlhmx=320ns tpclkqhlty=210ns + tpclkqhlmx=320ns + ) .model D_L90_3 ugate ( + tphlty=20ns tphlmx=20ns + tplhty=20ns tplhmx=20ns + ) *--------- * 74LS90 4 bit Binary Counter * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74LS90 R91 R92 CKA CKB R01 R02 QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + CKB CKB_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UR0_9 nanda(2,2) DPWR DGND + R01 R02 R91 R92 R0 R9 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UR09S and(2) DPWR DGND + R0 R9 R09 + D0_GATE IO_LS US and(2) DPWR DGND + QB1 QC1 S + D0_GATE IO_LS UJKA jkff(1) DPWR DGND + R9 R0 CKA $D_HI $D_HI QA $D_NC + D_LS90_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UJKB jkff(1) DPWR DGND + $D_HI R09 CKB_BUF QDBAR1 $D_HI QBS $D_NC + D_LS90_2 IO_LS MNTYMXDLY={MNTYMXDLY} UJKC jkff(1) DPWR DGND + $D_HI R09 QB1 $D_HI $D_HI QCS $D_NC + D_LS90_4 IO_LS MNTYMXDLY={MNTYMXDLY} UJKD jkff(1) DPWR DGND + R9 R0 CKB_BUF S QD1 QDS QDBAR + D_LS90_3 IO_LS MNTYMXDLY={MNTYMXDLY} UQS bufa(7) DPWR DGND + QBS QCS QDS QBS QCS QDS QDBAR + QB QC QD QB1 QC1 QD1 QDBAR1 + D_LS90_5 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS90_1 ueff ( + twclklmx=15ns twclkhmx=15ns + twpclmx=30ns tsupcclkhmx=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tppcqlhty=20ns tppcqlhmx=30ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=12ns tpclkqhlmx=18ns + ) .model D_LS90_2 ueff ( + twclklmx=30ns twclkhmx=30ns + twpclmx=30ns tsupcclkhmx=25ns + tppcqhlty=21ns tppcqhlmx=35ns + tpclkqlhty=5ns tpclkqlhmx=11ns + tpclkqhlty=9ns tpclkqhlmx=16ns + ) .model D_LS90_3 ueff ( + twclklmx=30ns twclkhmx=30ns + twpclmx=30ns tsupcclkhmx=25ns + tppcqhlty=21ns tppcqhlmx=35ns + tppcqlhty=15ns tppcqlhmx=25ns + tpclkqlhty=16ns tpclkqlhmx=27ns + tpclkqhlty=18ns tpclkqhlmx=30ns + ) .model D_LS90_4 ueff ( + twclklmx=30ns twclkhmx=30ns + twpclmx=30ns tsupcclkhmx=25ns + tppcqhlty=21ns tppcqhlmx=35ns + tpclkqlhty=2ns tpclkqlhmx=6ns + tpclkqhlty=4ns tpclkqhlmx=9ns + ) .model D_LS90_5 ugate ( + tplhty=5ns tplhmx=5ns + tphlty=5ns tphlmx=5ns + ) *------------------------------------------------------------------------- * 7491A 8-Bit Shift Register * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/15/89 Update interface and model names .subckt 7491A CLK A B QH QHBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B R + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + CLK R CLKB S + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 jkff(1) DPWR DGND + $D_HI $D_HI CLKB S R Q1 QB1 + D_91A_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 jkff(6) DPWR DGND + $D_HI $D_HI CLKB + Q1 Q2 Q3 Q4 Q5 Q6 + QB1 QB2 QB3 QB4 QB5 QB6 + Q2 Q3 Q4 Q5 Q6 Q7 + QB2 QB3 QB4 QB5 QB6 QB7 + D_91A_2 IO_STD MNTYMXDLY={MNTYMXDLY} U5 jkff(1) DPWR DGND + $D_HI $D_HI CLKB Q7 QB7 QH QHBAR + D_91A_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_91A_1 ueff ( + twclkhmn=25ns twclklmn=25ns + tsudclkmn=25ns + ) .model D_91A_2 ueff ( + twclkhmn=25ns twclklmn=25ns + ) .model D_91A_3 ueff ( + twclkhmn=25ns twclklmn=25ns + tpclkqlhty=24ns tpclkqlhmx=40ns + tpclkqhlty=27ns tpclkqhlmx=40ns + ) *--------- * 74L91 8-Bit Shift Register * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/15/89 Update interface and model names .subckt 74L91 CLK A B QH QHBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B R + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + CLK R CLKB S + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 jkff(1) DPWR DGND + $D_HI $D_HI CLKB S R Q1 QB1 + D_L91_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 jkff(6) DPWR DGND + $D_HI $D_HI CLKB + Q1 Q2 Q3 Q4 Q5 Q6 + QB1 QB2 QB3 QB4 QB5 QB6 + Q2 Q3 Q4 Q5 Q6 Q7 + QB2 QB3 QB4 QB5 QB6 QB7 + D_L91_2 IO_STD MNTYMXDLY={MNTYMXDLY} U5 jkff(1) DPWR DGND + $D_HI $D_HI CLKB Q7 QB7 QH QHBAR + D_L91_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L91_1 ueff ( + twclkhmn=100ns twclklmn=150ns + tsudclkmn=120ns + ) .model D_L91_2 ueff ( + twclkhmn=100ns twclklmn=150ns + ) .model D_L91_3 ueff ( + twclkhmn=100ns twclklmn=150ns + tpclkqlhty=55ns tpclkqlhmx=100ns + tpclkqhlty=100ns tpclkqhlmx=150ns + ) *--------- * 74LS91 8-Bit Shift Register * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/15/89 Update interface and model names .subckt 74LS91 CLK A B QH QHBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B R + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + CLK R CLKB S + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 jkff(1) DPWR DGND + $D_HI $D_HI CLKB S R Q1 QB1 + D_LS91_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 jkff(6) DPWR DGND + $D_HI $D_HI CLKB + Q1 Q2 Q3 Q4 Q5 Q6 + QB1 QB2 QB3 QB4 QB5 QB6 + Q2 Q3 Q4 Q5 Q6 Q7 + QB2 QB3 QB4 QB5 QB6 QB7 + D_LS91_2 IO_STD MNTYMXDLY={MNTYMXDLY} U5 jkff(1) DPWR DGND + $D_HI $D_HI CLKB Q7 QB7 QH QHBAR + D_LS91_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS91_1 ueff ( + twclkhmn=25ns twclklmn=25ns + tsudclkmn=25ns + ) .model D_LS91_2 ueff ( + twclkhmn=25ns twclklmn=25ns + ) .model D_LS91_3 ueff ( + twclkhmn=25ns twclklmn=25ns + tpclkqlhty=24ns tpclkqlhmx=40ns + tpclkqhlty=27ns tpclkqhlmx=40ns + ) *------------------------------------------------------------------------- * 7492A Divide-by-Twelve Counter * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/15/89 Update interface and model names .subckt 7492A CKA CKB R01 R02 QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + CKB CLKB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 nand(2) DPWR DGND + R01 R02 CLRB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UEA jkff(1) DPWR DGND + $D_HI CLRB CKA $D_HI $D_HI QA $D_NC + D_92A_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UEB jkff(1) DPWR DGND + $D_HI CLRB CLKB QCB1 $D_HI QBD $D_NC + D_92A_2 IO_STD MNTYMXDLY={MNTYMXDLY} UEC jkff(1) DPWR DGND + $D_HI CLRB CLKB QB1 $D_HI QCD QCB + D_92A_3 IO_STD MNTYMXDLY={MNTYMXDLY} UED jkff(1) DPWR DGND + $D_HI CLRB QC1 $D_HI $D_HI QD $D_NC + D_92A_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 bufa(5) DPWR DGND + QBD QBD QCD QCD QCB + QB QB1 QC QC1 QCB1 + D_92A_5 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_92A_1 ueff ( + twclkhmn=15ns twclklmn=15ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=12ns tpclkqhlmx=18ns + ) .model D_92A_2 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=30ns tsupcclkhmn=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=4ns tpclkqlhmx=10ns + tpclkqhlty=8ns tpclkqhlmx=15ns + ) .model D_92A_3 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=4ns tpclkqlhmx=10ns + tpclkqhlty=8ns tpclkqhlmx=15ns + ) .model D_92A_4 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tpclkqlhty=7ns tpclkqlhmx=11ns + tpclkqhlty=9ns tpclkqhlmx=14ns + ) .model D_92A_5 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *--------- * 74LS92 Divide-by-Twelve Counter * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/15/89 Update interface and model names .subckt 74LS92 CKA CKB R01 R02 QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + CKB CLKB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 nand(2) DPWR DGND + R01 R02 CLRB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UEA jkff(1) DPWR DGND + $D_HI CLRB CKA $D_HI $D_HI QA $D_NC + D_LS92_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UEB jkff(1) DPWR DGND + $D_HI CLRB CLKB QCB1 $D_HI QBD $D_NC + D_LS92_2 IO_STD MNTYMXDLY={MNTYMXDLY} UEC jkff(1) DPWR DGND + $D_HI CLRB CLKB QB1 $D_HI QCD QCB + D_LS92_3 IO_STD MNTYMXDLY={MNTYMXDLY} UED jkff(1) DPWR DGND + $D_HI CLRB QC1 $D_HI $D_HI QD $D_NC + D_LS92_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 bufa(5) DPWR DGND + QBD QBD QCD QCD QCB + QB QB1 QC QC1 QCB1 + D_LS92_5 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS92_1 ueff ( + twclkhmn=15ns twclklmn=15ns + twpclmn=30ns tsupcclkhmn=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=12ns tpclkqhlmx=18ns + ) .model D_LS92_2 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=30ns tsupcclkhmn=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=4ns tpclkqlhmx=10ns + tpclkqhlty=8ns tpclkqhlmx=15ns + ) .model D_LS92_3 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=4ns tpclkqlhmx=10ns + tpclkqhlty=8ns tpclkqhlmx=15ns + ) .model D_LS92_4 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tpclkqlhty=7ns tpclkqlhmx=11ns + tpclkqhlty=9ns tpclkqhlmx=14ns + ) .model D_LS92_5 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *------------------------------------------------------------------------- * 7493A 4-Bit Binary Counter * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/16/89 Update interface and model names .subckt 7493A CKA CKB R01 R02 QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + R01 R02 CLRB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UEA jkff(1) DPWR DGND + $D_HI CLRB CKA $D_HI $D_HI QA $D_NC + D_93A_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UEB jkff(1) DPWR DGND + $D_HI CLRB CKB $D_HI $D_HI QBD $D_NC + D_93A_2 IO_STD MNTYMXDLY={MNTYMXDLY} UEC jkff(1) DPWR DGND + $D_HI CLRB CKC $D_HI $D_HI QCD $D_NC + D_93A_3 IO_STD MNTYMXDLY={MNTYMXDLY} UED jkff(1) DPWR DGND + $D_HI CLRB CKD $D_HI $D_HI QD $D_NC + D_93A_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + QBD QBD QCD QCD QB CKC QC CKD + D_93A_5 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_93A_1 ueff ( + twclkhmn=15ns twclklmn=15ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=12ns tpclkqhlmx=18ns + ) .model D_93A_2 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=4ns tpclkqlhmx=10ns + tpclkqhlty=8ns tpclkqhlmx=15ns + ) .model D_93A_3 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=1ns tpclkqlhmx=5ns + tpclkqhlty=3ns tpclkqhlmx=8ns + ) .model D_93A_4 ueff ( + twclkhmn=15ns twclklmn=15ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tpclkqlhty=11ns tpclkqlhmx=17ns + tpclkqhlty=11ns tpclkqhlmx=17ns + ) .model D_93A_5 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *--------- * 74HC93 Decade, Divide-by-12, and Binary Counters * * (c) Haris Semiconductor, 1989 * cv 08/30/90 .subckt 74HC93 CP0 CP1 MR1 MR2 Q0 Q1 Q2 Q3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + MR1 MR2 CLRB + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} UEA jkff(1) DPWR DGND + $D_HI CLRB CP0 $D_HI $D_HI Q0 $D_NC + D_HC93_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UEB jkff(1) DPWR DGND + $D_HI CLRB CP1 $D_HI $D_HI Q1D $D_NC + D_HC93_2 IO_HC MNTYMXDLY={MNTYMXDLY} UEC jkff(1) DPWR DGND + $D_HI CLRB CP2 $D_HI $D_HI Q2D $D_NC + D_HC93_3 IO_HC MNTYMXDLY={MNTYMXDLY} UED jkff(1) DPWR DGND + $D_HI CLRB CP3 $D_HI $D_HI Q3 $D_NC + D_HC93_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + Q1D Q1D Q2D Q2D Q1 CP2 Q2 CP3 + D_HC93_5 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC93_1 ueff ( + twclkhmn=20ns twclklmn=20ns + twpclmn=20ns tsupcclkhmn=13ns + tppcqhlmx=39ns tpclkqlhmx=31ns + tpclkqhlmx=31ns + ) .model D_HC93_2 ueff ( + twclkhmn=20ns twclklmn=20ns + twpclmn=20ns tsupcclkhmn=13ns + tppcqhlmx=33ns tpclkqlhmx=28ns + tpclkqhlmx=28ns + ) .model D_HC93_3 ueff ( + twclkhmn=20ns twclklmn=20ns + twpclmn=20ns tsupcclkhmn=13ns + tppcqhlmx=33ns tpclkqlhmx=6ns + tpclkqhlmx=6ns + ) .model D_HC93_4 ueff ( + twclkhmn=15ns twclklmn=15ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlmx=39ns tpclkqlhmx=15ns + tpclkqhlmx=15ns + ) .model D_HC93_5 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *--------- * 74HCT93 Decade, Divide-by-12, and Binary Counters * * (c) Haris Semiconductor, 1989 * cv 08/30/90 .subckt 74HCT93 CP0 CP1 MR1 MR2 Q0 Q1 Q2 Q3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + MR1 MR2 CLRB + D0_GATE IO_HCT IO_LEVEL={IO_LEVEL} UEA jkff(1) DPWR DGND + $D_HI CLRB CP0 $D_HI $D_HI Q0 $D_NC + D_HCT93_1 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UEB jkff(1) DPWR DGND + $D_HI CLRB CP1 $D_HI $D_HI Q1D $D_NC + D_HCT93_2 IO_HCT MNTYMXDLY={MNTYMXDLY} UEC jkff(1) DPWR DGND + $D_HI CLRB CP2 $D_HI $D_HI Q2D $D_NC + D_HCT93_3 IO_HCT MNTYMXDLY={MNTYMXDLY} UED jkff(1) DPWR DGND + $D_HI CLRB CP3 $D_HI $D_HI Q3 $D_NC + D_HCT93_4 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + Q1D Q1D Q2D Q2D Q1 CP2 Q2 CP3 + D_HCT93_5 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HCT93_1 ueff ( + twclkhmn=20ns twclklmn=20ns + twpclmn=20ns tsupcclkhmn=13ns + tppcqhlmx=41ns tpclkqlhmx=43ns + tpclkqhlmx=43ns + ) .model D_HCT93_2 ueff ( + twclkhmn=20ns twclklmn=20ns + twpclmn=20ns tsupcclkhmn=13ns + tppcqhlmx=35ns tpclkqlhmx=37ns + tpclkqhlmx=37ns + ) .model D_HCT93_3 ueff ( + twclkhmn=20ns twclklmn=20ns + twpclmn=20ns tsupcclkhmn=13ns + tppcqhlmx=35ns tpclkqlhmx=9ns + tpclkqhlmx=9ns + ) .model D_HCT93_4 ueff ( + twclkhmn=15ns twclklmn=15ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlmx=41ns tpclkqlhmx=15ns + tpclkqhlmx=15ns + ) .model D_HCT93_5 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *--------- * 74LS93 4-Bit Binary Counter * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/16/89 Update interface and model names .subckt 74LS93 CKA CKB R01 R02 QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + R01 R02 CLRB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UEA jkff(1) DPWR DGND + $D_HI CLRB CKA $D_HI $D_HI QA $D_NC + D_LS93_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UEB jkff(1) DPWR DGND + $D_HI CLRB CKB $D_HI $D_HI QBD $D_NC + D_LS93_2 IO_STD MNTYMXDLY={MNTYMXDLY} UEC jkff(1) DPWR DGND + $D_HI CLRB CKC $D_HI $D_HI QCD $D_NC + D_LS93_3 IO_STD MNTYMXDLY={MNTYMXDLY} UED jkff(1) DPWR DGND + $D_HI CLRB CKD $D_HI $D_HI QD $D_NC + D_LS93_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + QBD QBD QCD QCD QB CKC QC CKD + D_LS93_5 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS93_1 ueff ( + twclkhmn=15ns twclklmn=15ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=12ns tpclkqhlmx=18ns + ) .model D_LS93_2 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=4ns tpclkqlhmx=10ns + tpclkqhlty=8ns tpclkqhlmx=15ns + ) .model D_LS93_3 ueff ( + twclkhmn=30ns twclklmn=30ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=20ns tppcqhlmx=34ns + tpclkqlhty=1ns tpclkqlhmx=5ns + tpclkqhlty=3ns tpclkqhlmx=8ns + ) .model D_LS93_4 ueff ( + twclkhmn=15ns twclklmn=15ns + twpclmn=15ns tsupcclkhmn=25ns + tppcqhlty=26ns tppcqhlmx=40ns + tpclkqlhty=11ns tpclkqlhmx=17ns + tpclkqhlty=11ns tpclkqhlmx=17ns + ) .model D_LS93_5 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *------------------------------------------------------------------------- * 7494 4-Bit Shift Register * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/16/89 Update interface and model names .subckt 7494 CLR CLK SER PE1 P1A P1B P1C P1D PE2 P2A P2B P2C P2D QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * The IO_ model of U7 and U8 is IO_LS instead of IO_STD in order to generate * an X for S to sastisfy the setup time requirement U1 bufa(4) DPWR DGND + CLK PE1 PE2 SER CLKB PE1_BUF PE2_BUF S_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + CLR CLRB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 aoi(2,2) DPWR DGND + PE1_BUF P1A PE2_BUF P2A PREA + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U4 aoi(2,2) DPWR DGND + PE1_BUF P1B PE2_BUF P2B PREB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U5 aoi(2,2) DPWR DGND + PE1_BUF P1C PE2_BUF P2C PREC + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U6 aoi(2,2) DPWR DGND + PE1_BUF P1D PE2_BUF P2D PRED + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U7 buf DPWR DGND + S_BUF S + D_94_1 IO_LS MNTYMXDLY={MNTYMXDLY} U8 buf DPWR DGND + S_BUF S + D0_GATE IO_LS UEA dff(1) DPWR DGND + PREA CLRB CLKB S QA $D_NC + D_94_2 IO_STD MNTYMXDLY={MNTYMXDLY} UEB dff(1) DPWR DGND + PREB CLRB CLKB QA QB $D_NC + D_94_2 IO_STD MNTYMXDLY={MNTYMXDLY} UEC dff(1) DPWR DGND + PREC CLRB CLKB QB QC $D_NC + D_94_2 IO_STD MNTYMXDLY={MNTYMXDLY} UED dff(1) DPWR DGND + PRED CLRB CLKB QC QD $D_NC + D_94_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_94_1 ugate ( + tphlmn=10ns tplhmx=10ns + ) .model D_94_2 ueff ( + twclkhmn=35ns twclklmn=35ns + twpclmn=30ns tsudclkmn=25ns + tppcqlhmx=35ns tppcqhlmx=40ns + ) .model D_94_3 ueff ( + twclkhmn=35ns twclklmn=35ns + twpclmn=30ns tsudclkmn=25ns + tppcqlhmx=35ns tppcqhlmx=40ns + tpclkqlhty=25ns tpclkqlhmx=40ns + tpclkqhlty=25ns tpclkqhlmx=40ns + ) *------------------------------------------------------------------------- * 7495A 4-bit Parallel-Access Shift Registers * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/23/89 Update interface and model names .subckt 7495A MODE CLK1 CLK2 SER A B C D QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * In order to meet the spec's, some devices in this subcircuit have IO_LS model, * instead of IO_STD, to create sufficient setup time. UIBUF bufa(3) DPWR DGND + MODE CLK1 CLK2 MODE_BUF CLK11 CLK21 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + MODE_BUF CK1 CK2 MODEB CK1B CK2B + D0_GATE IO_STD U2 buf DPWR DGND + MODEB CK1IN + D_95A_1 IO_STD MNTYMXDLY={MNTYMXDLY} U3 buf DPWR DGND + MODE_BUF CK2IN + D_95A_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 buf DPWR DGND + MODE_BUF CK1EN + D_95A_2 IO_STD MNTYMXDLY={MNTYMXDLY} U5 buf DPWR DGND + MODEB CK2EN + D_95A_3 IO_STD MNTYMXDLY={MNTYMXDLY} U6 anda(3,4) DPWR DGND + CK1EN CK1B MODEB + CK1IN CLK11 MODE_BUF + CK2EN CK2B MODE_BUF + CK2IN CLK21 MODEB + EN1 IN1 EN2 IN2 + D0_GATE IO_STD U7 anda(2,2) DPWR DGND + CLK11 MODEB CLK21 MODE_BUF CK1 CK2 + D0_GATE IO_STD U8 or(2) DPWR DGND + CK1 CK2 CK + D0_GATE IO_STD U9 ora(2,2) DPWR DGND + EN1 EN2 IN1 IN2 EN IN + D0_GATE IO_STD XA MODE_BUF MODEB CK SER A EN IN SQA QA DPWR DGND 95ACHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB MODE_BUF MODEB CK SQA B EN IN SQB QB DPWR DGND 95ACHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC MODE_BUF MODEB CK SQB C EN IN SQC QC DPWR DGND 95ACHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD MODE_BUF MODEB CK SQC D EN IN SQD QD DPWR DGND 95ACHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 95ACHL MD MDB CK SER DAT EN IN SQ Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + SER MDB MD DAT R + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + R S + D0_GATE IO_STD U3 buf DPWR DGND + $D_HI CLRBPREB + D0_GATE IO_LS U4 buf3 DPWR DGND + $D_X EN R + D0_TGATE IO_LS U5 buf3 DPWR DGND + $D_X IN CLRBPREB + D0_TGATE IO_LS U6 jkff(1) DPWR DGND + CLRBPREB CLRBPREB CK S R SQ1 $D_NC + D_95A_4 IO_STD MNTYMXDLY={MNTYMXDLY} U7 bufa(2) DPWR DGND + SQ1 SQ1 SQ Q + D_95A_5 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_95A_1 ugate ( + tphlmn=5ns tphlmx=5ns + ) .model D_95A_2 ugate ( + tplhmn=15ns tplhmx=15ns + ) .model D_95A_3 ugate ( + tphlmn=15ns tphlmx=15ns + ) .model D_95A_4 ueff ( + twclkhmn=20ns twclklmn=20ns + tsudclkmn=15ns tpclkqlhty=12ns + tpclkqlhmx=21ns tpclkqhlty=15ns + tpclkqhlmx=26ns + ) .model D_95A_5 ugate ( + tplhmx=6ns tplhty=6ns + tphlmx=6ns tphlty=6ns + ) *--------- * 74AS95 4-bit Parallel-Access Shift Registers * * The ALS/AS Logic Data Book, 1986, TI * tdn 08/23/89 Update interface and model names .subckt 74AS95 MODE CLK1 CLK2 SER A B C D QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: If MODE changes from HIGH to LOW when both CLOCKs are HIGH, then * for shift-left operation only, the output QD will be in X state. This is * designed to follow the logic diagram in the TI Book. However, this is not * listed in the function table. UIBUF bufa(2) DPWR DGND + MODE CLK1 MODE_BUF CLK1_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + MODE_BUF CK1 CK2 MODEB CK1B CK2B + D0_GATE IO_AS00 MNTYMXDLY={MNTYMXDLY} U2 buf DPWR DGND + CK1 CLK11 + D_AS95_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U3 buf DPWR DGND + CK1 CLK11 + D0_GATE IO_AS00 U4 anda(2,2) DPWR DGND + MODEB CLK1_BUF MODE_BUF CLK2 CK1 CK2 + D0_GATE IO_AS00 U5 and(2) DPWR DGND + MODE CLK11 CKH + D0_GATE IO_AS00 U6 or(3) DPWR DGND + CK1 CK2 CKH CK + D0_GATE IO_AS00 U7 buf DPWR DGND + MODEB CK1IN + D_AS95_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} U8 buf DPWR DGND + MODE_BUF CK1EN + D_AS95_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} U9 buf DPWR DGND + MODEB CK2EN + D_AS95_4 IO_AS00 MNTYMXDLY={MNTYMXDLY} U10 anda(3,3) DPWR DGND + CK1EN CK1B MODEB + CK1IN CLK1 MODE_BUF + CK2EN CK2B MODE_BUF + EN1 IN1 EN2 + D0_GATE IO_AS00 U11 or(2) DPWR DGND + EN1 EN2 EN + D0_GATE IO_AS00 XA MODE_BUF MODEB CK SER A EN IN1 SQA QA DPWR DGND AS95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB MODE_BUF MODEB CK SQA B EN IN1 SQB QB DPWR DGND AS95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC MODE_BUF MODEB CK SQB C EN IN1 SQC QC DPWR DGND AS95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD MODE_BUF MODEB CK SQC D EN IN1 SQD QD DPWR DGND AS95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt AS95CHL MD MDB CK SER DAT EN IN SQ Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + SER MDB MD DAT R + D_AS95_5 IO_AS00 IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + R S + D0_GATE IO_AS00 U3 buf DPWR DGND + $D_HI CLRBPREB + D0_GATE IO_AS00 U4 buf3 DPWR DGND + $D_X EN R + D0_TGATE IO_AS00 U5 buf3 DPWR DGND + $D_X IN CLRBPREB + D0_TGATE IO_AS00 U6 jkff(1) DPWR DGND + CLRBPREB CLRBPREB CK S R SQ1 $D_NC + D_AS95_6 IO_AS00 MNTYMXDLY={MNTYMXDLY} U7 bufa(2) DPWR DGND + SQ1 SQ1 SQ Q + D_AS95_5 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS95_1 ugate ( + tphlmn=3ns tphlmx=3ns + ) .model D_AS95_2 ugate ( + tphlmn=2.5ns tphlmx=2.5ns + ) .model D_AS95_3 ugate ( + tplhmn=12ns tplhmx=12ns + ) .model D_AS95_4 ugate ( + tphlmn=12ns tphlmx=12ns + ) .model D_AS95_5 ugate ( + tplhmn=1ns tphlmn=1ns + ) .model D_AS95_6 ueff ( + twclkhmn=5ns twclklmn=5ns + tsudclkmn=2ns tpclkqlhmn=1ns + tpclkqlhmx=9ns thdclkmn=2.5ns + tpclkqhlmn=1ns tpclkqhlmx=8.5ns + ) *--------- * 74HC95 4-bit Parallel-Access Shift Registers * * (c) Hitachi America, 1988 * cv 08/31/90 .subckt 74HC95 MODE CLK1 CLK2 SER A B C D QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + MODE CLK1 CLK2 MODE_BUF CLK11 CLK21 + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + MODE_BUF CK1 CK2 MODEB CK1B CK2B + D0_GATE IO_HC U2 buf DPWR DGND + MODEB CK1IN + D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} U3 buf DPWR DGND + MODE_BUF CK2IN + D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} U4 buf DPWR DGND + MODE_BUF CK1EN + D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} U5 buf DPWR DGND + MODEB CK2EN + D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} U6 anda(3,4) DPWR DGND + CK1EN CK1B MODEB + CK1IN CLK11 MODE_BUF + CK2EN CK2B MODE_BUF + CK2IN CLK21 MODEB + EN1 IN1 EN2 IN2 + D0_GATE IO_HC U7 anda(2,2) DPWR DGND + CLK11 MODEB CLK21 MODE_BUF CK1 CK2 + D0_GATE IO_HC U8 or(2) DPWR DGND + CK1 CK2 CK + D0_GATE IO_HC U9 ora(2,2) DPWR DGND + EN1 EN2 IN1 IN2 EN IN + D0_GATE IO_HC XA MODE_BUF MODEB CK SER A EN IN SQA QA DPWR DGND HC95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB MODE_BUF MODEB CK SQA B EN IN SQB QB DPWR DGND HC95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC MODE_BUF MODEB CK SQB C EN IN SQC QC DPWR DGND HC95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD MODE_BUF MODEB CK SQC D EN IN SQD QD DPWR DGND HC95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt HC95CHL MD MDB CK SER DAT EN IN SQ Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + SER MDB MD DAT R + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + R S + D0_GATE IO_HC U3 buf DPWR DGND + $D_HI CLRBPREB + D0_GATE IO_HC U4 buf3 DPWR DGND + $D_X EN R + D0_TGATE IO_HC U5 buf3 DPWR DGND + $D_X IN CLRBPREB + D0_TGATE IO_HC U6 jkff(1) DPWR DGND + CLRBPREB CLRBPREB CK S R SQ1 $D_NC + D_HC95_1 IO_HC MNTYMXDLY={MNTYMXDLY} U7 bufa(2) DPWR DGND + SQ1 SQ1 SQ Q + D_HC95_2 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC95_1 ueff ( + twclkhmn=20ns twclklmn=20ns + tsudclkmn=25ns thdclkmn=10ns + tpclkqlhty=11ns tpclkqlhmx=30ns + tpclkqhlty=11ns tpclkqhlmx=37ns + ) .model D_HC95_2 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) *--------- * 54L95 4-bit Parallel-Access Shift Registers * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/23/89 Update interface and model names .subckt 54L95 MODE CLK1 CLK2 SER A B C D QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + MODE MODE_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + MODE_BUF CK1 CK2 MODEB CK1B CK2B + D0_GATE IO_L U2 buf DPWR DGND + MODEB CK1IN + D_54L95_1 IO_L MNTYMXDLY={MNTYMXDLY} U3 buf DPWR DGND + MODE_BUF CK1EN + D_54L95_2 IO_L MNTYMXDLY={MNTYMXDLY} U4 buf DPWR DGND + MODEB CK2EN + D_54L95_3 IO_L MNTYMXDLY={MNTYMXDLY} U5 anda(3,3) DPWR DGND + CK1EN CK1B MODEB + CK1IN CLK1 MODE_BUF + CK2EN CK2B MODE_BUF + EN1 IN1 EN2 + D0_GATE IO_L U6 anda(2,2) DPWR DGND + CLK1 MODEB CLK2 MODE_BUF CK1 CK2 + D0_GATE IO_L U7 or(2) DPWR DGND + CK1 CK2 CK + D0_GATE IO_L XA MODE_BUF MODEB CK SER EN1 IN1 EN2 A SQA QA DPWR DGND 54L95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB MODE_BUF MODEB CK SQA EN1 IN1 EN2 B SQB QB DPWR DGND 54L95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC MODE_BUF MODEB CK SQB EN1 IN1 EN2 C SQC QC DPWR DGND 54L95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD MODE_BUF MODEB CK SQC EN1 IN1 EN2 D SQD QD DPWR DGND 54L95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 54L95CHL MD MDB CK SER EN1 IN1 EN2 DAT SQ Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + SER MDB MD DAT R + D0_GATE IO_L IO_LEVEL={IO_LEVEL} X1 R RX DPWR DGND 54L95TSUDAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + RX SX + D0_GATE IO_L U3 buf3 DPWR DGND + $D_X EN1 RX + D0_TGATE IO_L U4 buf3a(2) DPWR DGND + $D_X $D_X IN1 CLRB PREB + D0_TGATE IO_L U5 buf3 DPWR DGND + $D_X EN2 RX + D0_TGATE IO_L U6 jkff(1) DPWR DGND + CLRB PREB CK SX RX SQ1 $D_NC + D_54L95_5 IO_L MNTYMXDLY={MNTYMXDLY} U7 bufa(2) DPWR DGND + SQ1 SQ1 SQ Q + D_54L95_6 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 bufa(2) DPWR DGND + $D_HI $D_HI CLRB PREB + D0_GATE IO_L .ends .subckt 54L95TSUDAT DAT DATX + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + DAT DATX + D_54L95_4 IO_L MNTYMXDLY={MNTYMXDLY} U2 buf DPWR DGND + DAT DATX + D0_GATE IO_L .ends .model D_54L95_1 ugate ( + tphlmn=100ns tphlmx=100ns + ) .model D_54L95_2 ugate ( + tplhmn=225ns tplhmx=225ns + ) .model D_54L95_3 ugate ( + tphlmn=200ns tphlmx=200ns + ) .model D_54L95_4 ugate ( + tplhmn=20ns tplhmx=20ns + ) .model D_54L95_5 ueff ( + twclkhmn=200ns twclklmn=200ns + tsudclkmn=100ns tpclkqlhty=95ns + tpclkqlhmx=180ns tpclkqhlty=105ns + tpclkqhlmx=180ns + ) .model D_54L95_6 ugate ( + tplhmx=20ns tplhty=20ns + tphlmx=20ns tphlty=20ns + ) *--------- * 74L95 4-bit Parallel-Access Shift Registers * * (c) National Semiconductor, 1987 * cv 08/31/90 .subckt 74L95 MODE CLK1 CLK2 SER A B C D QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + MODE CLK1 CLK2 MODE_BUF CLK11 CLK21 + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + MODE_BUF CK1 CK2 MODEB CK1B CK2B + D0_GATE IO_L U2 buf DPWR DGND + MODEB CK1IN + D_74L95_1 IO_L MNTYMXDLY={MNTYMXDLY} U3 buf DPWR DGND + MODE_BUF CK2IN + D_74L95_1 IO_L MNTYMXDLY={MNTYMXDLY} U4 buf DPWR DGND + MODE_BUF CK1EN + D_74L95_2 IO_L MNTYMXDLY={MNTYMXDLY} U5 buf DPWR DGND + MODEB CK2EN + D_74L95_3 IO_L MNTYMXDLY={MNTYMXDLY} U6 anda(3,4) DPWR DGND + CK1EN CK1B MODEB + CK1IN CLK11 MODE_BUF + CK2EN CK2B MODE_BUF + CK2IN CLK21 MODEB + EN1 IN1 EN2 IN2 + D0_GATE IO_L U7 anda(2,2) DPWR DGND + CLK11 MODEB CLK21 MODE_BUF CK1 CK2 + D0_GATE IO_L U8 or(2) DPWR DGND + CK1 CK2 CK + D0_GATE IO_L U9 ora(2,2) DPWR DGND + EN1 EN2 IN1 IN2 EN IN + D0_GATE IO_L XA MODE_BUF MODEB CK SER A EN IN SQA QA DPWR DGND 74L95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB MODE_BUF MODEB CK SQA B EN IN SQB QB DPWR DGND 74L95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC MODE_BUF MODEB CK SQB C EN IN SQC QC DPWR DGND 74L95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD MODE_BUF MODEB CK SQC D EN IN SQD QD DPWR DGND 74L95CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 74L95CHL MD MDB CK SER DAT EN IN SQ Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + SER MDB MD DAT R + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + R S + D0_GATE IO_L U3 buf DPWR DGND + $D_HI CLRBPREB + D0_GATE IO_L U4 buf3 DPWR DGND + $D_X EN R + D0_TGATE IO_L U5 buf3 DPWR DGND + $D_X IN CLRBPREB + D0_TGATE IO_L U6 jkff(1) DPWR DGND + CLRBPREB CLRBPREB CK S R SQ1 $D_NC + D_74L95_4 IO_L MNTYMXDLY={MNTYMXDLY} U7 bufa(2) DPWR DGND + SQ1 SQ1 SQ Q + D_74L95_5 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_74L95_1 ugate ( + tphlmn=0ns tphlmx=0ns + ) .model D_74L95_2 ugate ( + tplhmn=120ns tplhmx=120ns + ) .model D_74L95_3 ugate ( + tphlmn=100ns tphlmx=100ns + ) .model D_74L95_4 ueff ( + twclkhmn=90ns twclklmn=90ns + tsudclkmn=50ns tpclkqlhmx=84ns + tpclkqhlmx=84ns + ) .model D_74L95_5 ugate ( + tplhmx=6ns tphlmx=6ns + ) *--------- * 74LS95B 4-bit Parallel-Access Shift Registers * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/23/89 Update interface and model names .subckt 74LS95B MODE CLK1 CLK2 SER A B C D QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + MODE CLK1 CLK2 MODE_BUF CLK11 CLK21 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + MODE_BUF CK1 CK2 MODEB CK1B CK2B + D0_GATE IO_LS U2 buf DPWR DGND + MODEB CK1IN + D_LS95B_1 IO_LS MNTYMXDLY={MNTYMXDLY} U3 buf DPWR DGND + MODE_BUF CK2IN + D_LS95B_1 IO_LS MNTYMXDLY={MNTYMXDLY} U4 buf DPWR DGND + MODE_BUF CK1EN + D_LS95B_2 IO_LS MNTYMXDLY={MNTYMXDLY} U5 buf DPWR DGND + MODEB CK2EN + D_LS95B_1 IO_LS MNTYMXDLY={MNTYMXDLY} U6 anda(3,4) DPWR DGND + CK1EN CK1B MODEB + CK1IN CLK11 MODE_BUF + CK2EN CK2B MODE_BUF + CK2IN CLK21 MODEB + EN1 IN1 EN2 IN2 + D0_GATE IO_LS U7 anda(2,2) DPWR DGND + CLK11 MODEB CLK21 MODE_BUF CK1 CK2 + D0_GATE IO_LS U8 or(2) DPWR DGND + CK1 CK2 CK + D0_GATE IO_LS U9 ora(2,2) DPWR DGND + EN1 EN2 IN1 IN2 EN IN + D0_GATE IO_LS XA MODE_BUF MODEB CK SER A EN IN SQA QA DPWR DGND LS95BCHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB MODE_BUF MODEB CK SQA B EN IN SQB QB DPWR DGND LS95BCHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC MODE_BUF MODEB CK SQB C EN IN SQC QC DPWR DGND LS95BCHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD MODE_BUF MODEB CK SQC D EN IN SQD QD DPWR DGND LS95BCHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt LS95BCHL MD MDB CK SER DAT EN IN SQ Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + SER MDB MD DAT R + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + R S + D0_GATE IO_LS U3 buf DPWR DGND + $D_HI CLRBPREB + D0_GATE IO_LS U4 buf3 DPWR DGND + $D_X EN R + D0_TGATE IO_LS U5 buf3 DPWR DGND + $D_X IN CLRBPREB + D0_TGATE IO_LS U6 jkff(1) DPWR DGND + CLRBPREB CLRBPREB CK S R SQ1 $D_NC + D_LS95B_3 IO_LS MNTYMXDLY={MNTYMXDLY} U7 bufa(2) DPWR DGND + SQ1 SQ1 SQ Q + D_LS95B_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS95B_1 ugate ( + tphlmn=20ns tphlmx=20ns + ) .model D_LS95B_2 ugate ( + tplhmn=20ns tplhmx=20ns + ) .model D_LS95B_3 ueff ( + twclkhmn=20ns twclklmn=20ns + tsudclkmn=20ns tpclkqlhty=12ns + tpclkqlhmx=21ns thdclkmn=10ns + tpclkqhlty=15ns tpclkqhlmx=26ns + ) .model D_LS95B_4 ugate ( + tplhmx=6ns tplhty=6ns + tphlmx=6ns tphlty=6ns + ) *------------------------------------------------------------------------- * 7496 5-bit Shift Registers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 7496 CLK CLRBAR SER PRE A B C D E QA QB QC QD QE + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + CLRBAR PRE SER CLRBAR_BUF PRE_BUF SER_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UCK inva(2) DPWR DGND + CLK SER_BUF CLKBAR SERB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 nanda(2,5) DPWR DGND + A PRE_BUF + B PRE_BUF + C PRE_BUF + D PRE_BUF + E PRE_BUF + PREA PREB PREC PRED PREE + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} XA PREA CLRBAR_BUF CLKBAR SER_BUF SERB SQA SQAB QA DPWR DGND 96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB PREB CLRBAR_BUF CLKBAR SQA SQAB SQB SQBB QB DPWR DGND 96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC PREC CLRBAR_BUF CLKBAR SQB SQBB SQC SQCB QC DPWR DGND 96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD PRED CLRBAR_BUF CLKBAR SQC SQCB SQD SQDB QD DPWR DGND 96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XE PREE CLRBAR_BUF CLKBAR SQD SQDB SQE SQEB QE DPWR DGND 96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 96CHL PRES CLRBARS CK S R SQ SQB Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 URS jkff(1) DPWR DGND + PRES CLRBARS CK S R SQ1 SQB1 + D_96_1 IO_STD MNTYMXDLY={MNTYMXDLY} UQ bufa(3) DPWR DGND + SQ1 SQ1 SQB1 Q SQ SQB + D_96_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_96_1 ueff ( + twclkhmx=35ns twclklmx=35ns + twpclmx=30ns thdclkmx=30ns + tppcqlhty=22ns tppcqlhmx=29ns + tppcqhlmx=49ns tpclkqlhty=19ns + tpclkqlhmx=34ns tpclkqhlty=19ns + tpclkqhlmx=34ns + ) .model D_96_2 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *--------- * 74L96 5-bit Shift Registers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74L96 CLK CLRBAR SER PRE A B C D E QA QB QC QD QE + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + PRE CLRBAR SER PRE_BUF CLRBAR_BUF SER_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} UCK inva(2) DPWR DGND + CLK SER_BUF CLKBAR SERB + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 nanda(2,5) DPWR DGND + A PRE_BUF + B PRE_BUF + C PRE_BUF + D PRE_BUF + E PRE_BUF + PREA PREB PREC PRED PREE + D0_GATE IO_L IO_LEVEL={IO_LEVEL} XA PREA CLRBAR_BUF CLKBAR SER_BUF SERB SQA SQAB QA DPWR DGND L96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB PREB CLRBAR_BUF CLKBAR SQA SQAB SQB SQBB QB DPWR DGND L96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC PREC CLRBAR_BUF CLKBAR SQB SQBB SQC SQCB QC DPWR DGND L96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD PRED CLRBAR_BUF CLKBAR SQC SQCB SQD SQDB QD DPWR DGND L96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XE PREE CLRBAR_BUF CLKBAR SQD SQDB SQE SQEB QE DPWR DGND L96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt L96CHL PRE CLRBAR CK S R SQ SQB Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 URS jkff(1) DPWR DGND + PRE CLRBAR CK S R SQ1 SQB1 + D_L96_1 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ1 buf DPWR DGND + SQ1 Q + D_L96_2 IO_L MNTYMXDLY={MNTYMXDLY} UQ2 bufa(2) DPWR DGND + SQ1 SQB1 SQ SQB + D_L96_3 IO_L MNTYMXDLY={MNTYMXDLY} .ends .model D_L96_1 ueff ( + twclkhmx=100ns twclklmx=100ns + twpclmx=100ns twpclmn=100ns + thdclkmx=100ns tppcqlhty=36ns + tppcqlhmx=50ns tppcqhlmx=90ns + tpclkqlhty=30ns tpclkqlhmx=60ns + tpclkqhlty=30ns tpclkqhlmx=60ns + ) .model D_L96_2 ugate ( + tplhty=20ns tplhmx=20ns + tphlty=20ns tphlmx=20ns + ) .model D_L96_3 ugate ( + tplhty=40ns tplhmx=40ns + tphlty=40ns tphlmx=40ns + ) *--------- * 74LS96 5-bit Shift Registers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74LS96 CLK CLRBAR SER PRE A B C D E QA QB QC QD QE + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + PRE CLRBAR SER PRE_BUF CLRBAR_BUF SER_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UCK inva(2) DPWR DGND + CLK SER_BUF CLKBAR SERB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 nanda(2,5) DPWR DGND + A PRE_BUF + B PRE_BUF + C PRE_BUF + D PRE_BUF + E PRE_BUF + PREA PREB PREC PRED PREE + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} XA PREA CLRBAR_BUF CLKBAR SER_BUF SERB SQA SQAB QA DPWR DGND LS96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB PREB CLRBAR_BUF CLKBAR SQA SQAB SQB SQBB QB DPWR DGND LS96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC PREC CLRBAR_BUF CLKBAR SQB SQBB SQC SQCB QC DPWR DGND LS96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD PRED CLRBAR_BUF CLKBAR SQC SQCB SQD SQDB QD DPWR DGND LS96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XE PREE CLRBAR_BUF CLKBAR SQD SQDB SQE SQEB QE DPWR DGND LS96CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt LS96CHL PRE CLRBAR CK S R SQ SQB Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 URS jkff(1) DPWR DGND + PRE CLRBAR CK S R SQ1 SQB1 + D_LS96_1 IO_LS MNTYMXDLY={MNTYMXDLY} UQ bufa(3) DPWR DGND + SQ1 SQ1 SQB1 Q SQ SQB + D_LS96_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS96_1 ueff ( + twclkhmx=20ns twclklmx=20ns + twpclmx=30ns thdclkmx=30ns + tppcqlhty=22ns tppcqlhmx=26ns + tppcqhlmx=49ns tpclkqlhty=19ns + tpclkqlhmx=34ns tpclkqhlty=19ns + tpclkqhlmx=34ns + ) .model D_LS96_2 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *------------------------------------------------------------------------- * 7497 Synchronous 6-bit Binary Rate Multipliers * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/30/89 Update interface and model names .subckt 7497 CLR STRB CLK ENIN B0 B1 B2 B3 B4 B5 UNICAS Y Z ENOUT + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: Some devices in this SUBCKT are IO_LS model, even though the IC is STD * type. This is done to meet the setup, and hold time spec of the ENin pin, * since the IO_STD-typed devices cannot perform this task. U1 bufa(8) DPWR DGND + ENin CLK B5 B4 B3 B2 B1 B0 + EI CLKD B5D B4D B3D B2D B1D B0D + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inva(9) DPWR DGND + EI CLKD STRB CLR EF EE ED EC EB + EIB CLKB STRBB CLRB EFB EEB EDB ECB EBB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 bufa(12) DPWR DGND + QA QAB QB QBB QC QCB + QD QDB QE QEB QF QFB + QA1 QAB1 QB1 QBB1 QC1 QCB1 + QD1 QDB1 QE1 QEB1 QF1 QFB1 + D_97_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 bufa(12) DPWR DGND + QA1 QAB1 QB1 QBB1 QC1 QCB1 + QD1 QDB1 QE1 QEB1 QF1 QFB1 + QA2 QAB2 QB2 QBB2 QC2 QCB2 + QD2 QDB2 QE2 QEB2 QF2 QFB2 + D_97_2 IO_STD MNTYMXDLY={MNTYMXDLY} U5 anda(8,12) DPWR DGND + QFB2 QE2 QD2 QC2 QB2 QA2 CKSTY B0D + $D_HI QEB2 QD2 QC2 QB2 QA2 CKSTY B1D + $D_HI $D_HI QDB2 QC2 QB2 QA2 CKSTY B2D + $D_HI $D_HI $D_HI QCB2 QB2 QA2 CKSTY B3D + $D_HI $D_HI $D_HI $D_HI QBB2 QA2 CKSTY B4D + $D_HI $D_HI $D_HI $D_HI $D_HI QAB2 CKSTY B5D + QFB1 QE1 QD1 QC1 QB1 QA1 CKSTZ B0D + $D_HI QEB1 QD1 QC1 QB1 QA1 CKSTZ B1D + $D_HI $D_HI QDB1 QC1 QB1 QA1 CKSTZ B2D + $D_HI $D_HI $D_HI QCB1 QB1 QA1 CKSTZ B3D + $D_HI $D_HI $D_HI $D_HI QBB1 QA1 CKSTZ B4D + $D_HI $D_HI $D_HI $D_HI $D_HI QAB1 CKSTZ B5D + AY BY CY DY EY FY + AZ BZ CZ DZ EZ FZ + D0_GATE IO_STD U6 anda(6,5) DPWR DGND + QE QD QC QB QA EIB + $D_HI QD QC QB QA EIB + $D_HI $D_HI QC QB QA EIB + $D_HI $D_HI $D_HI QB QA EIB + $D_HI $D_HI $D_HI $D_HI QA EIB + EF EE ED EC EB + D0_GATE IO_STD U7 buf DPWR DGND + EI EID + D_97_3 IO_STD MNTYMXDLY={MNTYMXDLY} U8 and(4) DPWR DGND + EID EIB CLKD CLRB X2 + D0_GATE IO_STD XA CLKB CLRB EI EIB X2 QA QAB DPWR DGND 97ENSUHD + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB CLKB CLRB EBB EB X2 QB QBB DPWR DGND 97ENSUHD + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC CLKB CLRB ECB EC X2 QC QCB DPWR DGND 97ENSUHD + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD CLKB CLRB EDB ED X2 QD QDB DPWR DGND 97ENSUHD + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XE CLKB CLRB EEB EE X2 QE QEB DPWR DGND 97ENSUHD + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XF CLKB CLRB EFB EF X2 QF QFB DPWR DGND 97ENSUHD + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 buf DPWR DGND + CLKB CKBY + D_97_4 IO_STD MNTYMXDLY={MNTYMXDLY} U10 buf DPWR DGND + CLKB CKBZ + D_97_5 IO_STD MNTYMXDLY={MNTYMXDLY} U11 buf DPWR DGND + STRBB STRY + D_97_6 IO_STD MNTYMXDLY={MNTYMXDLY} U12 and(2) DPWR DGND + CKBY STRY CKSTY + D_97_7 IO_STD MNTYMXDLY={MNTYMXDLY} U13 and(2) DPWR DGND + CKBZ STRBB CKSTZ + D_97_8 IO_STD MNTYMXDLY={MNTYMXDLY} U14 nand(7) DPWR DGND + QF QE QD QC QB QA EIB ENout + D_97_9 IO_STD MNTYMXDLY={MNTYMXDLY} U15 nor(6) DPWR DGND + AY BY CY DY EY FY Y1 + D_97_10 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U16 nor(6) DPWR DGND + AZ BZ CZ DZ EZ FZ Z + D_97_11 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U17 nand(2) DPWR DGND + Y1 UNICASD Y + D_97_12 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U18 buf DPWR DGND + UNICAS UNICASD + D_97_13 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 97ENSUHD CLKB CLRB IN INB XEN2 Q QBAR DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 srff(1) DPWR DGND + $D_HI CLRS CLKB INBD $D_LO INP $D_NC + D_97_14 IO_STD MNTYMXDLY={MNTYMXDLY} U2 buf DPWR DGND + CLRB CLRBD + D_97_15 IO_STD MNTYMXDLY={MNTYMXDLY} U3 buf DPWR DGND + INB INBD + D_97_16 IO_STD MNTYMXDLY={MNTYMXDLY} U4 suhdck(1) DPWR DGND + CLRS INB SUOUT $D_NC + D_97_17 IO_STD MNTYMXDLY={MNTYMXDLY} U5 and(3) DPWR DGND + SUOUT IN CLRBD XEN1 + D0_GATE IO_STD U6 buf3a(2) DPWR DGND + $D_X $D_X XEN1 INP PRE + D0_TGATE IO_LS U7 buf3 DPWR DGND + $D_X XEN2 PRE + D0_TGATE IO_LS U8 and(2) DPWR DGND + CLRB CLKB CLRS + D0_GATE IO_STD U9 jkff(1) DPWR DGND + PRE CLRB CLKB INP INP Q QBAR + D_97_18 IO_STD MNTYMXDLY={MNTYMXDLY} U10 buf DPWR DGND + $D_HI PRE + D0_GATE IO_LS .ends .model D_97_1 ugate ( + tphlty=6ns tphlmx=9ns + tplhty=6ns tplhmx=9ns + ) .model D_97_2 ugate ( + tphlty=3ns tphlmx=4ns + tplhty=3ns tplhmx=4ns + ) .model D_97_3 ugate ( + tphlmx=25ns + ) .model D_97_4 ugate ( + tplhty=7ns tplhmx=9ns + ) .model D_97_5 ugate ( + tplhty=2ns tplhmx=3ns + ) .model D_97_6 ugate ( + tphlty=2ns tphlmx=3ns + ) .model D_97_7 ugate ( + tphlty=5ns tphlmx=7ns + tplhty=4ns tplhmx=7ns + ) .model D_97_8 ugate ( + tphlty=6ns tphlmx=8ns + tplhty=6ns tplhmx=9ns + ) .model D_97_9 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=14ns tphlmx=21ns + ) .model D_97_10 ugate ( + tphlty=9ns tphlmx=13ns + tplhty=9ns tplhmx=13ns + ) .model D_97_11 ugate ( + tphlty=9ns tphlmx=14ns + tplhty=6ns tplhmx=10ns + ) .model D_97_12 ugate ( + tphlty=6ns tphlmx=10ns + tplhty=6ns tplhmx=10ns + ) .model D_97_13 ugate ( + tphlty=3ns tphlmx=4ns + ) .model D_97_14 ugff ( + twghmn=20ns tsudgmn=10ns + thdgmn=20ns tppcqhlmn=5ns + ) .model D_97_15 ugate ( + tplhmn=.1ns + ) .model D_97_16 ugate ( + tphlty=5ns tphlmx=5ns + ) .model D_97_17 usuhd ( + tsumn=10ns + ) .model D_97_18 ueff ( + twclkhmn=20ns twclklmn=20ns + twpclmn=15ns tpclkqhlty=6ns + tpclkqhlmx=13ns tpclkqlhty=8ns + tpclkqlhmx=12ns + ) *------------------------------------------------------------------------- * 54L98 4-Bit Data Selectors/Storage Registers * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/16/89 Update interface and model names .subckt 54L98 CLK WS A1 B1 C1 D1 A2 B2 C2 D2 QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + CLK CLKB + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U2 bufa(10) DPWR DGND + WS WS_BUF A1 B1 C1 + D1 A2 B2 C2 D2 + WS_BUF WSB A1B B1B C1B + D1B A2B B2B C2B D2B + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U3 buf DPWR DGND + WS_BUF WSB + D_L98_1 IO_LS MNTYMXDLY={MNTYMXDLY} U4 inv DPWR DGND + WS_BUF WSBB + D0_GATE IO_L U5 bufa(8) DPWR DGND + A1B A2B B1B B2B C1B C2B D1B D2B + A1BB A2BB B1BB B2BB C1BB C2BB D1BB D2BB + D_L98_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 bufa(8) DPWR DGND + A1B A2B B1B B2B C1B C2B D1B D2B + A1BB A2BB B1BB B2BB C1BB C2BB D1BB D2BB + D0_GATE IO_LS U7 ao(2,2) DPWR DGND + A1BB WSBB A2BB WSB A + D0_GATE IO_L U8 ao(2,2) DPWR DGND + B1BB WSBB B2BB WSB B + D0_GATE IO_L U9 ao(2,2) DPWR DGND + C1BB WSBB C2BB WSB C + D0_GATE IO_L U10 ao(2,2) DPWR DGND + D1BB WSBB D2BB WSB D + D0_GATE IO_L U11 dff(4) DPWR DGND + $D_HI $D_HI CLKB + A B C D + QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D_L98_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L98_1 ugate ( + tplhmn=50ns tplhmx=50ns + ) .model D_L98_2 ugate ( + tphlmn=20ns tphlmx=20ns + ) .model D_L98_3 ueff ( + twclkhmn=200ns tsudclkmn=100ns + tpclkqlhty=115ns tpclkqlhmx=200ns + tpclkqhlty=125ns tpclkqhlmx=200ns + ) *------------------------------------------------------------------------- * 54L99 4-bit Right-Shift Left-Shift Register * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/24/89 Update interface and model names .subckt 54L99 MODE CLK1 CLK2 J KBAR A B C D QA QB QC QD QDBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + MODE KBAR MODE_BUF KB + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + MODE_BUF CK1 CK2 MODEB CK1B CK2B + D0_GATE IO_L U2 buf DPWR DGND + MODEB CK1IN + D_L99_1 IO_L MNTYMXDLY={MNTYMXDLY} U3 buf DPWR DGND + MODE_BUF CK1EN + D_L99_2 IO_L MNTYMXDLY={MNTYMXDLY} U4 buf DPWR DGND + MODEB CK2EN + D_L99_3 IO_L MNTYMXDLY={MNTYMXDLY} U5 anda(3,3) DPWR DGND + CK1EN CK1B MODEB + CK1IN CLK1 MODE_BUF + CK2EN CK2B MODE_BUF + EN1 IN1 EN2 + D0_GATE IO_L U6 anda(2,2) DPWR DGND + CLK1 MODEB CLK2 MODE_BUF CK1 CK2 + D0_GATE IO_L U7 or(2) DPWR DGND + CK1 CK2 CK + D0_GATE IO_L UAS anda(4,4) DPWR DGND + J QAB CK MODEB + CK MODE_BUF A $D_HI + K SQA CK MODEB + CK MODE_BUF AB $D_HI + S1 S2 S3 S4 + D0_GATE IO_L USR nora(3,2) DPWR DGND + S1 S2 SA S3 S4 RA RA SA + D0_GATE IO_L X1 RA RX DPWR DGND L99TSUDAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 SA SX DPWR DGND L99TSUDAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3 EN1 IN1 EN2 RX CLRBPREB DPWR DGND L99XCLK12 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UAV inva(3) DPWR DGND + J KB A JB K AB + D0_GATE IO_L UAE jkff(1) DPWR DGND + CLRBPREB CLRBPREB CK SX RX QAD QABD + D_L99_4 IO_L MNTYMXDLY={MNTYMXDLY} UAB bufa(3) DPWR DGND + QAD QAD QABD SQA QA QAB + D_L99_5 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB MODE_BUF MODEB CK SQA B EN1 IN1 EN2 SQB QB $D_NC DPWR DGND L99CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC MODE_BUF MODEB CK SQB C EN1 IN1 EN2 SQC QC $D_NC DPWR DGND L99CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD MODE_BUF MODEB CK SQC D EN1 IN1 EN2 SQD QD QDBAR DPWR DGND L99CHL + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt L99TSUDAT DAT DATX DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + DAT DATX + D_L99_6 IO_L MNTYMXDLY={MNTYMXDLY} U2 buf DPWR DGND + DAT DATX + D0_GATE IO_L .ends .subckt L99XCLK12 EN1 IN1 EN2 XDAT XCLRBPREB DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + EN1 EN2 EN + D0_GATE IO_L U2 buf3 DPWR DGND + $D_X EN XDAT + D0_TGATE IO_L U3 buf3 DPWR DGND + $D_X IN1 XCLRBPREB + D0_TGATE IO_L U4 buf DPWR DGND + $D_HI XCLRBPREB + D0_GATE IO_L .ends .subckt L99CHL MD MDB CK SER DAT EN1 IN1 EN2 SQ Q QB DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + SER MDB MD DAT R + D0_GATE IO_L IO_LEVEL={IO_LEVEL} X1 R RX DPWR DGND L99TSUDAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 EN1 IN1 EN2 RX CLRBPREB DPWR DGND L99XCLK12 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + RX SX + D0_GATE IO_L U3 jkff(1) DPWR DGND + CLRBPREB CLRBPREB CK SX RX SQ1 SQ1B + D_L99_4 IO_L MNTYMXDLY={MNTYMXDLY} U4 bufa(3) DPWR DGND + SQ1 SQ1 SQ1B SQ Q QB + D_L99_5 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L99_1 ugate ( + tphlmn=100ns tphlmx=100ns + ) .model D_L99_2 ugate ( + tplhmn=225ns tplhmx=225ns + ) .model D_L99_3 ugate ( + tphlmn=200ns tphlmx=200ns + ) .model D_L99_4 ueff ( + twclkhmn=200ns twclklmn=200ns + tsudclkmn=100ns tpclkqlhty=95ns + tpclkqlhmx=180ns tpclkqhlty=105ns + tpclkqhlmx=180ns + ) .model D_L99_5 ugate ( + tplhmn=20ns tplhmx=20ns + tphlmn=20ns tphlmx=20ns + ) .model D_L99_6 ugate ( + tplhmn=20ns tplhmx=20ns + ) *------------------------------------------------------------------------- * 74100 8-Bit Bistable Latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/17/89 Update interface and model names .subckt 74100 1C 1D1 1D2 1D3 1D4 1Q1 1Q2 1Q3 1Q4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * There are 2 4-bit latches in the real 74100 IC. However, the model here is * designed with only 1 4-bit latch. In case of 8-bit latches needed, please use * the SUBCKT twice. U1 dltch(4) DPWR DGND + $D_HI $D_HI 1C + 1D1 1D2 1D3 1D4 + 1Q1 1Q2 1Q3 1Q4 $D_NC $D_NC $D_NC $D_NC + D_100 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_100 ugff ( + twghmn=20ns tsudgmn=20ns + thdgmn=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=16ns + tpdqlhmx=30ns tpdqhlty=14ns + tpdqhlmx=25ns + ) *------------------------------------------------------------------------- * 74H101 And-Or-Gated J-K Negative-Edge-Triggered Flip-Flops with Preset * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/17/89 Update interface and model names .subckt 74H101 PREBAR CLK J1A J1B J2A J2B K1A K1B K2A K2B Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 ao(2,2) DPWR DGND + J1A J1B J2A J2B J1 + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 ao(2,2) DPWR DGND + K1A K1B K2A K2B K1 + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U3 bufa(4) DPWR DGND + K1 J1 CLK PREBAR K11 J11 CLK_BUF PREB + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U4 bufa(2) DPWR DGND + K1 J1 K11 J11 + D_H101_1 IO_H MNTYMXDLY={MNTYMXDLY} U5 inva(4) DPWR DGND + J11 K11 PREB CLK_BUF J11B K11B PRE CLKB + D0_GATE IO_H U6 ao(3,2) DPWR DGND + J11 K11 Q1 $D_HI K11 J11B K + D0_GATE IO_H U7 ao(3,2) DPWR DGND + J11 K11 QB1 $D_HI J11 K11B J + D0_GATE IO_H U8 jkff(1) DPWR DGND + PREB $D_HI CLK_BUF J K QD QBD + D_H101_2 IO_H MNTYMXDLY={MNTYMXDLY} U9 bufa(2) DPWR DGND + QD QBD Q1 QB1 + D_H101_3 IO_H MNTYMXDLY={MNTYMXDLY} U10 bufa(2) DPWR DGND + QD QBD Q2 QB2 + D_H101_1 IO_H MNTYMXDLY={MNTYMXDLY} X1 PRE PREB CLK_BUF CLKB Q2 Q DPWR DGND 101SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 PRE PREB CLK_BUF CLKB QB2 QBAR DPWR DGND 101SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 101SUB P PB C CB IN OUT DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + C IN P OUT1 + D_H101_4 IO_H MNTYMXDLY={MNTYMXDLY} U2 and(3) DPWR DGND + CB IN P OUT2 + D_H101_5 IO_H MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + PB IN OUT3 + D_H101_6 IO_H MNTYMXDLY={MNTYMXDLY} U4 or(3) DPWR DGND + OUT1 OUT2 OUT3 OUT + D_H101_7 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H101_1 ugate ( + tphlmn=3ns tphlmx=3ns + ) .model D_H101_2 ueff ( + twclkhmn=10ns twclklmn=15ns + twpclmn=16ns tsudclkmn=10ns + tpclkqhlty=1ns tpclkqhlmx=1ps + ) .model D_H101_3 ugate ( + tphlty=16ns tphlmx=20ns + tplhty=10ns tplhmx=15ns + ) .model D_H101_4 ugate ( + tphlty=1ns tphlmx=1ps + ) .model D_H101_5 ugate ( + tphlty=9ns tphlmx=15ns + ) .model D_H101_6 ugate ( + tplhty=2ns tplhmx=3ns + tphlty=1ns tphlmx=1ps + ) .model D_H101_7 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=11ns tphlmx=17ns + ) *------------------------------------------------------------------------- * 74H102 And-Gated J-K Negative-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/17/89 Update interface and model names .subckt 74H102 CLK PREBAR CLRBAR J1 J2 J3 K1 K2 K3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 anda(3,2) DPWR DGND + J1 J2 J3 K1 K2 K3 J10 K10 + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 bufa(5) DPWR DGND + K10 J10 CLK PREBAR CLRBAR + K11 J11 CLK_BUF PREB CLRB + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U3 bufa(4) DPWR DGND + K10 J10 QD QBD K11 J11 Q2 QB2 + D_H102_1 IO_H MNTYMXDLY={MNTYMXDLY} U4 inva(5) DPWR DGND + J11 K11 PREB CLRB CLK_BUF + J11B K11B PRE CLR CLKB + D0_GATE IO_H U5 ao(3,2) DPWR DGND + J11 K11 Q1 $D_HI K11 J11B K + D0_GATE IO_H U6 ao(3,2) DPWR DGND + J11 K11 QB1 $D_HI J11 K11B J + D0_GATE IO_H U7 jkff(1) DPWR DGND + PREB CLRB CLK_BUF J K QD QBD + D_H102_2 IO_H MNTYMXDLY={MNTYMXDLY} U8 bufa(2) DPWR DGND + QD QBD Q1 QB1 + D_H102_3 IO_H MNTYMXDLY={MNTYMXDLY} X1 PRE PREB CLR CLRB CLK_BUF CLKB Q2 Q DPWR DGND 102SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 PRE PREB CLR CLRB CLK_BUF CLKB QB2 QBAR DPWR DGND 102SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 102SUB P PB C CB CK CKB IN OUT DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + P C PC + D0_GATE IO_H U2 and(2) DPWR DGND + IN PC INCK + D_H102_4 IO_H MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + IN PC INCKB + D_H102_5 IO_H MNTYMXDLY={MNTYMXDLY} U4 anda(2,2) DPWR DGND + INCK CK INCKB CKB OUT1 OUT2 + D0_GATE IO_H U5 and(2) DPWR DGND + PB IN OUT3 + D_H102_6 IO_H MNTYMXDLY={MNTYMXDLY} U6 or(3) DPWR DGND + OUT1 OUT2 OUT3 OUT + D_H102_7 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H102_1 ugate ( + tphlmn=3ns tphlmx=3ns + ) .model D_H102_2 ueff ( + twclkhmn=10ns twclklmn=15ns + twpclmn=16ns tsudclkmn=10ns + tpclkqhlty=1ns tpclkqhlmx=1ps + ) .model D_H102_3 ugate ( + tphlty=16ns tphlmx=20ns + tplhty=10ns tplhmx=15ns + ) .model D_H102_4 ugate ( + tphlty=1ns tphlmx=1ps + ) .model D_H102_5 ugate ( + tphlty=9ns tphlmx=15ns + ) .model D_H102_6 ugate ( + tplhty=2ns tplhmx=3ns + tphlty=1ns tphlmx=1ps + ) .model D_H102_7 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=11ns tphlmx=17ns + ) *------------------------------------------------------------------------- * 74H103 Dual J-K Negative-Edge-Triggered Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/17/89 Update interface and model names .subckt 74H103 1CLK 1CLRBAR 1J 1K 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(4) DPWR DGND + 1K 1J 1CLK 1CLRBAR K11 J11 CLK_BUF CLRB + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + 1K 1J QD QBD K11 J11 Q2 QB2 + D_H103_1 IO_H MNTYMXDLY={MNTYMXDLY} U3 inva(4) DPWR DGND + J11 K11 CLRB CLK_BUF J11B K11B CLR CLKB + D0_GATE IO_H U4 ao(3,2) DPWR DGND + J11 K11 Q1 $D_HI K11 J11B K + D0_GATE IO_H U5 ao(3,2) DPWR DGND + J11 K11 QB1 $D_HI J11 K11B J + D0_GATE IO_H U6 jkff(1) DPWR DGND + $D_HI CLRB CLK_BUF J K QD QBD + D_H103_2 IO_H MNTYMXDLY={MNTYMXDLY} U7 bufa(2) DPWR DGND + QD QBD Q1 QB1 + D_H103_3 IO_H MNTYMXDLY={MNTYMXDLY} X1 CLR CLRB CLK_BUF CLKB Q2 1Q DPWR DGND 103SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 CLR CLRB CLK_BUF CLKB QB2 1QBAR DPWR DGND 103SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 103SUB P PB C CB IN OUT DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + C IN P OUT1 + D_H103_4 IO_H MNTYMXDLY={MNTYMXDLY} U2 and(3) DPWR DGND + CB IN P OUT2 + D_H103_5 IO_H MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + PB IN OUT3 + D_H103_6 IO_H MNTYMXDLY={MNTYMXDLY} U4 or(3) DPWR DGND + OUT1 OUT2 OUT3 OUT + D_H103_7 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H103_1 ugate ( + tphlmn=3ns tphlmx=3ns + ) .model D_H103_2 ueff ( + twclkhmn=10ns twclklmn=15ns + twpclmn=16ns tsudclkmn=10ns + tpclkqhlty=1ns tpclkqhlmx=1ps + ) .model D_H103_3 ugate ( + tphlty=16ns tphlmx=20ns + tplhty=10ns tplhmx=15ns + ) .model D_H103_4 ugate ( + tphlty=1ns tphlmx=1ps + ) .model D_H103_5 ugate ( + tphlty=9ns tphlmx=15ns + ) .model D_H103_6 ugate ( + tplhty=2ns tplhmx=3ns + tphlty=1ns tphlmx=1ps + ) .model D_H103_7 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=11ns tphlmx=17ns + ) *------------------------------------------------------------------------- * 74104 Gated J-K Master-Slave Flip-Flops * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/18/89 Update interface and model names .subckt 74104 CLK PREBAR CLRBAR JK J1 J2 J3 K1 K2 K3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + CLRBAR PREBAR CLK CLRB PREB CLK_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 anda(4,2) DPWR DGND + J1 J2 J3 JK + K1 K2 K3 JK + J1 K1 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + J1 K1 J11 K11 + D0_GATE IO_LS U4 bufa(2) DPWR DGND + J1 K2 J11 K11 + D_104_1 IO_LS MNTYMXDLY={MNTYMXDLY} U5 inva(3) DPWR DGND + CLK_BUF J11 K11 CLKB J11B K11B + D0_GATE IO_STD U6 ao(3,2) DPWR DGND + J11 K11 QB1 J11 K11B $D_HI J + D0_GATE IO_STD U7 ao(3,2) DPWR DGND + J11 K11 Q1 J11B K11 $D_HI K + D0_GATE IO_STD UE1 jkff(1) DPWR DGND + PREB CLRB CLK_BUF J K Y YB + D_104_2 IO_STD MNTYMXDLY={MNTYMXDLY} UE2 jkff(1) DPWR DGND + PREB CLRB CLKB Y YB QD QBD + D_104_3 IO_STD MNTYMXDLY={MNTYMXDLY} U8 bufa(4) DPWR DGND + QD QD QBD QBD Q1 Q QB1 QBAR + D_104_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_104_1 ugate ( + tplhmn=25ns tplhmx=25ns + ) .model D_104_2 ueff ( + twclklmn=15ns twpclmn=20ns + tsudclkmn=10ns + ) .model D_104_3 ueff ( + twclkhmn=15ns twpclmn=20ns + tppcqlhty=3ns tppcqlhmx=9ns + tppcqhlty=10ns tppcqhlmx=19ns + tpclkqlhty=3ns tpclkqlhmx=9ns + tpclkqhlty=10ns tpclkqhlmx=19ns + ) .model D_104_4 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *------------------------------------------------------------------------- * 74105 Gated J-K Master-Slave Flip-Flops * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/18/89 Update interface and model names .subckt 74105 CLK PREBAR CLRBAR JK J1 J2BAR J3 K1 K2BAR K3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + CLRBAR PREBAR CLK CLRB PREB CLK_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 anda(4,2) DPWR DGND + J1 J2 J3 JK + K1 K2 K3 JK + J1 K1 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + J1 K1 J11 K11 + D0_GATE IO_LS U4 bufa(2) DPWR DGND + J1 K2 J11 K11 + D_105_1 IO_LS MNTYMXDLY={MNTYMXDLY} U5 inva(5) DPWR DGND + CLK_BUF J2BAR K2BAR J11 K11 + CLKB J2 K2 J11B K11B + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + J11 K11 QB1 J11 K11B $D_HI J + D0_GATE IO_STD U7 ao(3,2) DPWR DGND + J11 K11 Q1 J11B K11 $D_HI K + D0_GATE IO_STD UE1 jkff(1) DPWR DGND + PREB CLRB CLK_BUF J K Y YB + D_105_2 IO_STD MNTYMXDLY={MNTYMXDLY} UE2 jkff(1) DPWR DGND + PREB CLRB CLKB Y YB QD QBD + D_105_3 IO_STD MNTYMXDLY={MNTYMXDLY} U8 bufa(4) DPWR DGND + QD QD QBD QBD Q1 Q QB1 QBAR + D_105_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_105_1 ugate ( + tplhmn=25ns tplhmx=25ns + ) .model D_105_2 ueff ( + twclklmn=15ns twpclmn=20ns + tsudclkmn=10ns + ) .model D_105_3 ueff ( + twclkhmn=15ns twpclmn=20ns + tppcqlhty=3ns tppcqlhmx=9ns + tppcqhlty=10ns tppcqhlmx=19ns + tpclkqlhty=3ns tpclkqlhmx=9ns + tpclkqhlty=10ns tpclkqhlmx=19ns + ) .model D_105_4 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *------------------------------------------------------------------------- * 74H106 Dual J-K Negative-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/17/89 Update interface and model names .subckt 74H106 1CLK 1PREBAR 1CLRBAR 1J 1K 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(7) DPWR DGND + 1J 1K K10 J10 1CLK 1PREBAR 1CLRBAR + J10 K10 K11 J11 CLK_BUF PREB CLRB + D0_GATE IO_H IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + K10 J10 QD QBD K11 J11 Q2 QB2 + D_H106_1 IO_H MNTYMXDLY={MNTYMXDLY} U3 inva(5) DPWR DGND + J11 K11 PREB CLRB CLK_BUF + J11B K11B PRE CLR CLKB + D0_GATE IO_H U4 ao(3,2) DPWR DGND + J11 K11 Q1 $D_HI K11 J11B K + D0_GATE IO_H U5 ao(3,2) DPWR DGND + J11 K11 QB1 $D_HI J11 K11B J + D0_GATE IO_H U6 jkff(1) DPWR DGND + PREB CLRB CLK_BUF J K QD QBD + D_H106_2 IO_H MNTYMXDLY={MNTYMXDLY} U7 bufa(2) DPWR DGND + QD QBD Q1 QB1 + D_H106_3 IO_H MNTYMXDLY={MNTYMXDLY} X1 PRE PREB CLR CLRB CLK_BUF CLKB Q2 1Q DPWR DGND 106SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 PRE PREB CLR CLRB CLK_BUF CLKB QB2 1QBAR DPWR DGND 106SUB + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .subckt 106SUB P PB C CB CK CKB IN OUT DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + P C PC + D0_GATE IO_H U2 and(2) DPWR DGND + IN PC INCK + D_H106_4 IO_H MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + IN PC INCKB + D_H106_5 IO_H MNTYMXDLY={MNTYMXDLY} U4 anda(2,2) DPWR DGND + INCK CK INCKB CKB OUT1 OUT2 + D0_GATE IO_H U5 and(2) DPWR DGND + PB IN OUT3 + D_H106_6 IO_H MNTYMXDLY={MNTYMXDLY} U6 or(3) DPWR DGND + OUT1 OUT2 OUT3 OUT + D_H106_7 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_H106_1 ugate ( + tphlmn=3ns tphlmx=3ns + ) .model D_H106_2 ueff ( + twclkhmn=10ns twclklmn=15ns + twpclmn=16ns tsudclkmn=10ns + tpclkqhlty=1ns tpclkqhlmx=1ps + ) .model D_H106_3 ugate ( + tphlty=16ns tphlmx=20ns + tplhty=10ns tplhmx=15ns + ) .model D_H106_4 ugate ( + tphlty=1ns tphlmx=1ps + ) .model D_H106_5 ugate ( + tphlty=9ns tphlmx=15ns + ) .model D_H106_6 ugate ( + tplhty=2ns tplhmx=3ns + tphlty=1ns tphlmx=1ps + ) .model D_H106_7 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=11ns tphlmx=17ns + ) *------------------------------------------------------------------------- * 74107 Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74107 CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + CLRBAR J K CLRBAR_BUF J_BUF K_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2BUF buf DPWR DGND + CLK CLK_BUF + D_107_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLK_BUF W1 W2 Y YB + D_107_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLKBAR Y YB QBUF QBAR_BUF + D_107_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + CLK_BUF J_BUF K_BUF CLKBAR JB KB + D0_GATE IO_STD U4 ao(3,2) DPWR DGND + J_BUF K_BUF QBAR_BUFD J_BUF KB $D_HI W1 + D_107_3 IO_STD MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J_BUF K_BUF QBUFD JB K_BUF $D_HI W2 + D_107_3 IO_STD MNTYMXDLY={MNTYMXDLY} UBUF bufa(4) DPWR DGND + QBUF QBAR_BUF QBUF QBAR_BUF Q QBAR QBUFD QBAR_BUFD + D_107_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_107_1 ugff ( + twghmx=19ns twghty=19ns + twpclmx=47ns twpclty=47ns + ) .model D_107_2 ugff ( + tppcqlhty=10ns tppcqlhmx=19ns + tppcqhlty=19ns tppcqhlmx=34ns + tpgqlhty=10ns tpgqlhmx=19ns + tpgqhlty=19ns tpgqhlmx=34ns + twghmx=20ns twghty=20ns + twpclmx=47ns twpclty=47ns + ) .model D_107_3 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) .model D_107_4 ugate ( + tplhmn=6ns tplhmx=6ns + ) *--------- * 74AC107 Dual J-K Flip-Flops with Clear * * (c) HITACHI AMERICA, 1988 * cv 06/29/90 Update interface and model names .subckt 74AC107 CP CDBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + $D_HI CDBAR CP J K Q QBAR + D_AC107 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC107 ueff ( + tppcqlhmn=1ns tppcqlhty=7.5ns + tppcqlhmx=11ns tppcqhlmn=1ns + tppcqhlty=7.5ns tppcqhlmx=11ns + tpclkqlhmn=1ns tpclkqlhty=7.5ns + tpclkqlhmx=11ns tpclkqhlmn=1ns + tpclkqhlty=8ns tpclkqhlmx=11.5ns + twclkhmx=5ns twclkhty=5ns + twclklmx=5ns twclklty=5ns + twpclmx=5ns twpclty=5ns + tsudclkmx=4.5ns tsudclkty=4.5ns + tsupcclkhmx=0ns tsupcclkhty=0ns + ) *--------- * 74ACT107 Dual J-K Flip-Flops with Clear * * (c) HITACHI AMERICA, 1988 * cv 06/29/90 Update interface and model names .subckt 74ACT107 CP CDBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + $D_HI CDBAR CP J K Q QBAR + D_ACT107 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT107 ueff ( + tppcqlhmn=1ns tppcqlhty=8.5ns + tppcqlhmx=12ns tppcqhlmn=1ns + tppcqhlty=8.5ns tppcqhlmx=12ns + tpclkqlhmn=1ns tpclkqlhty=9.5ns + tpclkqlhmx=13.5ns tpclkqhlmn=1ns + tpclkqhlty=10.5ns tpclkqhlmx=14ns + twclkhmx=8ns twclkhty=8ns + twclklmx=8ns twclklty=8ns + twpclmx=8ns twpclty=8ns + tsudclkmx=8ns tsudclkty=8ns + thdclkmx=1.5ns thdclkty=1.5ns + tsupcclkhmx=3ns tsupcclkhty=3ns + ) *--------- * 74HC107 Dual J-K Flip-Flops with Clear * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/29/89 Update interface and model names .subckt 74HC107 CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + $D_HI CLRBAR CLK J K Q QBAR + D_HC107 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC107 ueff ( + tppcqlhty=25ns tppcqlhmx=39ns + tppcqhlty=25ns tppcqhlmx=39ns + tpclkqlhty=20ns tpclkqlhmx=32ns + tpclkqhlty=20ns tpclkqhlmx=32ns + twclkhmx=20ns twclkhty=20ns + twclklmx=20ns twclklty=20ns + twpclmx=25ns twpclty=25ns + tsudclkmx=25ns tsudclkty=25ns + tsupcclkhmx=25ns tsupcclkhty=25ns + ) *--------- * 74LS107A Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74LS107A CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + $D_HI CLRBAR CLK J K Q QBAR + D_LS107 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS107 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhmn=20ns + twpclmx=20ns twpclmn=20ns + tsudclkmx=20ns tsudclkmn=20ns + thdclkmn=20ns thdclkmx=20ns + ) *------------------------------------------------------------------------- * 74H108 Dual J-K Negative-Edge-Triggered Flip-Flops w/ Preset, Common Clear & Common Clock * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/17/89 Update interface and model names .subckt 74H108 CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + CLK CLRBAR CLKB CLRB + D0_GATE IO_H IO_LEVEL={IO_LEVEL} X1 CLK 1PREBAR CLRB 1J 1K 1Q 1QBAR DPWR DGND 74H106 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 CLK 2PREBAR CLRB 2J 2K 2Q 2QBAR DPWR DGND 74H106 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends *------------------------------------------------------------------------- * 74109 Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/30/89 Update interface and model names .subckt 74109 CLK PREBAR CLRBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + PREBAR CLRBAR J PREBAR_BUF CLRBAR_BUF J_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J_BUF K $D_NC QBAR + D_109_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J_BUF K Q $D_NC + D_109_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + CLK KBAR CLKBAR K + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} .ends .model D_109_1 ueff ( + tppcqlhty=10ns tppcqlhmx=15ns + tppcqhlty=10ns tppcqhlmx=15ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=18ns tpclkqhlmx=28ns + twclkhmx=20ns twclklmx=20ns + twclkhty=20ns twclklty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=10ns tsudclkty=20ns + thdclkmx=6ns thdclkty=6ns + ) .model D_109_2 ueff ( + tppcqlhty=23ns tppcqlhmx=35ns + tppcqhlty=17ns tppcqhlmx=25ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=18ns tpclkqhlmx=28ns + twclkhmx=20ns twclklmx=20ns + twclkhty=20ns twclklty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=10ns tsudclkty=20ns + thdclkmx=6ns thdclkty=6ns + ) *--------- * 74AC109 Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The FACT Data Book, 1987, Fairchild * cv 06/22/90 Created from LS .subckt 74AC109 CP SDBAR CDBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U11 jkff(1) DPWR DGND + SDBAR CDBAR CPBAR J K Q QBAR + D_AC109 IO_AC MNTYMXDLY={MNTYMXDLY} U22 inva(2) DPWR DGND + KBAR CP K CPBAR + D0_GATE IO_AC IO_LEVEL={IO_LEVEL} .ends .model D_AC109 ueff ( + tppcqlhty=6ns tppcqlhmx=10ns + tppcqlhmn=1ns tppcqhlty=7.5ns + tppcqhlmx=10.5ns tppcqhlmn=1ns + tpclkqlhty=6ns tpclkqlhmx=10.5ns + tpclkqlhmn=1ns tpclkqhlty=6ns + tpclkqhlmx=10.5ns tpclkqhlmn=1ns + twclkhmx=3.5ns twclklmx=3.5ns + twclkhty=3.5ns twclklty=3.5ns + twpclmx=3.5ns twpclty=3.5ns + tsudclkmx=5ns tsudclkty=5ns + tsupcclkhmx=0ns tsupcclkhty=0ns + thdclkmx=0.5ns thdclkty=0.5ns + ) *--------- * 74ACT109 Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The FACT Data Book, 1987, Fairchild * cv 06/22/90 Created from LS .subckt 74ACT109 CP SDBAR CDBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U11 jkff(1) DPWR DGND + SDBAR CDBAR CPBAR J K Q QBAR + D_ACT109 IO_ACT MNTYMXDLY={MNTYMXDLY} U22 inva(2) DPWR DGND + KBAR CP K CPBAR + D0_GATE IO_ACT IO_LEVEL={IO_LEVEL} .ends .model D_ACT109 ueff ( + tppcqlhty=5.5ns tppcqlhmx=10.5ns + tppcqlhmn=1ns tppcqhlty=6ns + tppcqhlmx=11.5ns tppcqhlmn=1ns + tpclkqlhty=7ns tpclkqlhmx=13ns + tpclkqlhmn=1ns tpclkqhlty=6ns + tpclkqhlmx=11.5ns tpclkqhlmn=1ns + twclkhmx=6ns twclklmx=6ns + twclkhty=6ns twclklty=6ns + twpclmx=6ns twpclty=6ns + tsudclkmx=2.5ns tsudclkty=2.5ns + tsupcclkhmx=0ns tsupcclkhty=0ns + thdclkmx=2ns thdclkty=2ns + ) *--------- * 74ALS109A Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Set & Reset * * (c) Philips Components, 1989 * cv 08/20/90 Created from LS .subckt 74ALS109A CP SDBAR RDBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + SDBAR RDBAR CPBAR J K Q QBAR + D_ALS109A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + KBAR CP K CPBAR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} .ends .model D_ALS109A ueff ( + tppcqlhmn=1ns tppcqlhmx=8ns + tppcqhlmn=3ns tppcqhlmx=10ns + tpclkqlhmn=3ns tpclkqlhmx=14ns + tpclkqhlmn=3ns tpclkqhlmx=14ns + twclkhmn=6ns twclklmn=6ns + twpclmn=6ns tsudclkmn=6ns + tsupcclkhmn=6ns thdclkmn=0ns + ) *--------- * 74AS109 Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ PreSet & Clear * * (c) National Semiconductor, 1987 * cv 08/20/90 Created from LS .subckt 74AS109 CLK PRBAR CLRBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PRBAR CLRBAR CLKBAR J K Q QBAR + D_AS109 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + KBAR CLK K CLKBAR + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} .ends .model D_AS109 ueff ( + tppcqlhmn=3ns tppcqlhmx=8ns + tppcqhlmn=3.5ns tppcqhlmx=10.5ns + tpclkqlhmn=3.5ns tpclkqlhmx=9ns + tpclkqhlmn=4.5ns tpclkqhlmx=9ns + twclkhmn=4ns twclklmn=5.5ns + twpclmn=4ns tsudclkmn=5.5ns + tsupcclkhmn=2ns thdclkmn=0ns + ) *--------- * 74F109 Dual J-Kbar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The F Logic Data Book, 1987, TI * tdn 06/30/89 Update interface and model names .subckt 74F109 CLK PREBAR CLRBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLKBAR J K Q QBAR + D_F109 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + KBAR CLK K CLKBAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} .ends .model D_F109 ueff ( + tppcqlhmn=2.4ns tppcqlhty=4.8ns + tppcqlhmx=7.1ns tppcqhlmn=2.7ns + tppcqhlty=6.6ns tppcqhlmx=10.5ns + tpclkqlhmn=3ns tpclkqlhty=4.9ns + tpclkqlhmx=7.8ns tpclkqhlmn=3.6ns + tpclkqhlty=5.8ns tpclkqhlmx=9.2ns + twclkhmx=4ns twclklmx=5ns + twclkhty=4ns twclklty=5ns + twpclmx=4ns twpclty=4ns + tsudclkmx=3ns tsudclkty=3ns + tsupcclkhmx=2ns tsupcclkhty=2ns + thdclkmx=1ns thdclkty=1ns + ) *--------- * 74HC109 Dual J-Kbar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 06/30/89 Update interface and model names .subckt 74HC109 CLK PREBAR CLRBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLKBAR J K Q QBAR + D_HC109 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + KBAR CLK K CLKBAR + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} .ends .model D_HC109 ueff ( + tppcqlhty=15ns tppcqlhmx=58ns + tppcqhlty=15ns tppcqhlmx=58ns + tpclkqlhty=15ns tpclkqlhmx=44ns + tpclkqhlty=15ns tpclkqhlmx=44ns + twclkhmx=20ns twclklmx=20ns + twclkhty=20ns twclklty=20ns + twpclmx=25ns twpclty=25ns + tsudclkmx=25ns tsudclkty=25ns + tsupcclkhmx=6ns tsupcclkhty=6ns + ) *--------- * 74HCT109 Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Set & Reset * * (c) Harris Semiconductor, 1989 * cv 08/20/90 Created from LS .subckt 74HCT109 CP SBAR RBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + SBAR RBAR CPBAR JBUF KBUF $D_NC QBAR + D_HCT109_1 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1A jkff(1) DPWR DGND + SBAR RBAR CPBAR JBUF KBUF Q $D_NC + D_HCT109_2 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + KBAR CP K CPBAR + D0_GATE IO_HCT IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + J K JBUF KBUF + D_HCT109_3 IO_HCT MNTYMXDLY={MNTYMXDLY} .ends .model D_HCT109_1 ueff ( + tppcqlhmx=38ns tppcqhlmx=46ns + tpclkqlhmx=50ns tpclkqhlmx=50ns + twclkhmn=23ns twclklmn=23ns + twpclmn=23ns tsudclkmn=23ns + tsupcclkhmn=23ns thdclkmn=3ns + ) .model D_HCT109_2 ueff ( + tppcqlhmx=56ns tppcqhlmx=56ns + tpclkqlhmx=50ns tpclkqhlmx=50ns + twclkhmn=23ns twclklmn=23ns + twpclmn=23ns tsudclkmn=23ns + tsupcclkhmn=23ns thdclkmn=3ns + thdclkmx=3ns + ) .model D_HCT109_3 ugate ( + tplhmn=3ns tplhmx=3ns + tphlmn=3ns tphlmx=3ns + ) *--------- * 74LS109A Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/30/89 Update interface and model names .subckt 74LS109A CLK PREBAR CLRBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + PREBAR CLRBAR J PREBAR_BUF CLRBAR_BUF J_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J1 K1 Q QBAR + D_LS109A_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + CLK KBAR CLKBAR K + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + J_BUF K J1 K1 + D0_GATE IO_LS U4 bufa(2) DPWR DGND + J_BUF K J1 K1 + D_LS109A_2 IO_LS MNTYMXDLY={MNTYMXDLY} .ends .model D_LS109A_1 ueff ( + tppcqlhty=13ns tppcqlhmx=25ns + tppcqhlty=25ns tppcqhlmx=40ns + tpclkqlhty=13ns tpclkqlhmx=25ns + tpclkqhlty=25ns tpclkqhlmx=40ns + twclkhmx=25ns twclklmx=25ns + twclkhmn=25ns twclklmn=25ns + twpclmx=25ns twpclmn=25ns + tsudclkmx=25ns tsudclkmn=25ns + thdclkmx=5ns thdclkmn=5ns + ) .model D_LS109A_2 ugate ( + tplhmn=10ns tplhmx=10ns + ) *--------- * 74S109 Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Set & Reset * * (c) Fairchild Semiconductor Corp., 1978 * cv 08/20/90 Created from LS .subckt 74S109 CP SDBAR CDBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + SDBAR CDBAR CPBAR J K Q QBAR + D_S109 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + KBAR CP K CPBAR + D0_GATE IO_S IO_LEVEL={IO_LEVEL} .ends .model D_S109 ueff ( + tppcqlhmx=6ns tppcqhlmx=12ns + tpclkqlhmx=9ns tpclkqhlmx=11ns + twclkhmn=7ns twclklmn=6.5ns + twpclmn=6ns tsudclkmn=6ns + thdclkmn=0ns + ) *------------------------------------------------------------------------- * 74110 And-Gated J-K Master-Slave Flip-Flops with Data Lockout * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/18/89 Update interface and model names .subckt 74110 CLK PREBAR CLRBAR J1 J2 J3 K1 K2 K3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + PREBAR CLRBAR PREBAR_BUF CLRBAR_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + CLK CLKBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 anda(3,2) DPWR DGND + J1 J2 J3 K1 K2 K3 J K + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J K QI $D_NC + D_110_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 dff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR QI Q QBAR + D_110_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_110_1 ueff ( + tsudclkmn=20ns thdclkmn=5ns + twclkhmn=25ns twclklmn=25ns + twpclmn=25ns + ) .model D_110_2 ueff ( + tppcqlhty=12ns tppcqlhmx=20ns + tsudclkmn=20ns thdclkmn=5ns + tppcqhlty=18ns tppcqhlmx=25ns + tpclkqlhty=20ns tpclkqlhmx=30ns + tpclkqhlty=13ns tpclkqhlmx=20ns + twclkhmn=25ns twpclmn=25ns + ) *------------------------------------------------------------------------- * 74111 Dual J-K Master-Slave Flip-Flops with Data Lockout * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/30/89 Update interface and model names .subckt 74111 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + PREBAR CLRBAR PREBAR_BUF CLRBAR_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UA inv DPWR DGND + CLK CLKBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J K QI $D_NC + D_111_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 dltch(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLK QI Q QBAR + D_111_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_111_1 ueff ( + thdclkty=30ns thdclkmx=30ns + twclkhty=25ns twclkhmx=25ns + twclklty=25ns twclklmx=25ns + twpclty=25ns twpclmx=25ns + ) .model D_111_2 ugff ( + tppcqlhty=12ns tppcqlhmx=18ns + tppcqhlty=21ns tppcqhlmx=30ns + tpgqlhty=12ns tpgqlhmx=17ns + tpgqhlty=20ns tpgqhlmx=30ns + twghmx=25ns twghty=25ns + twpclmx=25ns twpclty=25ns + ) *------------------------------------------------------------------------- * 74AC112 Dual J-K Negative-Edge-Triggered Flip-Flops with Set & Resset * * The Advanced CMOS Logic ICs Data Book, RCA * CV 07/13/90 Created from S .subckt 74AC112 CP SBAR RBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + SBAR RBAR CP J K Q QBAR + D_AC112 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC112 ueff ( + tppcqlhmn=3.2ns tppcqlhmx=11.1ns + tppcqhlmn=3.2ns tppcqhlmx=11.1ns + tpclkqlhmn=2.7ns tpclkqlhmx=9.4ns + tpclkqhlmn=2.7ns tpclkqhlmx=9.4ns + twclkhmn=4.4ns twclklmn=4.4ns + twpclmn=3.9ns tsudclkmn=3.5ns + tsupcclkhmn=2.2ns thdclkmn=0ns + ) *--------- * 74ACT112 Dual J-K Negative-Edge-Triggered Flip-Flops with Set & Resset * * The Advanced CMOS Logic ICs Data Book, RCA * CV 07/13/90 Created from S .subckt 74ACT112 CP SBAR RBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + SBAR RBAR CP J K Q QBAR + D_ACT112 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT112 ueff ( + tppcqlhmn=3.2ns tppcqlhmx=11.1ns + tppcqhlmn=3.2ns tppcqhlmx=11.1ns + tpclkqlhmn=2.7ns tpclkqlhmx=9.4ns + tpclkqhlmn=2.7ns tpclkqhlmx=9.4ns + twclkhmn=4.4ns twclklmn=4.4ns + twpclmn=4.8ns tsudclkmn=3.5ns + tsupcclkhmn=2.2ns thdclkmn=1ns + ) *--------- * 74ALS112A Dual J-K Negative-Edge-Triggered Flip-Flops with Set & Reset * * (c) Philips Components, 1989 * cv 08/20/90 Created from LS .subckt 74ALS112A CP SDBAR RDBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + SDBAR RDBAR CP J K Q QBAR + D_ALS112A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS112A ueff ( + tppcqlhmn=3ns tppcqlhmx=15ns + tppcqhlmn=4ns tppcqhlmx=18ns + tpclkqlhmn=3ns tpclkqlhmx=15ns + tpclkqhlmn=5ns tpclkqhlmx=19ns + twclkhmn=16.5ns twclkhmx=16.5ns + twclklmx=16.5ns twclklmn=16.5ns + twpclmx=10ns twpclmn=10ns + tsudclkmx=22ns tsudclkmn=22ns + tsupcclkhmx=20ns tsupcclkhmn=20ns + thdclkmn=0ns thdclkmx=0ns + ) *--------- * 74F112 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Clear * * The F Logic Data Book, 1987, TI * tdn 07/05/89 Update interface and model names .subckt 74F112 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + J K J_BUF K_BUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UB1 bufa(2) DPWR DGND + J_BUF K_BUF J1 K1 + D_F112_1 IO_F MNTYMXDLY={MNTYMXDLY} UB2 bufa(2) DPWR DGND + J_BUF K_BUF J1 K1 + D0_GATE IO_F U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLK J1 K1 Q QBAR + D_F112_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F112_1 ugate ( + tplhmn=1.5ns tplhmx=1.5ns + ) .model D_F112_2 ueff ( + tppcqlhmn=1.2ns tppcqlhty=4.1ns + tppcqlhmx=7.5ns tppcqhlmn=1.2ns + tppcqhlty=4.1ns tppcqhlmx=7.5ns + tpclkqlhmn=1.2ns tpclkqlhty=4.6ns + tpclkqlhmx=7.5ns tpclkqhlmn=1.2ns + tpclkqhlty=4.6ns tpclkqhlmx=7.5ns + twclkhmx=5ns twclkhty=5ns + twclklmx=5ns twclklty=5ns + twpclmx=5ns twpclty=5ns + tsudclkmx=3.5ns tsudclkty=3.5ns + tsupcclkhmx=5ns tsupcclkhty=5ns + ) *--------- * 74HC112 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Clear * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HC112 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLK J K Q QBAR + D_HC112 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC112 ueff ( + tppcqlhty=16ns tppcqlhmx=41ns + tppcqhlty=16ns tppcqhlmx=41ns + tpclkqlhty=16ns tpclkqlhmx=31ns + tpclkqhlty=16ns tpclkqhlmx=31ns + twclkhmx=25ns twclkhty=25ns + twclklmx=25ns twclklty=25ns + twpclmx=25ns twpclty=25ns + tsudclkmx=25ns tsudclkty=25ns + tsupcclkhmx=25ns tsupcclkhty=25ns + ) *--------- * 74HCT112 Dual J-K Negative-Edge-Triggered Flip-Flops with Set & Reset * * (c) Harris Semiconductor, 1989 * cv 08/20/90 Created from LS .subckt 74HCT112 CP SBAR RBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + SBAR RBAR CP J K $D_NC QBAR + D_HCT112_1 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + SBAR RBAR CP J K Q $D_NC + D_HCT112_2 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HCT112_1 ueff ( + tppcqlhmx=40ns tppcqhlmx=40ns + tpclkqlhmx=44ns tpclkqhlmx=44ns + twclkhmn=20ns twclklmn=20ns + twpclmn=23ns tsudclkmn=20ns + tsupcclkhmn=25ns thdclkmn=3ns + ) .model D_HCT112_2 ueff ( + tppcqlhmx=46ns tppcqhlmx=46ns + tpclkqlhmx=44ns tpclkqhlmx=44ns + twclkhmn=20ns twclklmn=20ns + twpclmn=23ns tsudclkmn=20ns + tsupcclkhmn=25ns thdclkmn=3ns + ) *--------- * 74LS112 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names * muw 03/13/90 Correct timing - Data book has LS and S timing reversed .subckt 74LS112A CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * NOTE: Spec allows tsu pre-clk to be 20ns, this model requires 25ns, the same as tsu clr-clk U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLK J K Q QBAR + D_LS112 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS112 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=25ns twpclty=25ns + tsudclkmx=20ns tsudclkty=20ns + tsupcclkhmx=25ns tsupcclkhty=25ns + ) *--------- * 74S112 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names * muw 03/13/90 Correct timing - Data book has LS and S timing reversed .subckt 74S112 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLK J K Q QBAR + D_S112 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S112 ueff ( + tppcqlhty=4ns tppcqlhmx=7ns + tppcqhlty=5ns tppcqhlmx=7ns + tpclkqlhty=4ns tpclkqlhmx=7ns + tpclkqhlty=5ns tpclkqhlmx=7ns + twclkhmx=6ns twclkhty=6ns + twclklmx=6.5ns twclklty=6.5ns + twpclmx=8ns twpclty=8ns + tsudclkmx=3ns tsudclkty=3ns + ) *------------------------------------------------------------------------- * 74F113 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset * * The F Logic Data Book, 1987, TI * tdn 07/05/89 Update interface and model names .subckt 74F113 CLK PREBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR $D_HI CLK J K Q QBAR + D_F113 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F113 ueff ( + tppcqlhmn=1.2ns tppcqlhty=4.1ns + tppcqlhmx=7.5ns tppcqhlmn=1.2ns + tppcqhlty=4.1ns tppcqhlmx=7.5ns + tpclkqlhmn=1.2ns tpclkqlhty=3.6ns + tpclkqlhmx=7ns tpclkqhlmn=1.2ns + tpclkqhlty=3.6ns tpclkqhlmx=7ns + twclkhmx=5ns twclkhty=5ns + twclklmx=5ns twclklty=5ns + twpclmx=5ns twpclty=5ns + tsudclkmx=5ns tsudclkmn=5ns + tsupcclkhmx=5ns tsupcclkhmn=5ns + ) *--------- * 74HC113 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HC113 CLK PREBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR $D_HI CLK J K Q QBAR + D_HC113 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC113 ueff ( + tppcqlhty=18ns tppcqlhmx=41ns + tppcqhlty=18ns tppcqhlmx=41ns + tpclkqlhty=19ns tpclkqlhmx=35ns + tpclkqhlty=19ns tpclkqhlmx=35ns + twclkhmx=20ns twclkhty=20ns + twclklmx=20ns twclklty=20ns + twpclmx=25ns twpclty=25ns + tsudclkmx=25ns tsudclkmn=25ns + tsupcclkhmx=6ns tsupcclkhmn=6ns + ) *--------- * 74LS113A Dual J-K Negative-Edge-Triggered Flip-Flops with Preset * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74LS113A CLK PREBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR $D_HI CLK J K Q QBAR + D_LS113 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS113 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=25ns twpclty=25ns + tsudclkmx=20ns tsudclkmn=20ns + tsupcclkhmx=20ns tsupcclkhmn=20ns + ) *--------- * 74S113 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74S113 CLK PREBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR $D_HI CLK J K Q QBAR + D_S113 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S113 ueff ( + tppcqlhty=4ns tppcqlhmx=7ns + tppcqhlty=5ns tppcqhlmx=7ns + tpclkqlhty=4ns tpclkqlhmx=7ns + tpclkqhlty=5ns tpclkqhlmx=7ns + twclkhmx=6ns twclkhty=6ns + twclklmx=6.5ns twclklty=6.5ns + twpclmx=8ns twpclty=8ns + tsudclkmx=3ns tsudclkmn=3ns + ) *------------------------------------------------------------------------- * 74F114 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset * & Common Clear, & Common Clock * * The F Logic Data Book, 1987, TI * tdn 07/05/89 Update interface and model names .subckt 74F114 CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + CLK CLRBAR 1PREBAR 2PREBAR CLK_BUF CLRBAR_BUF 1PREB 2PREB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + 1PREB CLRBAR_BUF CLK_BUF 1J 1K 1Q 1QBAR + D_F114 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + 2PREB CLRBAR_BUF CLK_BUF 2J 2K 2Q 2QBAR + D_F114 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F114 ueff ( + tppcqlhmn=2.2ns tppcqlhty=4.1ns + tppcqlhmx=7.5ns tppcqhlmn=2.2ns + tppcqhlty=4.1ns tppcqhlmx=7.5ns + tpclkqlhmn=2.2ns tpclkqlhty=4.6ns + tpclkqlhmx=7.5ns tpclkqhlmn=2.2ns + tpclkqhlty=5.1ns tpclkqhlmx=8.5ns + twclkhmx=5ns twclkhty=5ns + twclklmx=5ns twclklty=5ns + twpclmx=5ns twpclty=5ns + tsudclkmx=5ns tsudclkty=5ns + tsupcclkhmx=5ns tsupcclkhty=5ns + ) *--------- * 74HC114 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Common Clear, & Common Clock * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HC114 CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + CLK CLRBAR 1PREBAR 2PREBAR CLK_BUF CLRBAR_BUF 1PREB 2PREB + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + 1PREB CLRBAR_BUF CLK_BUF 1J 1K 1Q 1QBAR + D_HC114 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + 2PREB CLRBAR_BUF CLK_BUF 2J 2K 2Q 2QBAR + D_HC114 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC114 ueff ( + tppcqlhty=20ns tppcqlhmx=44ns + tppcqhlty=20ns tppcqhlmx=44ns + tpclkqlhty=19ns tpclkqlhmx=44ns + tpclkqhlty=19ns tpclkqhlmx=44ns + twclkhmx=25ns twclkhty=25ns + twclklmx=25ns twclklty=25ns + twpclmx=25ns twpclty=25ns + tsudclkmx=25ns tsudclkty=25ns + tsupcclkhmx=25ns tsupcclkhty=25ns + ) *--------- * 74LS114 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Common Clear, & Common Clock * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74LS114A CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + CLK CLRBAR 1PREBAR 2PREBAR CLK_BUF CLRBAR_BUF 1PREB 2PREB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + 1PREB CLRBAR_BUF CLK_BUF 1J 1K 1Q 1QBAR + D_LS114 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + 2PREB CLRBAR_BUF CLK_BUF 2J 2K 2Q 2QBAR + D_LS114 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS114 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=25ns twpclty=25ns + tsudclkmx=20ns tsudclkty=20ns + tsupcclkhty=25ns tsupcclkhmx=25ns + ) *--------- * 74S114 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Common Clear, & Common Clock * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74S114 CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + CLK CLRBAR 1PREBAR 2PREBAR CLK_BUF CLRBAR_BUF 1PREB 2PREB + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + 1PREB CLRBAR_BUF CLK_BUF 1J 1K 1Q 1QBAR + D_S114 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + 2PREB CLRBAR_BUF CLK_BUF 2J 2K 2Q 2QBAR + D_S114 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S114 ueff ( + tppcqlhty=4ns tppcqlhmx=7ns + tppcqhlty=5ns tppcqhlmx=7ns + tpclkqlhty=4ns tpclkqlhmx=7ns + tpclkqhlty=5ns tpclkqhlmx=7ns + twclkhmx=6ns twclkhty=6ns + twpclmx=6.5ns twpclty=6.5ns + tsudclkmx=3ns tsudclkty=3ns + ) *------------------------------------------------------------------------- * 74120 Dual Pulse Synchronizers/Drivers * * The TTL Data Book, Vol 2, 1985, TI * atl 9/21/89 Update interface and model names .subckt 74120 1M 1S1BAR 1S2BAR 1RBAR 1C 1Y 1YBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(5) DPWR DGND + 1M 1S1BAR 1S2BAR 1RBAR 1C + M S1B S2B RB C + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UINV inv DPWR DGND + C CB + D0_GATE IO_STD USUP1 suhdck(3) DPWR DGND + C + S1B S2B RB + SU1 SU2 SU3 HD1 HD2 HD3 + D_120_1 IO_STD MNTYMXDLY={MNTYMXDLY} UX1 buf DPWR DGND + M MBF + D_120_2 IO_STD MNTYMXDLY={MNTYMXDLY} UX2 xor DPWR DGND + M MBF CHK + D0_GATE IO_STD UX3 dff(1) DPWR DGND + $D_HI $D_HI C CHK SUH1 $D_NC + D_120_3 IO_STD MNTYMXDLY={MNTYMXDLY} UOEX or(7) DPWR DGND + SU1 SU2 SU3 HD1 HD2 HD3 SUH1 OEX + D_120_4 IO_STD MNTYMXDLY={MNTYMXDLY} UCTRL nanda(3,2) DPWR DGND + $D_HI RB CT2 CT1 S1B S2B CT1 CT2 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UT nanda(3,4) DPWR DGND + CB CT2 T3 + CT2 T3 C0 + C0 $D_HI C + CT2 1M C1 + T0 T1 T2 T3 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UC nanda(3,2) DPWR DGND + T0 T1 T2 T2 T3 $D_HI C0 C1 + D_120_5 IO_STD MNTYMXDLY={MNTYMXDLY} * Note: IO_LS is used here to assure that indetermined state occurs * whenever set-up or hold time conditions are violated. UT2X1 buf DPWR DGND + T2 T2X + D0_GATE IO_LS UT2X2 buf3 DPWR DGND + $D_X OEX T2X + D0_TGATE IO_LS UY inv DPWR DGND + T2X 1Y + D_120_6 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UYB buf DPWR DGND + T2X 1YBAR + D_120_7 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_120_1 usuhd ( + tsumn=12ns thdmn=3ns + ) .model D_120_2 ugate ( + tphlmn=11.9ns + ) .model D_120_3 ueff ( + thdclkmn=20ns + ) .model D_120_4 ugate ( + tplhmn=0.1ns + ) .model D_120_5 ugate ( + tplhmn=0.1ns tphlmn=0.1ns + ) .model D_120_6 ugate ( + tplhty=14ns tplhmx=22ns + tphlty=17ns tphlmx=25ns + ) .model D_120_7 ugate ( + tplhty=10ns tplhmx=16ns + tphlty=8ns tphlmx=13ns + ) *------------------------------------------------------------------------- * 74121 Non-retriggerable Monostable Multivibrator w/Schmitt-Trigger Inputs * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * * Notes: * 1. Instead of Rext and Cext connections, this model uses a simple PULSE * width parameter to define the output pulse width tw(out). You can * specify this value in the subcircuit call, e.g. PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (50ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. .subckt 74121 A1 A2 B Q Qbar + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=30ns IO_LEVEL=0 MNTYMXDLY=0 * UA nand(2) DPWR DGND + A1 A2 A + D0_GATE IO_STD_ST IO_LEVEL={IO_LEVEL} UAdly dlyline DPWR DGND + A A_dly + D_121_A_dly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigger nand(2) DPWR DGND + A_dly B Trigger + D0_GATE IO_STD_ST IO_LEVEL={IO_LEVEL} UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0S 0 + 1NS Z * UOutputs jkff(1) DPWR DGND + $D_HI Clear Trigger $D_HI $D_LO Q_ Q_Bar + D_121_Outputs IO_STD MNTYMXDLY={MNTYMXDLY} * UQ_Buf buf DPWR DGND + Q_ Q_Buf + D0_GATE IO_STD UQx isx(1) DPWR DGND + q_ q_x + D0_GATE IO_STD UQ0 is0(1) DPWR DGND + q_ q_0 + D0_GATE IO_STD UQ0_Bar inv DPWR DGND + q_0 q0_bar + D0_GATE IO_STD UQ_Rise or(2) DPWR DGND + Q_Buf q_x q_rise + D0_GATE IO_STD UTrigdly dlyline DPWR DGND + Trigger trigdly + D_121_trigdly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_STD UTrigx_bar inv DPWR DGND + trigx trigx_fall + D0_GATE IO_STD UReset0 nand(2) DPWR DGND + q_rise trigx_fall reset0 + D0_GATE IO_STD UClear jkff(1) dpwr dgnd + q0_bar $d_hi reset0 $d_lo $d_hi Clear $d_nc + D_121_pulse IO_STD MNTYMXDLY={MNTYMXDLY} * * Output buffers * UQ inv DPWR DGND + q_bar Q + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UQBar buf DPWR DGND + q_bar QBAR + D_121_Qbar IO_STD IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_121_pulse ueff( + tpclkqhlmn={pulse} tpclkqhlty={pulse} tpclkqhlmx={pulse} + ) .ends 74121 .model D_121_Outputs ueff ( + twclklty=35ns twclklmx=55ns + tpclkqlhty=35ns tpclkqlhmx=55ns + tpclkqhlty=35ns tpclkqhlmx=55ns + ) .model D_121_A_dly udly ( + dlyty=10ns dlymx=15ns + ) .model D_121_trigdly udly ( + dlyty=35ns dlymx=55ns + ) .model D_121_Qbar ugate ( + tplhty=5ns tplhmx=10ns + tphlty=5ns tphlmx=10ns + ) *--------- * 54L121 Non-retriggerable Monostable Multivibrator w/Schmitt-Trigger Inputs * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * * Notes: * 1. Instead of Rext and Cext connections, this model uses a simple PULSE * width parameter to define the output pulse width tw(out). You can * specify this value in the subcircuit call, e.g. PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (100ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. .subckt 54L121 A1 A2 B Q Qbar + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=35ns IO_LEVEL=0 MNTYMXDLY=0 * UA nand(2) DPWR DGND + A1 A2 A + D0_GATE IO_L_ST IO_LEVEL={IO_LEVEL} UAdly dlyline DPWR DGND + A A_dly + D_54L121_A_dly IO_L MNTYMXDLY={MNTYMXDLY} UTrigger nand(2) DPWR DGND + A_dly B Trigger + D0_GATE IO_L_ST IO_LEVEL={IO_LEVEL} UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0S 0 + 1NS Z * UOutputs jkff(1) DPWR DGND + $D_HI Clear Trigger $D_HI $D_LO Q_ Q_Bar + D_54L121_Outputs IO_L MNTYMXDLY={MNTYMXDLY} * UQ_Buf buf DPWR DGND + Q_ Q_Buf + D0_GATE IO_L UQx isx(1) DPWR DGND + q_ q_x + D0_GATE IO_L UQ0 is0(1) DPWR DGND + q_ q_0 + D0_GATE IO_L UQ0_Bar inv DPWR DGND + q_0 q0_bar + D0_GATE IO_L UQ_Rise or(2) DPWR DGND + Q_Buf q_x q_rise + D0_GATE IO_L UTrigdly dlyline DPWR DGND + Trigger trigdly + D_54L121_trigdly IO_L MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_L UTrigx_bar inv DPWR DGND + trigx trigx_fall + D0_GATE IO_L UReset0 nand(2) DPWR DGND + q_rise trigx_fall reset0 + D0_GATE IO_L UClear jkff(1) dpwr dgnd + q0_bar $d_hi reset0 $d_lo $d_hi Clear $d_nc + D_54L121_pulse IO_L MNTYMXDLY={MNTYMXDLY} * * Output buffers * UQ inv DPWR DGND + q_bar Q + D0_GATE IO_L IO_LEVEL={IO_LEVEL} UQBar buf DPWR DGND + q_bar Qbar + D_54L121_Qbar IO_L IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_54L121_pulse ueff( + tpclkqhlmn={pulse} tpclkqhlty={pulse} tpclkqhlmx={pulse} + ) .ends 54L121 .model D_54L121_Outputs ueff ( + twclklmx=110ns + tpclkqlhmx=110ns + tpclkqhlmx=110ns + ) .model D_54L121_A_dly udly ( + dlymx=30ns + ) .model D_54L121_trigdly udly ( + dlymx=110ns + ) .model D_54L121_Qbar ugate ( + tplhmx=20ns + tphlmx=20ns + ) *------------------------------------------------------------------------- * 74122 Retriggerable Monostable Multivibrator * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * * Notes: * 1. Instead of Rext and Cext connections, this model uses a simple PULSE * width parameter to define the output pulse width tw(out). You can * specify this value in the subcircuit call, e.g. PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (40ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. * 3. Some prop delays are off by a few nanoseconds. .subckt 74122 CLRBAR A1 A2 B1 B2 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=45ns IO_LEVEL=0 MNTYMXDLY=0 * UA nand(2) DPWR DGND + A1 A2 A + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UAdly dlyline DPWR DGND + A A_dly + D_122_A_dly IO_STD MNTYMXDLY={MNTYMXDLY} * UTrigger and(3) DPWR DGND + A_dly B1 B2 Trigger + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} * UTrigBar inv DPWR DGND + Trigger Trig_Bar + D0_GATE IO_STD UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0ns 0 + 1ns Z UClear and(2) DPWR DGND + CLRBAR Reset Clear + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UOutputs jkff(1) DPWR DGND + $D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR + D_122_Outputs IO_STD IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigdly dlyline DPWR DGND + Trigger trigdly + D_122_trigdly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_STD UTrigx_bar inv DPWR DGND + trigx trigx_bar + D0_GATE IO_STD UTrigx_barbar inv DPWR DGND + trigx_bar trigx_barbar + D_122_tedge IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx_fall and(2) DPWR DGND + trigx_barbar trigx_bar trigx_fall + D0_GATE IO_STD UReset0 nor(2) DPWR DGND + trigdly trigx_fall reset0 + D0_GATE IO_STD UTrig0 is0(1) DPWR DGND + Trigger Trig_0 + D0_GATE IO_STD UTrig0_Bar inv DPWR DGND + Trig_0 Trig0_Bar + D_122_edge IO_STD MNTYMXDLY={MNTYMXDLY} UTrigPreset or(2) DPWR DGND + Trig_0 Trig0_Bar TrigPreset + D0_GATE IO_STD UReset jkff(1) DPWR DGND + TrigPreset $d_hi reset0 $d_lo $d_hi reset $d_nc + D_122_pulse IO_STD MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_122_pulse ueff( + tpclkqhlmn={pulse-1ns+1ns} + tpclkqhlty={pulse-1ns+1ns} ;-1 for trigdly, +1=tp(trig)-tp(reset) + tpclkqhlmx={pulse-1ns+1ns} + ) .ends 74122 .model D_122_A_dly udly ( + dlyty=3ns dlymx=5ns + ) .model D_122_Outputs ueff ( + twclklty=19ns twclklmx=28ns + tpclkqlhty=19ns tpclkqlhmx=28ns + tpclkqhlty=27ns tpclkqhlmx=36ns + tppcqhlty=18ns tppcqhlmx=27ns + tppcqlhty=26ns tppcqlhmx=35ns + ) .model D_122_trigdly udly ( + dlymn=1ns dlyty=1ns dlymx=1ns + ) .model D_122_edge ugate( + tplhmn=1ns tplhty=1ns tplhmx=1ns + ) .model D_122_tedge ugate( + tphlmn=1ns tphlty=1ns tphlmx=1ns + ) *--------- * 54L122 Retriggerable Monostable Multivibrator * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * * Notes: * 1. Instead of Rext and Cext connections, this model uses a simple PULSE * width parameter to define the output pulse width tw(out). You can * specify this value in the subcircuit call, e.g. PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (50ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. * 3. Some prop delays are off by a few nanoseconds. .subckt 54L122 CLRBAR A1 A2 B1 B2 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=90ns IO_LEVEL=0 MNTYMXDLY=0 * UA nand(2) DPWR DGND + A1 A2 A + D0_GATE IO_L IO_LEVEL={IO_LEVEL} UAdly dlyline DPWR DGND + A A_dly + D_54L122_A_dly IO_L MNTYMXDLY={MNTYMXDLY} * UTrigger and(3) DPWR DGND + A_dly B1 B2 Trigger + D0_GATE IO_L IO_LEVEL={IO_LEVEL} * UTrigBar inv DPWR DGND + Trigger Trig_Bar + D0_GATE IO_L UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0ns 0 + 1ns Z UClear and(2) DPWR DGND + CLRBAR Reset Clear + D0_GATE IO_L IO_LEVEL={IO_LEVEL} UOutputs jkff(1) DPWR DGND + $D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR + D_54L122_Outputs IO_L IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigdly dlyline DPWR DGND + Trigger trigdly + D_54L122_trigdly IO_L MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_L UTrigx_bar inv DPWR DGND + trigx trigx_bar + D0_GATE IO_L UTrigx_barbar inv DPWR DGND + trigx_bar trigx_barbar + D_54L122_tedge IO_L MNTYMXDLY={MNTYMXDLY} UTrigx_fall and(2) DPWR DGND + trigx_barbar trigx_bar trigx_fall + D0_GATE IO_L UReset0 nor(2) DPWR DGND + trigdly trigx_fall reset0 + D0_GATE IO_L UTrig0 is0(1) DPWR DGND + Trigger Trig_0 + D0_GATE IO_L UTrig0_Bar inv DPWR DGND + Trig_0 Trig0_Bar + D_54L122_edge IO_L MNTYMXDLY={MNTYMXDLY} UTrigPreset or(2) DPWR DGND + Trig_0 Trig0_Bar TrigPreset + D0_GATE IO_L UReset jkff(1) DPWR DGND + TrigPreset $d_hi reset0 $d_lo $d_hi reset $d_nc + D_54L122_pulse IO_L MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_54L122_pulse ueff( + tpclkqhlmn={pulse-1ns+2ns} + tpclkqhlty={pulse-1ns+2ns} + tpclkqhlmx={pulse-1ns+2ns} + ) .ends 54L122 .model D_54L122_A_dly udly ( + dlyty=6ns dlymx=10ns + ) .model D_54L122_Outputs ueff ( + twclklty=38ns twclklmx=56ns + tpclkqlhty=38ns tpclkqlhmx=56ns + tpclkqhlty=54ns tpclkqhlmx=72ns + tppcqhlty=36ns tppcqhlmx=54ns + tppcqlhty=52ns tppcqlhmx=70ns + ) .model D_54L122_trigdly udly ( + dlymn=1ns dlyty=1ns dlymx=1ns + ) .model D_54L122_edge ugate( + tplhmn=1ns tplhty=1ns tplhmx=1ns + ) .model D_54L122_tedge ugate( + tphlmn=1ns tphlty=1ns tphlmx=1ns + ) *--------- * 74LS122 Retriggerable Monostable Multivibrator * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * * Notes: * 1. Instead of Rext and Cext connections, this model uses a simple PULSE * width parameter to define the output pulse width tw(out). You can * specify this value in the subcircuit call, e.g. PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (40ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. * 3. Some prop delays are off by a few nanoseconds. .subckt 74LS122 CLRBAR A1 A2 B1 B2 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=116ns IO_LEVEL=0 MNTYMXDLY=0 UA nand(2) DPWR DGND + A1 A2 A + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} UB1_dly dlyline DPWR DGND + B1 B1_dly + D_LS122_B_dly IO_LS_ST IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} UB2_dly dlyline DPWR DGND + B2 B2_dly + D_LS122_B_dly IO_LS_ST IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigger and(3) DPWR DGND + A B1_dly B2_dly Trigger + D0_GATE IO_LS * UTrigBar inv DPWR DGND + Trigger Trig_Bar + D0_GATE IO_LS UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0ns 0 + 1ns Z UClear and(2) DPWR DGND + CLRBAR Reset Clear + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UOutputs jkff(1) DPWR DGND + $D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR + D_LS122_Outputs IO_LS IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigdly dlyline DPWR DGND + Trigger trigdly + D_LS122_trigdly IO_LS MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_LS UTrigx_bar inv DPWR DGND + trigx trigx_bar + D0_GATE IO_LS UTrigx_barbar inv DPWR DGND + trigx_bar trigx_barbar + D_LS122_tedge IO_LS MNTYMXDLY={MNTYMXDLY} UTrigx_fall and(2) DPWR DGND + trigx_barbar trigx_bar trigx_fall + D0_GATE IO_LS UReset0 nor(2) DPWR DGND + trigdly trigx_fall reset0 + D0_GATE IO_LS UTrig0 is0(1) DPWR DGND + Trigger Trig_0 + D0_GATE IO_LS UTrig0_Bar inv DPWR DGND + Trig_0 Trig0_Bar + D_LS122_edge IO_LS MNTYMXDLY={MNTYMXDLY} UTrigPreset or(2) DPWR DGND + Trig_0 Trig0_Bar TrigPreset + D0_GATE IO_LS UReset jkff(1) DPWR DGND + TrigPreset $d_hi reset0 $d_lo $d_hi reset $d_nc + D_LS122_pulse IO_LS MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_LS122_pulse ueff( + tpclkqhlmn={pulse-1ns+1ns} + tpclkqhlty={pulse-1ns+3ns} + tpclkqhlmx={pulse-1ns+6ns} + ) .ends 74LS122 .model D_LS122_B_dly udly ( + dlyty=1ns dlymx=11ns + ) .model D_LS122_Outputs ueff ( + twclklty=23ns twclklmx=33ns + tpclkqlhty=23ns tpclkqlhmx=33ns + tpclkqhlty=32ns tpclkqhlmx=45ns + tppcqhlty=20ns tppcqhlmx=27ns + tppcqlhty=29ns tppcqlhmx=39ns + ) .model D_LS122_trigdly udly ( + dlymn=1ns dlyty=1ns dlymx=1ns + ) .model D_LS122_edge ugate( + tplhmn=1ns tplhty=1ns tplhmx=1ns + ) .model D_LS122_tedge ugate( + tphlmn=1ns tphlty=1ns tphlmx=1ns + ) *------------------------------------------------------------------------- * 74123 Retriggerable Monostable Multivibrator * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * * Notes: * 1. Instead of Rext and Cext connections, this model uses a simple PULSE * width parameter to define the output pulse width tw(out). You can * specify this value in the subcircuit call, e.g. PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (40ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. * 3. Some prop delays are off by a few nanoseconds. .subckt 74123 CLRBAR A B Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=45ns IO_LEVEL=0 MNTYMXDLY=0 * UABar inv DPWR DGND + A ABar + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UAdly dlyline DPWR DGND + ABar A_dly + D_123_A_dly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigger and(2) DPWR DGND + A_dly B Trigger + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} * UTrigBar inv DPWR DGND + Trigger Trig_Bar + D0_GATE IO_STD UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0ns 0 + 1ns Z UClear and(2) DPWR DGND + CLRBAR Reset Clear + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UOutputs jkff(1) DPWR DGND + $D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR + D_123_Outputs IO_STD IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigdly dlyline DPWR DGND + Trigger trigdly + D_123_trigdly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_STD UTrigx_bar inv DPWR DGND + trigx trigx_bar + D0_GATE IO_STD UTrigx_barbar inv DPWR DGND + trigx_bar trigx_barbar + D_123_tedge IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx_fall and(2) DPWR DGND + trigx_barbar trigx_bar trigx_fall + D0_GATE IO_STD UReset0 nor(2) DPWR DGND + trigdly trigx_fall reset0 + D0_GATE IO_STD UTrig0 is0(1) DPWR DGND + Trigger Trig_0 + D0_GATE IO_STD UTrig0_Bar inv DPWR DGND + Trig_0 Trig0_Bar + D_123_edge IO_STD MNTYMXDLY={MNTYMXDLY} UTrigPreset or(2) DPWR DGND + Trig_0 Trig0_Bar TrigPreset + D0_GATE IO_STD UReset jkff(1) DPWR DGND + TrigPreset $d_hi reset0 $d_lo $d_hi reset $d_nc + D_123_pulse IO_STD MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_123_pulse ueff( + tpclkqhlmn={pulse-1ns+1ns} + tpclkqhlty={pulse-1ns+1ns} ;-1 for trigdly, +1=tp(trig)-tp(reset) + tpclkqhlmx={pulse-1ns+1ns} + ) + ) .ends 74123 .model D_123_A_dly udly ( + dlyty=3ns dlymx=5ns + ) .model D_123_Outputs ueff ( + twclklty=19ns twclklmx=28ns + tpclkqlhty=19ns tpclkqlhmx=28ns + tpclkqhlty=27ns tpclkqhlmx=36ns + tppcqhlty=18ns tppcqhlmx=27ns + tppcqlhty=26ns tppcqlhmx=35ns + ) .model D_123_trigdly udly ( + dlymn=1ns dlyty=1ns dlymx=1ns + ) .model D_123_edge ugate( + tplhmn=1ns tplhty=1ns tplhmx=1ns + ) .model D_123_tedge ugate( + tphlmn=1ns tphlty=1ns tphlmx=1ns + ) *--------- * 54L123 Retriggerable Monostable Multivibrator * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * * Notes: * 1. Instead of Rext and Cext connections, this model uses a simple PULSE * width parameter to define the output pulse width tw(out). You can * specify this value in the subcircuit call, e.g. PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (50ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. * 3. Some prop delays are off by a few nanoseconds. .subckt 54L123 CLRBAR A B Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=90ns IO_LEVEL=0 MNTYMXDLY=0 UABar inv DPWR DGND + A ABar + D0_GATE IO_L IO_LEVEL={IO_LEVEL} UAdly dlyline DPWR DGND + ABar A_dly + D_54L123_A_dly IO_L MNTYMXDLY={MNTYMXDLY} UTrigger and(2) DPWR DGND + A_dly B Trigger + D0_GATE IO_L IO_LEVEL={IO_LEVEL} * UTrigBar inv DPWR DGND + Trigger Trig_Bar + D0_GATE IO_L UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0ns 0 + 1ns Z UClear and(2) DPWR DGND + CLRBAR Reset Clear + D0_GATE IO_L IO_LEVEL={IO_LEVEL} UOutputs jkff(1) DPWR DGND + $D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR + D_54L123_Outputs IO_L IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigdly dlyline DPWR DGND + Trigger trigdly + D_54L123_trigdly IO_L MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_L UTrigx_bar inv DPWR DGND + trigx trigx_bar + D0_GATE IO_L UTrigx_barbar inv DPWR DGND + trigx_bar trigx_barbar + D_54L123_tedge IO_L MNTYMXDLY={MNTYMXDLY} UTrigx_fall and(2) DPWR DGND + trigx_barbar trigx_bar trigx_fall + D0_GATE IO_L UReset0 nor(2) DPWR DGND + trigdly trigx_fall reset0 + D0_GATE IO_L UTrig0 is0(1) DPWR DGND + Trigger Trig_0 + D0_GATE IO_L UTrig0_Bar inv DPWR DGND + Trig_0 Trig0_Bar + D_54L123_edge IO_L MNTYMXDLY={MNTYMXDLY} UTrigPreset or(2) DPWR DGND + Trig_0 Trig0_Bar TrigPreset + D0_GATE IO_L UReset jkff(1) DPWR DGND + TrigPreset $d_hi reset0 $d_lo $d_hi reset $d_nc + D_54L123_pulse IO_L MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_54L123_pulse ueff( + tpclkqhlmn={pulse-1ns+2ns} + tpclkqhlty={pulse-1ns+2ns} + tpclkqhlmx={pulse-1ns+2ns} + ) .ends 54L123 .model D_54L123_A_dly udly ( + dlyty=6ns dlymx=10ns + ) .model D_54L123_Outputs ueff ( + twclklty=38ns twclklmx=56ns + tpclkqlhty=38ns tpclkqlhmx=56ns + tpclkqhlty=54ns tpclkqhlmx=72ns + tppcqhlty=36ns tppcqhlmx=54ns + tppcqlhty=52ns tppcqlhmx=70ns + ) .model D_54L123_trigdly udly ( + dlymn=1ns dlyty=1ns dlymx=1ns + ) .model D_54L123_edge ugate( + tplhmn=1ns tplhty=1ns tplhmx=1ns + ) .model D_54L123_tedge ugate( + tphlmn=1ns tphlty=1ns tphlmx=1ns + ) *--------- * 74LS123 Retriggerable Monostable Multivibrator * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * * Notes: * 1. Instead of Rext and Cext connections, this model uses a simple PULSE * width parameter to define the output pulse width tw(out). You can * specify this value in the subcircuit call, e.g. PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (40ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. * 3. Some prop delays are off by a few nanoseconds. .subckt 74LS123 CLRBAR A B Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=116ns IO_LEVEL=0 MNTYMXDLY=0 UABar inv DPWR DGND + A ABar + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} UB_dly dlyline DPWR DGND + B B_dly + D_LS123_B_dly IO_LS_ST IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigger and(2) DPWR DGND + ABar B_dly Trigger + D0_GATE IO_LS * UTrigBar inv DPWR DGND + Trigger Trig_Bar + D0_GATE IO_LS UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0ns 0 + 1ns Z UClear and(2) DPWR DGND + CLRBAR Reset Clear + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UOutputs jkff(1) DPWR DGND + $D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR + D_LS123_Outputs IO_LS IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigdly dlyline DPWR DGND + Trigger trigdly + D_LS123_trigdly IO_LS MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_LS UTrigx_bar inv DPWR DGND + trigx trigx_bar + D0_GATE IO_LS UTrigx_barbar inv DPWR DGND + trigx_bar trigx_barbar + D_LS123_tedge IO_LS MNTYMXDLY={MNTYMXDLY} UTrigx_fall and(2) DPWR DGND + trigx_barbar trigx_bar trigx_fall + D0_GATE IO_LS UReset0 nor(2) DPWR DGND + trigdly trigx_fall reset0 + D0_GATE IO_LS UTrig0 is0(1) DPWR DGND + Trigger Trig_0 + D0_GATE IO_LS UTrig0_Bar inv DPWR DGND + Trig_0 Trig0_Bar + D_LS123_edge IO_LS MNTYMXDLY={MNTYMXDLY} UTrigPreset or(2) DPWR DGND + Trig_0 Trig0_Bar TrigPreset + D0_GATE IO_LS UReset jkff(1) DPWR DGND + TrigPreset $d_hi reset0 $d_lo $d_hi reset reset_bar + D_LS123_pulse IO_LS MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_LS123_pulse ueff( + tpclkqhlmn={pulse-1ns+1ns} + tpclkqhlty={pulse-1ns+3ns} + tpclkqhlmx={pulse-1ns+6ns} + ) .ends 74LS123 .model D_LS123_B_dly udly ( + dlyty=1ns dlymx=11ns + ) .model D_LS123_Outputs ueff ( + twclklty=23ns twclklmx=33ns + tpclkqlhty=23ns tpclkqlhmx=33ns + tpclkqhlty=32ns tpclkqhlmx=45ns + tppcqhlty=20ns tppcqhlmx=27ns + tppcqlhty=29ns tppcqlhmx=39ns + ) .model D_LS123_trigdly udly ( + dlymn=1ns dlyty=1ns dlymx=1ns + ) .model D_LS123_edge ugate( + tplhmn=1ns tplhty=1ns tplhmx=1ns + ) .model D_LS123_tedge ugate( + tphlmn=1ns tphlty=1ns tphlmx=1ns + ) *------------------------------------------------------------------------- * 74125 Quadruple Bus Buffer with 3-state Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74125 A GBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_125 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + GBAR G + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} .ends .model D_125 utgate ( + tplhty=8ns tplhmx=13ns + tphlty=12ns tphlmx=18ns + tpzhty=11ns tpzhmx=17ns + tpzlty=16ns tpzlmx=25ns + tphzty=5ns tphzmx=8ns + tplzty=7ns tplzmx=12ns + ) *--------- * 74HC125 Quadruple Bus Buffer with 3-state Outputs * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HC125 A GBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_HC125 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + GBAR G + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} .ends .model D_HC125 utgate ( + tplhty=14ns tplhmx=30ns + tphlty=14ns tphlmx=30ns + tpzhty=14ns tpzhmx=30ns + tpzlty=14ns tpzlmx=30ns + tphzty=15ns tphzmx=30ns + tplzty=15ns tplzmx=30ns + ) *--------- * 74LS125A Quadruple Bus Buffer with 3-state Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74LS125A A GBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_LS125A IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + GBAR G + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} .ends .model D_LS125A utgate ( + tplhty=9ns tplhmx=15ns + tphlty=7ns tphlmx=18ns + tpzhty=12ns tpzhmx=20ns + tpzlty=15ns tpzlmx=25ns + tphzty=20ns tphzmx=20ns + tplzty=20ns tplzmx=20ns + ) *------------------------------------------------------------------------- * 74126 Quadruple Bus Buffer with 3-state Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74126 A G Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_126 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_126 utgate ( + tplhty=8ns tplhmx=13ns + tphlty=12ns tphlmx=18ns + tpzhty=11ns tpzhmx=18ns + tpzlty=16ns tpzlmx=25ns + tphzty=10ns tphzmx=16ns + tplzty=12ns tplzmx=18ns + ) *--------- * 74HC126 Quadruple Bus Buffer with 3-state Outputs * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HC126 A G Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_HC126 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC126 utgate ( + tplhty=14ns tplhmx=30ns + tphlty=14ns tphlmx=30ns + tpzhty=16ns tpzhmx=30ns + tpzlty=16ns tpzlmx=30ns + tphzty=17ns tphzmx=30ns + tplzty=17ns tplzmx=30ns + ) *--------- * 74LS126A Quadruple Bus Buffer with 3-state Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74LS126A A G Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_LS126A IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS126A utgate ( + tplhty=9ns tplhmx=15ns + tphlty=8ns tphlmx=18ns + tpzhty=16ns tpzhmx=25ns + tpzlty=21ns tpzlmx=35ns + tphzty=25ns tphzmx=25ns + tplzty=25ns tplzmx=25ns + ) *------------------------------------------------------------------------- * 74128 Line Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74128 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_128 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_128 ugate ( + tplhty=6ns tplhmx=9ns + tphlty=8ns tphlmx=12ns + ) *------------------------------------------------------------------------- * 74132 Quadruple 2-input Positive-Nand Schmitt Triggers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74132 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled by the AtoD interface. U1 nand(2) DPWR DGND + A B Y + D_132 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_132 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=15ns tphlmx=22ns + ) *--------- * 74HC132 Quadruple 2-input Positive-Nand Schmitt Triggers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HC132 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled by the AtoD interface. U1 nand(2) DPWR DGND + A B Y + D_HC132 IO_HC_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC132 ugate ( + tplhty=18ns tplhmx=31ns + tphlty=18ns tphlmx=31ns + ) *--------- * 74LS132 Quadruple 2-input Positive-Nand Schmitt Triggers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74LS132 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled by the AtoD interface. U1 nand(2) DPWR DGND + A B Y + D_LS132 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS132 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=15ns tphlmx=22ns + ) *--------- * 74S132 Quadruple 2-input Positive-Nand Schmitt Triggers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74S132 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled by the AtoD interface. U1 nand(2) DPWR DGND + A B Y + D_S132 IO_S_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S132 ugate ( + tplhty=7ns tplhmx=10.5ns + tphlty=8.5ns tphlmx=13ns + ) *------------------------------------------------------------------------- * 74ALS133 13-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names .subckt 74ALS133 A B C D E F G H I J K L M Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(13) DPWR DGND + A B C D E F G H I + J K L M + Y + D_ALS133 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS133 ugate ( + tplhty=8ns tphlty=17ns + tplhmn=3ns tplhmx=11ns + tphlmn=5ns tphlmx=25ns + ) *--------- * 74HC133 13-input Positive-Nand Gates * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HC133 A B C D E F G H I J K L M Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(13) DPWR DGND + A B C D E F G H I + J K L M + Y + D_HC133 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC133 ugate ( + tplhty=16ns tplhmx=38ns + tphlty=16ns tphlmx=38ns + ) *--------- * 74S133 13-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74S133 A B C D E F G H I J K L M Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(13) DPWR DGND + A B C D E F G H I + J K L M + Y + D_S133 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S133 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=4.5ns tphlmx=7ns + ) *------------------------------------------------------------------------- * 74S134 12-input Positive-Nand Gates with 3-state Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74S134 A B C D E F G H I J K L OCBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand3(12) DPWR DGND + A B C D E F + G H I J K L + OC + Y + D_S134 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + OCBAR OC + D0_GATE IO_S IO_LEVEL={IO_LEVEL} .ends .model D_S134 utgate ( + tplhty=4ns tplhmx=6ns + tphlty=5ns tphlmx=7.5ns + tpzhty=13ns tpzhmx=19.5ns + tpzlty=14ns tpzlmx=21ns + tphzty=5.5ns tphzmx=8.5ns + tplzty=9ns tplzmx=14ns + ) *------------------------------------------------------------------------- * 74S135 Quadruple Exclusive-Or/Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74S135 1A 1B 2A 2B C 1Y 2Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: The actual 74S135 device contains two independent circuits. This * subcircuit models only one of these. UIBUF bufa(5) DPWR DGND + C 1A 1B 2A 2B + C_BUF 1A_BUF 1B_BUF 2A_BUF 2B_BUF + D0_GATE IO_S IO_LEVEL={IO_LEVEL} X1 1A_BUF 1B_BUF C_BUF 1Y DPWR DGND SECT135 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 2A_BUF 2B_BUF C_BUF 2Y DPWR DGND SECT135 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74S135 .subckt SECT135 A B C Y DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 X1 A B D DPWR DGND GA135S + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 A B G DPWR DGND GB135S + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3 E J Y DPWR DGND GC135S + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + C E + D_S135_1 IO_S MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + E F + D0_GATE IO_S U3 ao(2,2) DPWR DGND + D F E G J + D0_GATE IO_S .ends SECT135 .subckt GA135S A B Y DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B C + D_S135_2 IO_S MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A B D + D_S135_3 IO_S MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_S135_4 IO_S MNTYMXDLY={MNTYMXDLY} .ends GA135S .subckt GB135S A B Y DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B C + D_S135_5 IO_S MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A B D + D_S135_6 IO_S MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_S135_7 IO_S MNTYMXDLY={MNTYMXDLY} .ends GB135S .subckt GC135S A B Y DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B C + D_S135_8 IO_S MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A B D + D_S135_9 IO_S MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_S135_10 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends GC135S .model D_S135_1 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) .model D_S135_2 ugate ( + tplhty=6.5ns tplhmx=7ns + tphlty=2ns tphlmx=1.5ns + ) .model D_S135_3 ugate ( + tplhty=6ns tplhmx=6ns + ) .model D_S135_4 ugate ( + tphlty=5.5ns tphlmx=5ns + ) .model D_S135_5 ugate ( + tplhty=4.5ns tplhmx=4ns + tphlty=1.5ns tphlmx=3ns + ) .model D_S135_6 ugate ( + tplhty=5ns tplhmx=7ns + ) .model D_S135_7 ugate ( + tphlty=7ns tphlmx=6.5ns + ) .model D_S135_8 ugate ( + tplhty=2ns tplhmx=6ns + tphlty=1.5ns tphlmx=2.5ns + ) .model D_S135_9 ugate ( + tplhty=1.5ns tplhmx=5.5ns + ) .model D_S135_10 ugate ( + tphlty=2ns tphlmx=6ns + ) *------------------------------------------------------------------------- * 74136 Quadruple 2-input Exclusive-Or Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74136 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_136_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_136_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_136_3 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74136 .model D_136_1 ugate ( + tplhty=12ns tplhmx=18ns + ) .model D_136_2 ugate ( + tplhty=14ns tplhmx=22ns + tphlty=3ns tphlmx=5ns + ) .model D_136_3 ugate ( + tphlty=39ns tphlmx=50ns + ) *--------- * 74ALS136 Quadruple 2-input Exclusive-Or Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names .subckt 74ALS136 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_ALS136_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_ALS136_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_ALS136_3 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74ALS136 .model D_ALS136_1 ugate ( + tplhmn=18ns tplhmx=48ns + tphlmn=1ns tphlmx=13ns + ) .model D_ALS136_2 ugate ( + tplhmn=18ns tplhmx=48ns + tphlmn=1ns tphlmx=10ns + ) .model D_ALS136_3 ugate ( + tplhmn=2ns tplhmx=2ns + tphlmn=2ns tphlmx=2ns + ) *--------- * 74AS136 Quadruple 2-input Exclusive-Or Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names .subckt 74AS136 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_AS136 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74AS136 .model D_AS136 ugate ( + tplhty=10.5ns tphlty=4.3ns + ) *--------- * 74LS136 Quadruple 2-input Exclusive-Or Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74LS136 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_LS136 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74LS136 .model D_LS136 ugate ( + tplhty=18ns tplhmx=30ns + tphlty=18ns tphlmx=30ns + ) *------------------------------------------------------------------------- * 74ALS137 3-line to 8-line Decoders/Demultiplexers with Address Latches * * The ALS/AS Data Book, 1986, TI * tdn 08/21/89 Update interface and model names .subckt 74ALS137 G1 G2BAR GLBAR A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 inva(4) DPWR DGND + A_BUF B_BUF C_BUF G2BAR A2 B2 C2 G2 + D0_GATE IO_ALS00 U3 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF A1 B1 C1 + D0_GATE IO_ALS00 U4 srff(3) DPWR DGND + $D_HI $D_HI EN1 + A1 B1 C1 A2 B2 C2 + P1 Q1 R1 $D_NC $D_NC $D_NC + D_ALS137_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U5 srff(3) DPWR DGND + $D_HI $D_HI EN1 + A1 B1 C1 A2 B2 C2 + $D_NC $D_NC $D_NC PB QB RB + D_ALS137_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U6 bufa(6) DPWR DGND + P1 Q1 R1 PB QB RB + P Q R PBAR QBAR RBAR + D_ALS137_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U7 buf DPWR DGND + G1 G1B + D_ALS137_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U8 and(2) DPWR DGND + G2 G1B EN2 + D0_GATE IO_ALS00 U9 inv DPWR DGND + GLBAR EN1 + D_ALS137_4 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U10 nanda(4,8) DPWR DGND + PBAR QBAR RBAR EN2 + P QBAR RBAR EN2 + PBAR Q RBAR EN2 + P Q RBAR EN2 + PBAR QBAR R EN2 + P QBAR R EN2 + PBAR Q R EN2 + P Q R EN2 + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_ALS137_5 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS137_1 ugff ( + twghmn=10ns tsudgmn=10ns + thdgmn=5ns tpdqlhmn=1ns + tpdqlhmx=1ps tpdqhlmn=1ns + tpdqhlmx=1ps tpgqlhmn=1ns + tpgqlhmx=8ns tpgqhlmn=2ns + tpgqlhmx=10ns + ) .model D_ALS137_2 ugate ( + tphlmx=8ns tplhmx=5ns + ) .model D_ALS137_3 ugate ( + tphlmn=1ns tphlmx=5ns + ) .model D_ALS137_4 ugate ( + tplhmn=1ns tplhmx=2ns + tphlmn=2ns tphlmx=1ps + ) .model D_ALS137_5 ugate ( + tplhmn=4ns tplhmx=12ns + tphlmn=5ns tphlmx=15ns + ) *--------- * 74AS137 3-line to 8-line Decoders/Demultiplexers with Address Latches * * The ALS/AS Data Book, 1986, TI * tdn 08/21/89 Update interface and model names .subckt 74AS137 G1 G2BAR GLBAR A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U2 inva(4) DPWR DGND + A_BUF B_BUF C_BUF G2BAR A2 B2 C2 G2 + D0_GATE IO_AS00 U3 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF A1 B1 C1 + D0_GATE IO_AS00 U4 srff(3) DPWR DGND + $D_HI $D_HI EN1 + A1 B1 C1 A2 B2 C2 + P1 Q1 R1 PB QB RB + D_AS137_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U5 bufa(6) DPWR DGND + P1 Q1 R1 PB QB RB + P Q R PBAR QBAR RBAR + D_AS137_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} U6 buf DPWR DGND + G1 G1B + D_AS137_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} U7 and(2) DPWR DGND + G2 G1B EN2 + D0_GATE IO_AS00 U8 inv DPWR DGND + GLBAR EN1 + D_AS137_4 IO_AS00 MNTYMXDLY={MNTYMXDLY} U9 nanda(4,8) DPWR DGND + PBAR QBAR RBAR EN2 + P QBAR RBAR EN2 + PBAR Q RBAR EN2 + P Q RBAR EN2 + PBAR QBAR R EN2 + P QBAR R EN2 + PBAR Q R EN2 + P Q R EN2 + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_AS137_5 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS137_1 ugff ( + twghmn=4.5ns tsudgmn=4ns + thdgmn=1ns + ) .model D_AS137_2 ugate ( + tphlmx=4.5ns tplhmx=4ns + ) .model D_AS137_3 ugate ( + tphlmx=.5ns + ) .model D_AS137_4 ugate ( + tplhmn=1ns tplhmx=1ns + tphlmn=1ns tphlmx=1.5ns + ) .model D_AS137_5 ugate ( + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=8.5ns + ) *--------- * 74LS137 3-line to 8-line Decoders/Demultiplexers with Address Latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/21/89 Update interface and model names .subckt 74LS137 G1 G2BAR GLBAR A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inva(4) DPWR DGND + A_BUF B_BUF C_BUF G2BAR A2 B2 C2 G2 + D0_GATE IO_LS U3 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF A1 B1 C1 + D0_GATE IO_LS U4 srff(3) DPWR DGND + $D_HI $D_HI EN1 + A1 B1 C1 A2 B2 C2 + P1 Q1 R1 $D_NC $D_NC $D_NC + D_LS137_1 IO_LS MNTYMXDLY={MNTYMXDLY} U5 srff(3) DPWR DGND + $D_HI $D_HI EN1 + A1 B1 C1 A2 B2 C2 + $D_NC $D_NC $D_NC PB QB RB + D_LS137_2 IO_LS MNTYMXDLY={MNTYMXDLY} U6 bufa(6) DPWR DGND + P1 Q1 R1 PB QB RB + P Q R PBAR QBAR RBAR + D_LS137_3 IO_LS MNTYMXDLY={MNTYMXDLY} U7 buf DPWR DGND + G1 G1B + D_LS137_4 IO_LS MNTYMXDLY={MNTYMXDLY} U8 and(2) DPWR DGND + G2 G1B EN2 + D0_GATE IO_LS U9 inv DPWR DGND + GLBAR EN1 + D_LS137_5 IO_LS MNTYMXDLY={MNTYMXDLY} U10 nanda(4,8) DPWR DGND + PBAR QBAR RBAR EN2 + P QBAR RBAR EN2 + PBAR Q RBAR EN2 + P Q RBAR EN2 + PBAR QBAR R EN2 + P QBAR R EN2 + PBAR Q R EN2 + P Q R EN2 + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_LS137_6 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS137_1 ugff ( + twghmn=15ns tsudgmn=10ns + thdgmn=10ns tpdqhlty=2ns + tpdqhlmx=3ns tpdqlhty=2ns + tpdqlhmx=3ns + ) .model D_LS137_2 ugff ( + twghmn=15ns tsudgmn=10ns + thdgmn=10ns tpdqhlty=1ps + tpdqhlmx=3ns + ) .model D_LS137_3 ugate ( + tplhty=7ns tplhmx=8ns + tphlty=3ns tphlmx=3ps + ) .model D_LS137_4 ugate ( + tplhty=2ns tplhmx=1ps + tphlty=1ns tphlmx=1ps + ) .model D_LS137_5 ugate ( + tplhty=2ns tplhmx=3ns + ) .model D_LS137_6 ugate ( + tplhty=13ns tplhmx=21ns + tphlty=16ns tphlmx=27ns + ) *------------------------------------------------------------------------- * 74AC138 3-line to 8-line Decoders/Demultiplexers * * The FACT Data Book, 1987, FAIRCHILD * cv 06/22/90 Created from LS .subckt 74AC138 E3 E2BAR E1BAR A0 A1 A2 O0BAR O1BAR O2BAR O3BAR O4BAR O5BAR + O6BAR O7BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(3) DPWR DGND + A0 A1 A2 A0_BUF A1_BUF A2_BUF + D0_GATE IO_AC IO_LEVEL={IO_LEVEL} U11 inv DPWR DGND + E3 E3BAR + D_AC138_3 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U22 nor(3) DPWR DGND + E3BAR E2BAR E1BAR G + D0_GATE IO_AC IO_LEVEL={IO_LEVEL} U33 bufa(3) DPWR DGND + A0_BUF A1_BUF A2_BUF P Q R + D_AC138_1 IO_AC MNTYMXDLY={MNTYMXDLY} U44 inva(3) DPWR DGND + A0_BUF A1_BUF A2_BUF PBAR QBAR RBAR + D_AC138_1 IO_AC MNTYMXDLY={MNTYMXDLY} U5 nanda(4,8) DPWR DGND + PBAR QBAR RBAR G + P QBAR RBAR G + PBAR Q RBAR G + P Q RBAR G + PBAR QBAR R G + P QBAR R G + PBAR Q R G + P Q R G + O0BAR O1BAR O2BAR O3BAR O4BAR O5BAR O6BAR O7BAR + D_AC138_2 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC138_1 ugate ( + tplhmn=1ns tplhty=6.5ns + tplhmx=10.5ns tphlmn=1ns + tphlty=6ns tphlmx=10.5ns + ) .model D_AC138_2 ugate ( + tplhmn=1ns tplhty=8ns + tplhmx=12ns tphlmn=1ns + tphlty=7ns tphlmx=10.5ns + ) .model D_AC138_3 ugate ( + tplhmn=1ns tplhty=8ns + tplhmx=12.5ns tphlmn=1ns + tphlty=6ns tphlmx=9.5ns + ) *--------- * 74ACT138 3-line to 8-line Decoders/Demultiplexers * * The FACT Data Book, 1987, Fairchild * cv 06/22/90 Created from LS .subckt 74ACT138 E3 E2BAR E1BAR A0 A1 A2 O0BAR O1BAR O2BAR O3BAR O4BAR O5BAR + O6BAR O7BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(3) DPWR DGND + A0 A1 A2 A0_BUF A1_BUF A2_BUF + D0_GATE IO_ACT IO_LEVEL={IO_LEVEL} U11 inv DPWR DGND + E3 E3BAR + D_ACT138_3 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U22 nor(3) DPWR DGND + E3BAR E2BAR E1BAR G + D0_GATE IO_ACT IO_LEVEL={IO_LEVEL} U33 bufa(3) DPWR DGND + A0_BUF A1_BUF A2_BUF P Q R + D_ACT138_1 IO_ACT MNTYMXDLY={MNTYMXDLY} U44 inva(3) DPWR DGND + A0_BUF A1_BUF A2_BUF PBAR QBAR RBAR + D_ACT138_1 IO_ACT MNTYMXDLY={MNTYMXDLY} U5 nanda(4,8) DPWR DGND + PBAR QBAR RBAR G + P QBAR RBAR G + PBAR Q RBAR G + P Q RBAR G + PBAR QBAR R G + P QBAR R G + PBAR Q R G + P Q R G + O0BAR O1BAR O2BAR O3BAR O4BAR O5BAR O6BAR O7BAR + D_ACT138_2 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT138_1 ugate ( + tplhmn=1ns tplhty=7ns + tplhmx=11.5ns tphlmn=1ns + tphlty=6.5ns tphlmx=11.5ns + ) .model D_ACT138_2 ugate ( + tplhmn=1ns tplhty=8ns + tplhmx=12.5ns tphlmn=1ns + tphlty=7.5ns tphlmx=12.5ns + ) .model D_ACT138_3 ugate ( + tplhmn=1ns tplhty=8ns + tplhmx=13ns tphlmn=1ns + tphlty=6.5ns tphlmx=11.5ns + ) *--------- * 74ALS138 3-line to 8-line Decoders/Demultiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names .subckt 74ALS138 G1 G2BARA G2BARB A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + G1 G1BAR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 nor(3) DPWR DGND + G1BAR G2BARA G2BARB G + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U3 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_ALS138_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U4 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_ALS138_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U5 nanda(4,8) DPWR DGND + PBAR QBAR RBAR G + P QBAR RBAR G + PBAR Q RBAR G + P Q RBAR G + PBAR QBAR R G + P QBAR R G + PBAR Q R G + P Q R G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_ALS138_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS138_1 ugate ( + tplhmn=1ns tplhmx=1ns + tphlmn=2ns tphlmx=5ns + ) .model D_ALS138_2 ugate ( + tplhmn=4ns tplhmx=17ns + tphlmn=5ns tphlmx=17ns + ) *--------- * 74AS138 3-line to 8-line Decoders/Demultiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names .subckt 74AS138 G1 G2BARA G2BARB A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + G1 G1BAR + D_AS138_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 nor(3) DPWR DGND + G1BAR G2BARA G2BARB G + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U3 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_AS138_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U4 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_AS138_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U5 nanda(4,8) DPWR DGND + PBAR QBAR RBAR G + P QBAR RBAR G + PBAR Q RBAR G + P Q RBAR G + PBAR QBAR R G + P QBAR R G + PBAR Q R G + P Q R G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_AS138_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS138_1 ugate ( + tplhmx=1ns tphlmx=2.5ns + ) .model D_AS138_2 ugate ( + tplhmn=2ns tplhmx=7.5ns + tphlmn=2ns tphlmx=8.5ns + ) .model D_AS138_3 ugate ( + tplhmx=2.5ns tphlmx=1.5ns + ) *--------- * 74F138 3-line to 8-line Decoders/Demultiplexers * * The F Logic Data Book, 1987, TI * tdn 07/05/89 Update interface and model names .subckt 74F138 G1 G2BARA G2BARB A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + G1 G1BAR + D_F138_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 nor(3) DPWR DGND + G1BAR G2BARA G2BARB G + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U3 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_F138_1 IO_F MNTYMXDLY={MNTYMXDLY} U4 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_F138_1 IO_F MNTYMXDLY={MNTYMXDLY} U5 nanda(4,8) DPWR DGND + PBAR QBAR RBAR G + P QBAR RBAR G + PBAR Q RBAR G + P Q RBAR G + PBAR QBAR R G + P QBAR R G + PBAR Q R G + P Q R G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_F138_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F138_1 ugate ( + tplhmn=1ns tplhty=0.8ns + tplhmx=1.5ns tphlty=0.2ns + tphlmx=0.5ns + ) .model D_F138_2 ugate ( + tplhmn=2.7ns tplhty=5ns + tplhmx=8ns tphlmn=2.2ns + tphlty=4.9ns tphlmx=7.5ns + ) .model D_F138_3 ugate ( + tplhmn=0.5ns tplhty=0.8ns + tplhmx=1ns tphlmn=0.5ns + tphlty=0.3ns tphlmx=1ns + ) *--------- * 74HC138 3-line to 8-line Decoders/Demultiplexers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HC138 G1 G2BARA G2BARB A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + G1 G1BAR + D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 nor(3) DPWR DGND + G1BAR G2BARA G2BARB G + D0_GATE IO_HC U3 bufa(3) DPWR DGND + A B C P Q R + D_HC138_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 inva(3) DPWR DGND + P Q R PBAR QBAR RBAR + D0_GATE IO_HC U5 nanda(4,8) DPWR DGND + PBAR QBAR RBAR G + P QBAR RBAR G + PBAR Q RBAR G + P Q RBAR G + PBAR QBAR R G + P QBAR R G + PBAR Q R G + P Q R G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_HC138_2 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC138_1 ugate ( + tplhty=1ps tplhmx=6ns + tphlty=1ps tphlmx=6ns + ) .model D_HC138_2 ugate ( + tplhty=18ns tplhmx=39ns + tphlty=18ns tphlmx=39ns + ) *--------- * 74HCT138 3-line to 8-line Decoders/Demultiplexers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HCT138 G1 G2BARA G2BARB A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + G1 G1BAR + D0_GATE IO_HCT IO_LEVEL={IO_LEVEL} U2 nor(3) DPWR DGND + G1BAR G2BARA G2BARB G + D0_GATE IO_HCT IO_LEVEL={IO_LEVEL} U3 bufa(3) DPWR DGND + A B C P Q R + D_HCT138_1 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 inva(3) DPWR DGND + P Q R PBAR QBAR RBAR + D0_GATE IO_HCT U5 nanda(4,8) DPWR DGND + PBAR QBAR RBAR G + P QBAR RBAR G + PBAR Q RBAR G + P Q RBAR G + PBAR QBAR R G + P QBAR R G + PBAR Q R G + P Q R G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_HCT138_2 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HCT138_1 ugate ( + tplhty=1ns tplhmx=3ns + tphlty=1ns tphlmx=3ns + ) .model D_HCT138_2 ugate ( + tplhty=22ns tplhmx=42ns + tphlty=22ns tphlmx=42ns + ) *--------- * 74LS138 3-line to 8-line Decoders/Demultiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74LS138 G1 G2BARA G2BARB A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: For these models, TTL data books list different propagation * delay times depending on the number of "levels of delay" a signal must * pass through to the output. These differences have been ignored here. * As usual, the LARGEST values of those listed have been used. UBUF bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + G1 G1BAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 nor(3) DPWR DGND + G1BAR G2BARA G2BARB G + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U3 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_LS138_1 IO_LS MNTYMXDLY={MNTYMXDLY} U4 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_LS138_1 IO_LS MNTYMXDLY={MNTYMXDLY} U5 nanda(4,8) DPWR DGND + PBAR QBAR RBAR G + P QBAR RBAR G + PBAR Q RBAR G + P Q RBAR G + PBAR QBAR R G + P QBAR R G + PBAR Q R G + P Q R G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_LS138_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS138_1 ugate ( + tplhty=1ps tplhmx=3ns + tphlty=7ns tphlmx=1ns + ) .model D_LS138_2 ugate ( + tplhty=14ns tplhmx=26ns + tphlty=20ns tphlmx=38ns + ) *--------- * 74S138 3-line to 8-line Decoders/Demultiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74S138 G1 G2BARA G2BARB A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: For these models, TTL data books list different propagation * delay times depending on the number of "levels of delay" a signal must * pass through to the output. These differences have been ignored here. * As usual, the LARGEST values of those listed have been used. UBUF bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + G1 G1BAR + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U2 nor(3) DPWR DGND + G1BAR G2BARA G2BARB G + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U3 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_S138_1 IO_S MNTYMXDLY={MNTYMXDLY} U4 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_S138_1 IO_S MNTYMXDLY={MNTYMXDLY} U5 nanda(4,8) DPWR DGND + PBAR QBAR RBAR G + P QBAR RBAR G + PBAR Q RBAR G + P Q RBAR G + PBAR QBAR R G + P QBAR R G + PBAR Q R G + P Q R G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D_S138_2 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S138_1 ugate ( + tplhty=1ns tplhmx=1ns + tphlty=0.5ns tphlmx=1ns + ) .model D_S138_2 ugate ( + tplhty=7ns tplhmx=11ns + tphlty=7ns tphlmx=11ns + ) *------------------------------------------------------------------------- * 74AC139 Dual 2-line to 4-line Decoders/Demultiplexers * * The FACT Data Book, 1987, FAIRCHILD * cv 06/22/90 Created from LS .subckt 74AC139 EBAR A0 A1 O0BAR O1BAR O2BAR O3BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U11 inv DPWR DGND + EBAR G + D_AC139_1 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U22 bufa(2) DPWR DGND + A0 A1 P Q + D0_GATE IO_AC IO_LEVEL={IO_LEVEL} U33 inva(2) DPWR DGND + P Q PBAR QBAR + D0_GATE IO_AC U44 nanda(3,4) DPWR DGND + PBAR QBAR G + P QBAR G + PBAR Q G + P Q G + O0BAR O1BAR O2BAR O3BAR + D_AC139_2 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74AC139 .model D_AC139_1 ugate ( + tplhmn=1ns tplhty=7ns + tplhmx=10ns tphlmn=1ns + tphlty=6ns tphlmx=8.5ns + ) .model D_AC139_2 ugate ( + tplhmn=1ns tplhty=6.5ns + tplhmx=9.5ns tphlmn=1ns + tphlty=5.5ns tphlmx=8.5ns + ) *--------- * 74ACT139 Dual 2-line to 4-line Decoders/Demultiplexers * * The FACT Data Book, 1987, Fairchild * cv 06/22/90 Created from LS .subckt 74ACT139 EBAR A0 A1 O0BAR O1BAR O2BAR O3BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U11 inv DPWR DGND + EBAR G + D_ACT139_1 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U22 bufa(2) DPWR DGND + A0 A1 P Q + D0_GATE IO_ACT IO_LEVEL={IO_LEVEL} U33 inva(2) DPWR DGND + P Q PBAR QBAR + D0_GATE IO_ACT U44 nanda(3,4) DPWR DGND + PBAR QBAR G + P QBAR G + PBAR Q G + P Q G + O0BAR O1BAR O2BAR O3BAR + D_ACT139_2 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74ACT139 .model D_ACT139_1 ugate ( + tplhmn=1ns tplhty=7ns + tplhmx=11ns tphlmn=1ns + tphlty=7ns tphlmx=10.5ns + ) .model D_ACT139_2 ugate ( + tplhmn=1ns tplhty=6ns + tplhmx=9.5ns tphlmn=1ns + tphlty=6ns tphlmx=10.5ns + ) *--------- * 74ALS139 Dual 2-line to 4-line Decoders/Demultiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names .subckt 74ALS139 GBAR A B Y0 Y1 Y2 Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + GBAR G + D_ALS139_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(2) DPWR DGND + A B P Q + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U3 inva(2) DPWR DGND + P Q PBAR QBAR + D0_GATE IO_ALS00 U4 nanda(3,4) DPWR DGND + PBAR QBAR G + P QBAR G + PBAR Q G + P Q G + Y0 Y1 Y2 Y3 + D_ALS139_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74ALS139 .model D_ALS139_1 ugate ( + tplhmx=1ns + ) .model D_ALS139_2 ugate ( + tplhmn=3ns tplhty=9ns + tplhmx=14ns tphlmn=3ns + tphlty=9ns tphlmx=14ns + ) *--------- * 74AS139 Dual 2-line to 4-line Decoders/Demultiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names .subckt 74AS139 GBAR A B Y0 Y1 Y2 Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + GBAR G + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U2 bufa(2) DPWR DGND + A B P Q + D_AS139_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inva(2) DPWR DGND + P Q PBAR QBAR + D0_GATE IO_AS00 U4 nanda(3,4) DPWR DGND + PBAR QBAR G + P QBAR G + PBAR Q G + P Q G + Y0 Y1 Y2 Y3 + D_AS139_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74AS139 .model D_AS139_1 ugate ( + tplhty=1ns tplhmx=1ns + ) .model D_AS139_2 ugate ( + tplhty=5.5ns tplhmx=5.5ns + tphlty=5ns tphlmx=5ns + ) *--------- * 74F139 Dual 2 of 4 Decoder/Demultiplexer * * (c) National Semiconductor, 1988 * cv 08/20/90 .subckt 74F139 EBAR A0 A1 OBAR0 OBAR1 OBAR2 OBAR3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A0 A1 A0_BUF A1_BUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + EBAR E + D_F139_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(2) DPWR DGND + A0_BUF A1_BUF P Q + D_F139_2 IO_F MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + A0_BUF A1_BUF PBAR QBAR + D_F139_2 IO_F MNTYMXDLY={MNTYMXDLY} U4 nanda(3,4) DPWR DGND + PBAR QBAR E + P QBAR E + PBAR Q E + P Q E + OBAR0 OBAR1 OBAR2 OBAR3 + D_F139_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F139_1 ugate ( + tplhmn=0.5ns tplhty=1.4ns + tplhmx=2ns tphlmn=0ns + tphlty=0.7ns tphlmx=2ns + ) .model D_F139_2 ugate ( + tplhmn=0ns tplhty=1.3ns + tplhmx=2.5ns tphlmn=1ns + tphlty=2.7ns tphlmx=3.5ns + ) .model D_F139_3 ugate ( + tplhmn=3ns tplhty=4ns + tplhmx=6ns tphlmn=3ns + tphlty=4ns tphlmx=5.5ns + ) *--------- * 74HC139 Dual 2-line to 4-line Decoders/Demultiplexers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/05/89 Update interface and model names .subckt 74HC139 GBAR A B Y0 Y1 Y2 Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + GBAR G + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U2 bufa(2) DPWR DGND + A B P Q + D_HC139_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inva(2) DPWR DGND + P Q PBAR QBAR + D0_GATE IO_HC U4 nanda(3,4) DPWR DGND + PBAR QBAR G + P QBAR G + PBAR Q G + P Q G + Y0 Y1 Y2 Y3 + D_HC139_2 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74HC139 .model D_HC139_1 ugate ( + tplhty=3ns tphlty=3ns + ) .model D_HC139_2 ugate ( + tplhty=11ns tplhmx=44ns + tphlty=11ns tphlmx=44ns + ) *--------- * 74HCT139 Dual 2-to-4 line Decoders/Demultiplexers * * (c) National Semiconductor, 1988 * cv 08/20/90 .subckt 74HCT139 G A B Y0 Y1 Y2 Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_HCT IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + G GBAR + D_HCT139_1 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_HCT139_2 IO_HCT MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_HCT139_2 IO_HCT MNTYMXDLY={MNTYMXDLY} U4 nanda(3,4) DPWR DGND + PBAR QBAR GBAR + P QBAR GBAR + PBAR Q GBAR + P Q GBAR + Y0 Y1 Y2 Y3 + D_HCT139_3 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HCT139_1 ugate ( + tplhty=1ns tplhmx=2ns + tphlty=1ns tphlmx=2ns + ) .model D_HCT139_2 ugate ( + tplhty=1ns tplhmx=2ns + tphlty=1ns tphlmx=2ns + ) .model D_HCT139_3 ugate ( + tplhty=34ns tplhmx=42ns + tphlty=34ns tphlmx=42ns + ) *--------- * 74LS139 Dual 2-line to 4-line Decoders/Demultiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74LS139 GBAR A B Y0 Y1 Y2 Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + GBAR G + D_LS139_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_LS139_3 IO_LS MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_LS139_2 IO_LS MNTYMXDLY={MNTYMXDLY} U4 nanda(3,4) DPWR DGND + PBAR QBAR G + P QBAR G + PBAR Q G + P Q G + Y0 Y1 Y2 Y3 + D_LS139_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74LS139 .model D_LS139_1 ugate ( + tphlty=3ns tphlmx=4ns + ) .model D_LS139_2 ugate ( + tplhty=1ns tplhmx=1ns + ) .model D_LS139_3 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=5ns tphlmx=9ns + ) .model D_LS139_4 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=21ns tphlmx=32ns + ) *--------- * 74S139 Dual 2-line to 4-line Decoders/Demultiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74S139 GBAR A B Y0 Y1 Y2 Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + GBAR G + D_S139_1 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_S139_2 IO_S MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D0_GATE IO_S U4 nanda(3,4) DPWR DGND + PBAR QBAR G + P QBAR G + PBAR Q G + P Q G + Y0 Y1 Y2 Y3 + D_S139_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74S139 .model D_S139_1 ugate ( + tphlmx=0.5ns tphlty=1ps + tphlmn=0ns + ) .model D_S139_2 ugate ( + tplhty=1.5ns tplhmx=2ns + tphlty=2ns tphlmx=4.5ns + ) .model D_S139_3 ugate ( + tplhty=5ns tplhmx=7.5ns + tphlty=6.5ns tphlmx=10ns + ) *------------------------------------------------------------------------- * 54S140 Dual 4-input Positive-Nand 50-Ohm Line Drivers * * (c) Texas Instruments, 1988 * cv 08/20/90 .subckt 54S140 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_54S140 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_54S140 ugate ( + tplhty=4ns tplhmx=6.5ns + tphlty=4ns tphlmx=6.5ns + ) *--------- * 74S140 Dual 4-input Positive-Nand 50-Ohm Line Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74S140 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_74S140 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_74S140 ugate ( + tplhty=4ns tplhmx=6.5ns + tphlty=4ns tphlmx=6.5ns + ) *------------------------------------------------------------------------- * 74145 BCD-to-Decimal Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/30/89 Update interface and model names .subckt 74145 A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 X1 A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 DPWR DGND 7445 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends *--------- * 74LS145 BCD-to-Decimal Decoders/Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/30/89 Update interface and model names .subckt 74LS145 A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(4) DPWR DGND + A B C D P Q R S + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inva(4) DPWR DGND + P Q R S PB QB RB SB + D0_GATE IO_LS U3 nanda(4,10) DPWR DGND + PB QB RB SB + P QB RB SB + PB Q RB SB + P Q RB SB + PB QB R SB + P QB R SB + PB Q R SB + P Q R SB + PB QB RB S + P QB RB S + Y0 Y1 Y2 Y3 Y4 + Y5 Y6 Y7 Y8 Y9 + D_LS145 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS145 ugate ( + tphlmx=50ns tplhmx=50ns + ) *------------------------------------------------------------------------- * 74147 10-Line to 4-Line Priority Decoders * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/30/89 Update interface and model names .subckt 74147 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 A B C D + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(9) DPWR DGND + IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 + I1 I2 I3 I4 I5 I6 I7 I8 I9 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inva(9) DPWR DGND + I1 I2 I3 I4 I5 I6 I7 I8 I9 + I1B I2B I3B I4B I5B I6B I7B I8B I9B + D0_GATE IO_STD U3 bufa(4) DPWR DGND + I2 I4 I5 I6 I2D I4D I5D I6D + D_147_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 aoi(5,5) DPWR DGND + I1B I2D I4D I6D I89 + I3B I4D I6D I89 $D_HI + I5B I6D I89 $D_HI $D_HI + I7B I89 $D_HI $D_HI $D_HI + I9B $D_HI $D_HI $D_HI $D_HI + A + D_147_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 aoi(4,4) DPWR DGND + I2B I4D I5D I89 + I3B I4D I5D I89 + I6B I89 $D_HI $D_HI + I7B I89 $D_HI $D_HI + B + D_147_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(2,4) DPWR DGND + I4B I89 I5B I89 I6B I89 I7B I89 C + D_147_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 nor(2) DPWR DGND + I8B I9B I89 + D_147_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 nor(2) DPWR DGND + I8B I9B D + D_147_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_147_1 ugate ( + tplhty=5ns tplhmx=8ns + tphlty=4ns tphlmx=5ns + ) .model D_147_2 ugate ( + tplhty=9ns tplhmx=14ns + tphlty=7ns tphlmx=11ns + ) *--------- * 74HC147 10-Line to 4-Line Priority Decoders * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 09/05/89 Update interface and model names .subckt 74HC147 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 A B C D + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(9) DPWR DGND + IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 + I1 I2 I3 I4 I5 I6 I7 I8 I9 + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U2 inva(9) DPWR DGND + I1 I2 I3 I4 I5 I6 I7 I8 I9 + I1B I2B I3B I4B I5B I6B I7B I8B I9B + D0_GATE IO_HC U4 aoi(5,5) DPWR DGND + I1B I2 I4 I6 I89 + I3B I4 I6 I89 $D_HI + I5B I6 I89 $D_HI $D_HI + I7B I89 $D_HI $D_HI $D_HI + I9B $D_HI $D_HI $D_HI $D_HI + A + D_HC147 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 aoi(4,4) DPWR DGND + I2B I4 I5 I89 + I3B I4 I5 I89 + I6B I89 $D_HI $D_HI + I7B I89 $D_HI $D_HI + B + D_HC147 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(2,4) DPWR DGND + I4B I89 I5B I89 I6B I89 I7B I89 C + D_HC147 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 nor(2) DPWR DGND + I8B I9B I89 + D0_GATE IO_HC U8 nor(2) DPWR DGND + I8B I9B D + D_HC147 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC147 ugate ( + tplhty=25ns tplhmx=48ns + tphlty=25ns tphlmx=48ns + ) *--------- * 74LS147 10-Line to 4-Line Priority Decoders * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/30/89 Update interface and model names .subckt 74LS147 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 A B C D + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(9) DPWR DGND + IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 + I1 I2 I3 I4 I5 I6 I7 I8 I9 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inva(9) DPWR DGND + I1 I2 I3 I4 I5 I6 I7 I8 I9 + I1B I2B I3B I4B I5B I6B I7B I8B I9B + D0_GATE IO_LS U3 bufa(4) DPWR DGND + I2 I4 I5 I6 I2D I4D I5D I6D + D_LS147_1 IO_LS MNTYMXDLY={MNTYMXDLY} U4 aoi(5,5) DPWR DGND + I1B I2D I4D I6D I89 + I3B I4D I6D I89 $D_HI + I5B I6D I89 $D_HI $D_HI + I7B I89 $D_HI $D_HI $D_HI + I9B $D_HI $D_HI $D_HI $D_HI + A + D_LS147_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 aoi(4,4) DPWR DGND + I2B I4D I5D I89 + I3B I4D I5D I89 + I6B I89 $D_HI $D_HI + I7B I89 $D_HI $D_HI + B + D_LS147_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(2,4) DPWR DGND + I4B I89 I5B I89 I6B I89 I7B I89 C + D_LS147_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 nor(2) DPWR DGND + I8B I9B I89 + D_LS147_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 nor(2) DPWR DGND + I8B I9B D + D_LS147_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS147_1 ugate ( + tplhty=3ns tplhmx=10ns + tphlty=9ns tphlmx=15ns + ) .model D_LS147_2 ugate ( + tplhty=12ns tplhmx=18ns + tphlty=12ns tphlmx=18ns + ) *------------------------------------------------------------------------- * 74148 8-Line to 3-Line Priority Encoder * * The TTL Data Book, Vol 2, 1985, TI * tdn 09/05/89 Update interface and model names .subckt 74148 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI A0 A1 A2 GS EO + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(8) DPWR DGND + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 + I0 I1 I2 I3 I4 I5 I6 I7 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inva(8) DPWR DGND + I1 I2 I3 I4 I5 I6 I7 EI + I1B I2B I3B I4B I5B I6B I7B EIBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 bufa(4) DPWR DGND + I2 I4 I5 I6 I2D I4D I5D I6D + D_148_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 buf DPWR DGND + EIBAR EIB + D_148_2 IO_STD MNTYMXDLY={MNTYMXDLY} U5 buf DPWR DGND + EIB EIBO + D_148_3 IO_STD MNTYMXDLY={MNTYMXDLY} U6 aoi(5,4) DPWR DGND + EIB I7B $D_HI $D_HI $D_HI + EIB I6D I5B $D_HI $D_HI + EIB I6B I4D I3B $D_HI + EIB I6D I4D I2D I1B + A0 + D_148_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 aoi(4,4) DPWR DGND + EIB I7B $D_HI $D_HI + EIB I6B $D_HI $D_HI + EIB I5D I4D I3B + EIB I5D I4D I2B + A1 + D_148_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 aoi(2,4) DPWR DGND + EIB I7B EIB I6B EIB I5B EIB I4B A2 + D_148_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 nand(9) DPWR DGND + I0 I1 I2 I3 I4 I5 I6 I7 EIBO + EOD + D_148_5 IO_STD MNTYMXDLY={MNTYMXDLY} U10 buf DPWR DGND + EOD EO + D_148_6 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U11 buf DPWR DGND + EOD EGS + D_148_7 IO_STD MNTYMXDLY={MNTYMXDLY} U12 nand(2) DPWR DGND + EGS EIBGS GS + D_148_8 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U13 and(9) DPWR DGND + EIBAR I0 I1 I2 I3 I4 I5 I6 I7 + EN + D0_GATE IO_STD U14 inv DPWR DGND + EN ENB + D0_GATE IO_STD U15 buf3 DPWR DGND + EIB EN EIBGS + D_148_9 IO_STD MNTYMXDLY={MNTYMXDLY} U16 buf3 DPWR DGND + EIB ENB EIBGS + D0_TGATE IO_STD .ends .model D_148_1 ugate ( + tplhty=3ns tplhmx=5ns + tphlty=3ns tphlmx=4ns + ) .model D_148_2 ugate ( + tplhty=1ns tplhmx=1ns + ) .model D_148_3 ugate ( + tplhty=2ns tplhmx=4ns + tphlty=4ns tphlmx=5ns + ) .model D_148_4 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=9ns tphlmx=14ns + ) .model D_148_5 ugate ( + tplhty=1ps tplhmx=4ns + tphlty=1ps tphlmx=4ns + ) .model D_148_6 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=14ns tphlmx=21ns + ) .model D_148_7 ugate ( + tplhty=5ns tplhmx=7ns + tphlty=10ns tphlmx=14ns + ) .model D_148_8 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=9ns tphlmx=14ns + ) .model D_148_9 utgate ( + tplhty=8ns tplhmx=15ns + ) *--------- * 74F148 8-Line to 3-Line Priority Encoder * * (c) Philips Components, 1990 * cv 09/05/90 Update interface and model names .subckt 74F148 I0B I1B I2B I3B I4B I5B I6B I7B EIB A0B A1B A2B GSB EOB + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(8) DPWR DGND + I0B I1B I2B I3B I4B I5B I6B I7B + I0 I1 I2 I3 I4 I5 I6 I7 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U2 inva(7) DPWR DGND + I1 I2 I3 I4 I5 I6 I7 + IB1 IB2 IB3 IB4 IB5 IB6 IB7 + D_F148_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inv DPWR DGND + EIB EI + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U4 bufa(4) DPWR DGND + I2 I4 I5 I6 I2D I4D I5D I6D + D_F148_2 IO_F MNTYMXDLY={MNTYMXDLY} U5 buf DPWR DGND + EI EIBUF + D_F148_3 IO_F MNTYMXDLY={MNTYMXDLY} U6 buf DPWR DGND + EI EIBO + D_F148_4 IO_F MNTYMXDLY={MNTYMXDLY} U7 aoi(5,4) DPWR DGND + EIBUF IB7 $D_HI $D_HI $D_HI + EIBUF I6D IB5 $D_HI $D_HI + EIBUF IB6 I4D IB3 $D_HI + EIBUF I6D I4D I2D IB1 + A0B + D_F148_5 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 aoi(4,4) DPWR DGND + EIBUF IB7 $D_HI $D_HI + EIBUF IB6 $D_HI $D_HI + EIBUF I5D I4D IB3 + EIBUF I5D I4D IB2 + A1B + D_F148_5 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 aoi(2,4) DPWR DGND + EIBUF IB7 EIBUF IB6 EIBUF IB5 EIBUF IB4 A2B + D_F148_5 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U10 nand(9) DPWR DGND + I0 I1 I2 I3 I4 I5 I6 I7 EIBO + EOD + D_F148_6 IO_F MNTYMXDLY={MNTYMXDLY} U11 buf DPWR DGND + EOD EOB + D_F148_7 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12 buf DPWR DGND + EOD EGS + D_F148_8 IO_F MNTYMXDLY={MNTYMXDLY} U13 buf DPWR DGND + EI EIBGS + D_F148_9 IO_F MNTYMXDLY={MNTYMXDLY} U14 nand(2) DPWR DGND + EGS EIBGS GSB + D_F148_10 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F148_1 ugate ( + tplhmn=0.5ns tplhty=1ns + tplhmx=1.5ns tphlmn=1ns + tphlty=1.5ns tphlmx=4ns + ) .model D_F148_2 ugate ( + tplhmn=0.5ns tplhty=1ns + tplhmx=1.5ns tphlmn=1ns + tphlty=1.5ns tphlmx=4ns + ) .model D_F148_3 ugate ( + tplhmn=0.5ns tplhty=1ns + tplhmx=1ns tphlmn=0ns + tphlty=1ns tphlmx=1ns + ) .model D_F148_4 ugate ( + tplhmn=1ns tplhty=1.5ns + tplhmx=0.5ns tphlmn=1.5ns + tphlty=2.5ns tphlmx=3.5ns + ) .model D_F148_5 ugate ( + tplhmn=3ns tplhty=5ns + tplhmx=8.5ns tphlmn=3ns + tphlty=4.5ns tphlmx=8ns + ) .model D_F148_6 ugate ( + tplhmn=2ns tplhty=3ns + tplhmx=7ns tphlmn=2ns + tphlty=4ns tphlmx=8ns + ) .model D_F148_7 ugate ( + tplhmn=0ns tplhty=0.5ns + tplhmx=0.5ns tphlmn=0.5ns + tphlty=0.5ns tphlmx=0.5ns + ) .model D_F148_8 ugate ( + tplhmn=0ns tplhty=0ns + tplhmx=0ns tphlmn=0ns + tphlty=1ns tphlmx=0ns + ) .model D_F148_9 ugate ( + tplhmn=2.5ns tplhty=3.5ns + tplhmx=5ns tphlmn=3ns + tphlty=4.5ns tphlmx=7.5ns + ) .model D_F148_10 ugate ( + tplhmn=0ns tplhty=1ns + tplhmx=3ns tphlmn=0ns + tphlty=1ns tphlmx=1ns + ) *--------- * 74HC148 8-Line to 3-Line Priority Encoder * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 09/07/89 Update interface and model names .subckt 74HC148 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI A0 A1 A2 GS EO + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(8) DPWR DGND + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 + I0 I1 I2 I3 I4 I5 I6 I7 + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U2 inva(8) DPWR DGND + I1 I2 I3 I4 I5 I6 I7 EI + I1B I2B I3B I4B I5B I6B I7B EIBAR + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U3 bufa(8) DPWR DGND + I0 I1 I2 I3 I4 I5 I6 I7 + I0E I1E I2E I3E I4E I5E I6E I7E + D_HC148_1 IO_HC MNTYMXDLY={MNTYMXDLY} U4 buf DPWR DGND + EIBAR EIB + D_HC148_2 IO_HC MNTYMXDLY={MNTYMXDLY} U5 buf DPWR DGND + EIBAR EIBO + D_HC148_3 IO_HC MNTYMXDLY={MNTYMXDLY} U6 aoi(5,4) DPWR DGND + EIB I7B $D_HI $D_HI $D_HI + EIB I6 I5B $D_HI $D_HI + EIB I6B I4 I3B $D_HI + EIB I6 I4 I2 I1B + A0 + D_HC148_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 aoi(4,4) DPWR DGND + EIB I7B $D_HI $D_HI + EIB I6B $D_HI $D_HI + EIB I5 I4 I3B + EIB I5 I4 I2B + A1 + D_HC148_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 aoi(2,4) DPWR DGND + EIB I7B EIB I6B EIB I5B EIB I4B A2 + D_HC148_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 nand(9) DPWR DGND + I0E I1E I2E I3E I4E I5E I6E I7E EIBO + EOD + D_HC148_5 IO_HC MNTYMXDLY={MNTYMXDLY} U10 buf DPWR DGND + EOD EO + D_HC148_6 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12 nand(2) DPWR DGND + EOD EIBGS GS + D_HC148_7 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U13 and(9) DPWR DGND + EIBAR I0 I1 I2 I3 I4 I5 I6 I7 + EN + D0_GATE IO_HC U14 inv DPWR DGND + EN ENB + D0_GATE IO_HC U15 buf3 DPWR DGND + EIB EN EIBGS + D_HC148_8 IO_HC MNTYMXDLY={MNTYMXDLY} U16 buf3 DPWR DGND + EIB ENB EIBGS + D0_TGATE IO_HC .ends .model D_HC148_1 ugate ( + tplhty=6ns tplhmx=10ns + tphlty=6ns tphlmx=10ns + ) .model D_HC148_2 ugate ( + tplhty=3ns tplhmx=4ns + tphlty=3ns tphlmx=4ns + ) .model D_HC148_3 ugate ( + tplhty=8ns tplhmx=13ns + tphlty=8ns tphlmx=13ns + ) .model D_HC148_4 ugate ( + tplhty=23ns tplhmx=45ns + tphlty=23ns tphlmx=45ns + ) .model D_HC148_5 ugate ( + tplhty=3ns tplhmx=6ns + tphlty=3ns tphlmx=6ns + ) .model D_HC148_6 ugate ( + tplhty=11ns tplhmx=22ns + tphlty=11ns tphlmx=22ns + ) .model D_HC148_7 ugate ( + tplhty=16ns tplhmx=32ns + tphlty=16ns tphlmx=32ns + ) .model D_HC148_8 utgate ( + tplhty=8ns tplhmx=15ns + ) *--------- * 74HCT148 8-Line to 3-Line Priority Encoder * * (c) Goldstar Semiconductor, 1989 * cv 09/05/90 Update interface and model names .subckt 74HCT148 A0B A1B A2B A3B A4B A5B A6B A7B EI Y0B Y1B Y2B GS EO + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(8) DPWR DGND + A0B A1B A2B A3B A4B A5B A6B A7B + A0 A1 A2 A3 A4 A5 A6 A7 + D0_GATE IO_HCT IO_LEVEL={IO_LEVEL} U2 inva(7) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 + AB1 AB2 AB3 AB4 AB5 AB6 AB7 + D_HCT148_1 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inv DPWR DGND + EI EIBAR + D0_GATE IO_HCT IO_LEVEL={IO_LEVEL} U4 bufa(4) DPWR DGND + A2 A4 A5 A6 A2D A4D A5D A6D + D_HCT148_2 IO_HCT MNTYMXDLY={MNTYMXDLY} U5 buf DPWR DGND + EIBAR EIBUF + D_HCT148_3 IO_HCT MNTYMXDLY={MNTYMXDLY} U6 buf DPWR DGND + EIBAR EIBO + D_HCT148_4 IO_HCT MNTYMXDLY={MNTYMXDLY} U7 aoi(5,4) DPWR DGND + EIBUF AB7 $D_HI $D_HI $D_HI + EIBUF A6D AB5 $D_HI $D_HI + EIBUF AB6 A4D AB3 $D_HI + EIBUF A6D A4D A2D AB1 + Y0B + D_HCT148_5 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 aoi(4,4) DPWR DGND + EIBUF AB7 $D_HI $D_HI + EIBUF AB6 $D_HI $D_HI + EIBUF A5D A4D AB3 + EIBUF A5D A4D AB2 + Y1B + D_HCT148_5 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 aoi(2,4) DPWR DGND + EIBUF AB7 EIBUF AB6 EIBUF AB5 EIBUF AB4 Y2B + D_HCT148_5 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U10 nand(9) DPWR DGND + A0 A1 A2 A3 A4 A5 A6 A7 EIBO + EOD + D_HCT148_6 IO_HCT MNTYMXDLY={MNTYMXDLY} U11 buf DPWR DGND + EOD EO + D_HCT148_7 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12 buf DPWR DGND + EOD EGS + D_HCT148_8 IO_HCT MNTYMXDLY={MNTYMXDLY} U13 buf DPWR DGND + EIBAR EIBGS + D_HCT148_9 IO_HCT MNTYMXDLY={MNTYMXDLY} U14 nand(2) DPWR DGND + EGS EIBGS GS + D_HCT148_10 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HCT148_1 ugate ( + tplhty=4ns tplhmx=4ns + tphlty=4ns tphlmx=4ns + ) .model D_HCT148_2 ugate ( + tplhty=4ns tplhmx=4ns + tphlty=4ns tphlmx=4ns + ) .model D_HCT148_3 ugate ( + tplhty=7ns tplhmx=9ns + tphlty=7ns tphlmx=9ns + ) .model D_HCT148_4 ugate ( + tplhty=2ns tplhmx=9ns + tphlty=2ns tphlmx=9ns + ) .model D_HCT148_5 ugate ( + tplhty=20ns tplhmx=50ns + tphlty=20ns tphlmx=50ns + ) .model D_HCT148_6 ugate ( + tplhty=20ns tplhmx=40ns + tphlty=20ns tphlmx=40ns + ) .model D_HCT148_7 ugate ( + tplhty=1ns tplhmx=5ns + tphlty=1ns tphlmx=5ns + ) .model D_HCT148_8 ugate ( + tplhty=5ns tplhmx=13ns + tphlty=5ns tphlmx=13ns + ) .model D_HCT148_9 ugate ( + tplhty=20ns tplhmx=40ns + tphlty=20ns tphlmx=40ns + ) .model D_HCT148_10 ugate ( + tplhty=1ns tplhmx=5ns + tphlty=1ns tphlmx=5ns + ) *--------- * 74LS148 8-Line to 3-Line Priority Encoder * * The TTL Data Book, Vol 2, 1985, TI * tdn 09/06/89 Update interface and model names .subckt 74LS148 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI A0 A1 A2 GS EO + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(8) DPWR DGND + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 + I0 I1 I2 I3 I4 I5 I6 I7 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inva(7) DPWR DGND + I1 I2 I3 I4 I5 I6 I7 + I1B I2B I3B I4B I5B I6B I7B + D_LS148_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inv DPWR DGND + EI EIBAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U4 bufa(4) DPWR DGND + I2 I4 I5 I6 I2D I4D I5D I6D + D_LS148_2 IO_LS MNTYMXDLY={MNTYMXDLY} U5 bufa(8) DPWR DGND + I0 I1 I2 I3 I4 I5 I6 I7 + I0E I1E I2E I3E I4E I5E I6E I7E + D_LS148_3 IO_LS MNTYMXDLY={MNTYMXDLY} U6 buf DPWR DGND + EIBAR EIB + D_LS148_4 IO_LS MNTYMXDLY={MNTYMXDLY} U7 buf DPWR DGND + EIBAR EIBO + D_LS148_5 IO_LS MNTYMXDLY={MNTYMXDLY} U8 buf DPWR DGND + EIBAR EIBGS1 + D_LS148_6 IO_LS MNTYMXDLY={MNTYMXDLY} U9 aoi(5,4) DPWR DGND + EIB I7B $D_HI $D_HI $D_HI + EIB I6D I5B $D_HI $D_HI + EIB I6B I4D I3B $D_HI + EIB I6D I4D I2D I1B + A0 + D_LS148_7 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U10 aoi(4,4) DPWR DGND + EIB I7B $D_HI $D_HI + EIB I6B $D_HI $D_HI + EIB I5D I4D I3B + EIB I5D I4D I2B + A1 + D_LS148_7 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U11 aoi(2,4) DPWR DGND + EIB I7B EIB I6B EIB I5B EIB I4B A2 + D_LS148_7 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12 nand(9) DPWR DGND + I0E I1E I2E I3E I4E I5E I6E I7E EIBO + EOD + D_LS148_8 IO_LS MNTYMXDLY={MNTYMXDLY} U13 buf DPWR DGND + EOD EO + D_LS148_9 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U14 buf DPWR DGND + EOD EGS + D_LS148_10 IO_LS MNTYMXDLY={MNTYMXDLY} U15 nand(2) DPWR DGND + EGS EIBGS GS + D_LS148_11 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U16 and(9) DPWR DGND + I0 I1 I2 I3 I4 I5 I6 I7 EIBAR + EN + D0_GATE IO_LS U17 inv DPWR DGND + EN ENB + D0_GATE IO_LS U18 buf3 DPWR DGND + EIBGS1 EN EIBGS + D_LS148_12 IO_LS MNTYMXDLY={MNTYMXDLY} U19 buf3 DPWR DGND + EIBGS1 ENB EIBGS + D0_TGATE IO_LS .ends .model D_LS148_1 ugate ( + tplhty=3ns tplhmx=1ps + ) .model D_LS148_2 ugate ( + tplhty=4ns tplhmx=4ns + tphlty=6ns tphlmx=18ns + ) .model D_LS148_3 ugate ( + tplhty=2ns tplhmx=5ns + ) .model D_LS148_4 ugate ( + tphlty=2ns tphlmx=7ns + ) .model D_LS148_5 ugate ( + tphlty=5ns tphlmx=3ns + ) .model D_LS148_6 ugate ( + tplhty=5ns tplhmx=15ns + ) .model D_LS148_7 ugate ( + tplhty=14ns tplhmx=18ns + tphlty=12ns tphlmx=25ns + ) .model D_LS148_8 ugate ( + tphlty=17ns tphlmx=28ns + ) .model D_LS148_9 ugate ( + tplhty=7ns tplhmx=18ns + tphlty=6ns tphlmx=7ns + ) .model D_LS148_10 ugate ( + tphlty=4ns tphlmx=5ns + ) .model D_LS148_11 ugate ( + tplhty=12ns tplhmx=17ns + tphlty=9ns tphlmx=21ns + ) .model D_LS148_12 utgate ( + tplhty=11ns tplhmx=1ps + ) *--------- * 74S148 8-Line to 3-Line Priority Encoder * * (c) Goldstar Semiconductor, 1989 * cv 09/05/90 Update interface and model names .subckt 74S148 D0B D1B D2B D3B D4B D5B D6B D7B EIB A0B A1B A2B GSB EOB + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(8) DPWR DGND + D0B D1B D2B D3B D4B D5B D6B D7B + D0 D1 D2 D3 D4 D5 D6 D7 + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U2 inva(7) DPWR DGND + D1 D2 D3 D4 D5 D6 D7 + DB1 DB2 DB3 DB4 DB5 DB6 DB7 + D_S148_1 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inv DPWR DGND + EIB EI + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U4 bufa(4) DPWR DGND + D2 D4 D5 D6 D2D D4D D5D D6D + D_S148_2 IO_S MNTYMXDLY={MNTYMXDLY} U5 buf DPWR DGND + EI EIBUF + D_S148_3 IO_S MNTYMXDLY={MNTYMXDLY} U6 buf DPWR DGND + EI EIBO + D_S148_4 IO_S MNTYMXDLY={MNTYMXDLY} U7 aoi(5,4) DPWR DGND + EIBUF DB7 $D_HI $D_HI $D_HI + EIBUF D6D DB5 $D_HI $D_HI + EIBUF DB6 D4D DB3 $D_HI + EIBUF D6D D4D D2D DB1 + A0B + D_S148_5 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 aoi(4,4) DPWR DGND + EIBUF DB7 $D_HI $D_HI + EIBUF DB6 $D_HI $D_HI + EIBUF D5D D4D DB3 + EIBUF D5D D4D DB2 + A1B + D_S148_5 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 aoi(2,4) DPWR DGND + EIBUF DB7 EIBUF DB6 EIBUF DB5 EIBUF DB4 A2B + D_S148_5 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U10 nand(9) DPWR DGND + D0 D1 D2 D3 D4 D5 D6 D7 EIBO + EOD + D_S148_6 IO_S MNTYMXDLY={MNTYMXDLY} U11 buf DPWR DGND + EOD EOB + D_S148_7 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12 buf DPWR DGND + EOD EGS + D_S148_8 IO_S MNTYMXDLY={MNTYMXDLY} U13 buf DPWR DGND + EI EIBGS + D_S148_9 IO_S MNTYMXDLY={MNTYMXDLY} U14 nand(2) DPWR DGND + EGS EIBGS GSB + D_S148_10 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S148_1 ugate ( + tplhty=1ns tplhmx=2ns + tphlty=1ns tphlmx=2ns + ) .model D_S148_2 ugate ( + tplhty=1ns tplhmx=2ns + tphlty=1ns tphlmx=2ns + ) .model D_S148_3 ugate ( + tplhty=2ns tplhmx=2ns + tphlty=2ns tphlmx=2ns + ) .model D_S148_4 ugate ( + tplhty=1ns tplhmx=1ns + tphlty=1ns tphlmx=1ns + ) .model D_S148_5 ugate ( + tplhty=8ns tplhmx=11ns + tphlty=8ns tphlmx=11ns + ) .model D_S148_6 ugate ( + tplhty=11ns tplhmx=13ns + tphlty=11ns tphlmx=13ns + ) .model D_S148_7 ugate ( + tplhty=1ns tplhmx=2ns + tphlty=1ns tphlmx=2ns + ) .model D_S148_8 ugate ( + tplhty=0ns tplhmx=1ns + tphlty=0ns tphlmx=1ns + ) .model D_S148_9 ugate ( + tplhty=6ns tplhmx=8ns + tphlty=6ns tphlmx=8ns + ) .model D_S148_10 ugate ( + tplhty=0ns tplhmx=1ns + tphlty=0ns tphlmx=1ns + ) *------------------------------------------------------------------------- * 74150 Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74150 GBAR A B C D E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 + E15 W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + GBAR G + D_150_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_150_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D_150_2 IO_STD MNTYMXDLY={MNTYMXDLY} U4 aoi(6,16) DPWR DGND + E0 PBAR QBAR RBAR SBAR G + E1 P QBAR RBAR SBAR G + E2 PBAR Q RBAR SBAR G + E3 P Q RBAR SBAR G + E4 PBAR QBAR R SBAR G + E5 P QBAR R SBAR G + E6 PBAR Q R SBAR G + E7 P Q R SBAR G + E8 PBAR QBAR RBAR S G + E9 P QBAR RBAR S G + E10 PBAR Q RBAR S G + E11 P Q RBAR S G + E12 PBAR QBAR R S G + E13 P QBAR R S G + E14 PBAR Q R S G + E15 P Q R S G + W + D_150_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_150_1 ugate ( + tplhty=8ns tplhmx=10ns + tphlty=7ns tphlmx=10ns + ) .model D_150_2 ugate ( + tplhty=9ns tplhmx=13ns + tphlty=14.5ns tphlmx=21ns + ) .model D_150_3 ugate ( + tplhty=8.5ns tplhmx=14ns + tphlty=13ns tphlmx=20ns + ) *------------------------------------------------------------------------- * 74151A Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/28/89 Update interface and model names .subckt 74151A GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 Y W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + GBAR A B C GBAR_BUF A_BUF B_BUF C_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + GBAR_BUF G + D_151A_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_151A_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_151A_2 IO_STD MNTYMXDLY={MNTYMXDLY} U4 aoi(5,8) DPWR DGND + D0 PBAR QBAR RBAR G + D1 P QBAR RBAR G + D2 PBAR Q RBAR G + D3 P Q RBAR G + D4 PBAR QBAR R G + D5 P QBAR R G + D6 PBAR Q R G + D7 P Q R G + W + D_151A_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 inv DPWR DGND + GBAR_BUF H + D_151A_4 IO_STD MNTYMXDLY={MNTYMXDLY} U6 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF L M N + D_151A_5 IO_STD MNTYMXDLY={MNTYMXDLY} U7 inva(3) DPWR DGND + A_BUF B_BUF C_BUF LBAR MBAR NBAR + D_151A_5 IO_STD MNTYMXDLY={MNTYMXDLY} U8 ao(5,8) DPWR DGND + D0 LBAR MBAR NBAR H + D1 L MBAR NBAR H + D2 LBAR M NBAR H + D3 L M NBAR H + D4 LBAR MBAR N H + D5 L MBAR N H + D6 LBAR M N H + D7 L M N H + Y + D_151A_6 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74151A .model D_151A_1 ugate ( + tplhty=7ns tplhmx=9ns + tphlty=6ns tphlmx=7ns + ) .model D_151A_2 ugate ( + tplhty=11ns tplhmx=16ns + tphlty=9ns tphlmx=12ns + ) .model D_151A_3 ugate ( + tplhty=8ns tplhmx=14ns + tphlty=8ns tphlmx=14ns + ) .model D_151A_4 ugate ( + tplhty=8ns tplhmx=13ns + tphlty=4ns tphlmx=6ns + ) .model D_151A_5 ugate ( + tplhty=12ns tplhmx=18ns + tphlty=7ns tphlmx=11ns + ) .model D_151A_6 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=18ns tphlmx=27ns + ) *--------- * 74AC151 Data Selectors/Multiplexers * * The FACT Data Book, 1987, Fairchild * cv 06/22/90 Created from LS .subckt 74AC151 EBAR S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 Z ZBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + EBAR S0 S1 S2 EBAR_BUF S0_BUF S1_BUF S2_BUF + D0_GATE IO_AC IO_LEVEL={IO_LEVEL} U11 inv DPWR DGND + EBAR_BUF G + D_AC151_1 IO_AC MNTYMXDLY={MNTYMXDLY} U22 bufa(3) DPWR DGND + S0_BUF S1_BUF S2_BUF P Q R + D_AC151_2 IO_AC MNTYMXDLY={MNTYMXDLY} U32 inva(3) DPWR DGND + S0_BUF S1_BUF S2_BUF PBAR QBAR RBAR + D_AC151_2 IO_AC U44 aoi(5,8) DPWR DGND + I0 PBAR QBAR RBAR G + I1 P QBAR RBAR G + I2 PBAR Q RBAR G + I3 P Q RBAR G + I4 PBAR QBAR R G + I5 P QBAR R G + I6 PBAR Q R G + I7 P Q R G + ZBAR + D_AC151_3 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U55 inv DPWR DGND + EBAR_BUF H + D_AC151_1 IO_AC MNTYMXDLY={MNTYMXDLY} U66 bufa(3) DPWR DGND + S0_BUF S1_BUF S2_BUF L M N + D_AC151_2 IO_AC MNTYMXDLY={MNTYMXDLY} U77 inva(3) DPWR DGND + S0_BUF S1_BUF S2_BUF LBAR MBAR NBAR + D_AC151_2 IO_AC U88 ao(5,8) DPWR DGND + I0 LBAR MBAR NBAR H + I1 L MBAR NBAR H + I2 LBAR M NBAR H + I3 L M NBAR H + I4 LBAR MBAR N H + I5 L MBAR N H + I6 LBAR M N H + I7 L M N H + Z + D_AC151_3 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC151_1 ugate ( + tplhmn=1ns tplhty=6ns + tplhmx=11ns tphlmn=1ns + tphlty=6.5ns tphlmx=11ns + ) .model D_AC151_2 ugate ( + tplhmn=1ns tplhty=8.5ns + tplhmx=15ns tphlmn=1ns + tphlty=8.5ns tphlmx=15ns + ) .model D_AC151_3 ugate ( + tplhmn=1ns tplhty=7ns + tplhmx=11ns tphlmn=1ns + tphlty=7ns tphlmx=12ns + ) *--------- * 74ACT151 Data Selectors/Multiplexers * * The FACT Data Book, 1987, FAIRCHILD * cv 06/22/90 Created from LS .subckt 74ACT151 EBAR S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 Z ZBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + EBAR S0 S1 S2 EBAR_BUF S0_BUF S1_BUF S2_BUF + D0_GATE IO_ACT IO_LEVEL={IO_LEVEL} U11 inv DPWR DGND + EBAR_BUF G + D_ACT151_1 IO_ACT MNTYMXDLY={MNTYMXDLY} U22 bufa(3) DPWR DGND + S0_BUF S1_BUF S2_BUF P Q R + D_ACT151_2 IO_ACT MNTYMXDLY={MNTYMXDLY} U33 inva(3) DPWR DGND + S0_BUF S1_BUF S2_BUF PBAR QBAR RBAR + D_ACT151_2 IO_ACT MNTYMXDLY={MNTYMXDLY} U44 aoi(5,8) DPWR DGND + I0 PBAR QBAR RBAR G + I1 P QBAR RBAR G + I2 PBAR Q RBAR G + I3 P Q RBAR G + I4 PBAR QBAR R G + I5 P QBAR R G + I6 PBAR Q R G + I7 P Q R G + ZBAR + D_ACT151_3 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U55 inv DPWR DGND + EBAR_BUF H + D_ACT151_4 IO_ACT MNTYMXDLY={MNTYMXDLY} U66 bufa(3) DPWR DGND + S0_BUF S1_BUF S2_BUF L M N + D_ACT151_5 IO_ACT MNTYMXDLY={MNTYMXDLY} U77 inva(3) DPWR DGND + S0_BUF S1_BUF S2_BUF LBAR MBAR NBAR + D_ACT151_5 IO_ACT MNTYMXDLY={MNTYMXDLY} U88 ao(5,8) DPWR DGND + I0 LBAR MBAR NBAR H + I1 L MBAR NBAR H + I2 LBAR M NBAR H + I3 L M NBAR H + I4 LBAR MBAR N H + I5 L MBAR N H + I6 LBAR M N H + I7 L M N H + Z + D_ACT151_6 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT151_1 ugate ( + tplhmn=1ns tplhmx=9.5ns + tphlmn=1ns tphlty=10.5ns + tphlmx=10.5ns + ) .model D_ACT151_2 ugate ( + tplhmn=1ns tplhty=12.5ns + tplhmx=16.5ns tphlmn=1ns + tphlty=12.5ns tphlmx=18.5ns + ) .model D_ACT151_3 ugate ( + tplhmn=1ns tplhty=11ns + tplhmx=13ns tphlmn=1ns + tphlty=11ns tphlmx=14ns + ) .model D_ACT151_4 ugate ( + tplhmn=1ns tplhty=10ns + tplhmx=10ns tphlmn=1ns + tphlmx=10ns + ) .model D_ACT151_5 ugate ( + tplhmn=1ns tplhty=12.5ns + tplhmx=17ns tphlmn=1ns + tphlty=12.5ns tphlmx=16.5ns + ) .model D_ACT151_6 ugate ( + tplhmn=1ns tplhty=11ns + tplhmx=12.5ns tphlmn=1ns + tphlty=11ns tphlmx=13.5ns + ) *--------- * 74ALS151 Data Selectors/Multiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/28/89 Update interface and model names .subckt 74ALS151 GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 Y W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: For the ALS and AS models, propagation delay times caused by changes in * the strobe input may be slightly higher than the values listed in TTL * data books. UIBUF bufa(4) DPWR DGND + GBAR A B C GBAR_BUF A_BUF B_BUF C_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + GBAR_BUF G + D_ALS151_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U2 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_ALS151_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_ALS151_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U4 aoi(5,8) DPWR DGND + D0 PBAR QBAR RBAR G + D1 P QBAR RBAR G + D2 PBAR Q RBAR G + D3 P Q RBAR G + D4 PBAR QBAR R G + D5 P QBAR R G + D6 PBAR Q R G + D7 P Q R G + W + D_ALS151_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 inv DPWR DGND + GBAR_BUF H + D_ALS151_4 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U6 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF L M N + D_ALS151_5 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U7 inva(3) DPWR DGND + A_BUF B_BUF C_BUF LBAR MBAR NBAR + D_ALS151_5 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U8 ao(5,8) DPWR DGND + D0 LBAR MBAR NBAR H + D1 L MBAR NBAR H + D2 LBAR M NBAR H + D3 L M NBAR H + D4 LBAR MBAR N H + D5 L MBAR N H + D6 LBAR M N H + D7 L M N H + Y + D_ALS151_6 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS151_1 ugate ( + tplhmn=1ns tplhmx=8ns + tphlmn=2ns tphlmx=4ns + ) .model D_ALS151_2 ugate ( + tplhmn=3ns tplhmx=8ns + tphlmn=4ns tphlmx=9ns + ) .model D_ALS151_3 ugate ( + tplhmn=3ns tplhmx=15ns + tphlmn=4ns tphlmx=15ns + ) .model D_ALS151_4 ugate ( + tplhmn=1ns tplhmx=8ns + tphlmx=4ns + ) .model D_ALS151_5 ugate ( + tplhmn=1ns tplhmx=8ns + tphlmn=3ns tphlmx=9ns + ) .model D_ALS151_6 ugate ( + tplhmn=3ns tplhmx=10ns + tphlmn=5ns tphlmx=15ns + ) *--------- * 74AS151 Data Selectors/Multiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/28/89 Update interface and model names .subckt 74AS151 GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 Y W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: For the ALS and AS models, propagation delay times caused by changes in * the strobe input may be slightly higher than the values listed in TTL * data books. UIBUF bufa(4) DPWR DGND + GBAR A B C GBAR_BUF A_BUF B_BUF C_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + GBAR_BUF G + D_AS151_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U2 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_AS151_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + A B C PBAR QBAR RBAR + D_AS151_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} U4 aoi(5,8) DPWR DGND + D0 PBAR QBAR RBAR G + D1 P QBAR RBAR G + D2 PBAR Q RBAR G + D3 P Q RBAR G + D4 PBAR QBAR R G + D5 P QBAR R G + D6 PBAR Q R G + D7 P Q R G + W + D_AS151_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 inv DPWR DGND + GBAR_BUF H + D_AS151_4 IO_AS00 MNTYMXDLY={MNTYMXDLY} U6 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF L M N + D_AS151_5 IO_AS00 MNTYMXDLY={MNTYMXDLY} U7 inva(3) DPWR DGND + A B C LBAR MBAR NBAR + D_AS151_5 IO_AS00 MNTYMXDLY={MNTYMXDLY} U8 ao(5,8) DPWR DGND + D0 LBAR MBAR NBAR H + D1 L MBAR NBAR H + D2 LBAR M NBAR H + D3 L M NBAR H + D4 LBAR MBAR N H + D5 L MBAR N H + D6 LBAR M N H + D7 L M N H + Y + D_AS151_6 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS151_1 ugate ( + tplhmn=2ns tplhmx=5.5ns + ) .model D_AS151_2 ugate ( + tplhmn=3ns tplhmx=7.5ns + tphlmn=2ns tphlmx=5.5ns + ) .model D_AS151_3 ugate ( + tplhmn=2ns tplhmx=6.5ns + tphlmn=1ns tphlmx=4.5ns + ) .model D_AS151_4 ugate ( + tplhmn=1.5ns tplhmx=3.5ns + ) .model D_AS151_5 ugate ( + tplhmn=1.5ns tplhmx=4ns + tphlmn=1.5ns tphlmx=4ns + ) .model D_AS151_6 ugate ( + tplhmn=3ns tplhmx=10.5ns + tphlmn=3ns tphlmx=11ns + ) *--------- * 74F151 Data Selectors/Multiplexers * * The F Logic Data Book, 1987, TI * tdn 07/28/89 Update interface and model names .subckt 74F151 GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 Y W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + GBAR A B C GBAR_BUF A_BUF B_BUF C_BUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + GBAR_BUF G + D_F151_1 IO_F MNTYMXDLY={MNTYMXDLY} U2 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_F151_2 IO_F MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_F151_2 IO_F MNTYMXDLY={MNTYMXDLY} U4 aoi(5,8) DPWR DGND + D0 PBAR QBAR RBAR G + D1 P QBAR RBAR G + D2 PBAR Q RBAR G + D3 P Q RBAR G + D4 PBAR QBAR R G + D5 P QBAR R G + D6 PBAR Q R G + D7 P Q R G + W + D_F151_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 inv DPWR DGND + GBAR_BUF H + D_F151_4 IO_F MNTYMXDLY={MNTYMXDLY} U6 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF L M N + D_F151_5 IO_F MNTYMXDLY={MNTYMXDLY} U7 inva(3) DPWR DGND + A_BUF B_BUF C_BUF LBAR MBAR NBAR + D_F151_5 IO_F MNTYMXDLY={MNTYMXDLY} U8 ao(5,8) DPWR DGND + D0 LBAR MBAR NBAR H + D1 L MBAR NBAR H + D2 LBAR M NBAR H + D3 L M NBAR H + D4 LBAR MBAR N H + D5 L MBAR N H + D6 LBAR M N H + D7 L M N H + Y + D_F151_6 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F151_1 ugate ( + tplhmn=2.7ns tplhty=4.5ns + tplhmx=4ns tphlmn=0.5ns + tphlty=0.5ns tphlmx=1ps + ) .model D_F151_2 ugate ( + tplhmn=1.2ns tplhty=2.5ns + tplhmx=2ns tphlmn=1.5ns + tphlty=2.5ns tphlmx=4ns + ) .model D_F151_3 ugate ( + tplhmn=2.2ns tplhty=4.1ns + tplhmx=7ns tphlmn=1ns + tphlty=2.1ns tphlmx=5ns + ) .model D_F151_4 ugate ( + tplhmn=0.5ns tplhty=2ns + tplhmx=1.5ns tphlty=0.5ns + tphlmx=0.5ns + ) .model D_F151_5 ugate ( + tplhmn=0.5ns tplhty=2ns + tplhmx=3ns tphlmn=0.5ns + tphlty=2.5ns tphlmx=5ns + ) .model D_F151_6 ugate ( + tplhmn=3.2ns tplhty=5.6ns + tplhmx=11ns tphlmn=3.2ns + tphlty=5.1ns tphlmx=8ns + ) *--------- * 74HC151 Data Selectors/Multiplexers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/28/89 Update interface and model names .subckt 74HC151 GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 Y W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + GBAR A B C GBAR_BUF A_BUF B_BUF C_BUF + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U1 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_HC151_3 IO_HC MNTYMXDLY={MNTYMXDLY} U2 inva(3) DPWR DGND + P Q R PBAR QBAR RBAR + D0_GATE IO_HC U3 aoi(4,8) DPWR DGND + D0 PBAR QBAR RBAR + D1 P QBAR RBAR + D2 PBAR Q RBAR + D3 P Q RBAR + D4 PBAR QBAR R + D5 P QBAR R + D6 PBAR Q R + D7 P Q R + J + D_HC151_2 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 or(2) DPWR DGND + GBAR_BUF J W + D_HC151_1 IO_HC MNTYMXDLY={MNTYMXDLY} U5 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF L M N + D_HC151_3 IO_HC MNTYMXDLY={MNTYMXDLY} U6 inva(3) DPWR DGND + L M N LBAR MBAR NBAR + D0_GATE IO_HC U7 aoi(4,8) DPWR DGND + D0 LBAR MBAR NBAR + D1 L MBAR NBAR + D2 LBAR M NBAR + D3 L M NBAR + D4 LBAR MBAR N + D5 L MBAR N + D6 LBAR M N + D7 L M N + K + D_HC151_2 IO_HC MNTYMXDLY={MNTYMXDLY} U8 nor(2) DPWR DGND + GBAR_BUF K Y + D_HC151_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC151_1 ugate ( + tplhty=15ns tplhmx=32ns + tphlty=15ns tphlmx=32ns + ) .model D_HC151_2 ugate ( + tplhty=8ns tplhmx=17ns + tphlty=8ns tphlmx=17ns + ) .model D_HC151_3 ugate ( + tplhty=7ns tplhmx=14ns + tphlty=7ns tphlmx=14ns + ) *--------- * 74LS151 Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/28/89 Update interface and model names .subckt 74LS151 GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 Y W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + GBAR A B C GBAR_BUF A_BUF B_BUF C_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + GBAR_BUF G + D_LS151_1 IO_LS MNTYMXDLY={MNTYMXDLY} U2 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_LS151_2 IO_LS MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_LS151_2 IO_LS MNTYMXDLY={MNTYMXDLY} U4 aoi(5,8) DPWR DGND + D0 PBAR QBAR RBAR G + D1 P QBAR RBAR G + D2 PBAR Q RBAR G + D3 P Q RBAR G + D4 PBAR QBAR R G + D5 P QBAR R G + D6 PBAR Q R G + D7 P Q R G + W + D_LS151_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 inv DPWR DGND + GBAR_BUF H + D_LS151_4 IO_LS MNTYMXDLY={MNTYMXDLY} U6 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF L M N + D_LS151_5 IO_LS MNTYMXDLY={MNTYMXDLY} U7 inva(3) DPWR DGND + A_BUF B_BUF C_BUF LBAR MBAR NBAR + D_LS151_5 IO_LS MNTYMXDLY={MNTYMXDLY} U8 ao(5,8) DPWR DGND + D0 LBAR MBAR NBAR H + D1 L MBAR NBAR H + D2 LBAR M NBAR H + D3 L M NBAR H + D4 LBAR MBAR N H + D5 L MBAR N H + D6 LBAR M N H + D7 L M N H + Y + D_LS151_6 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS151_1 ugate ( + tplhty=6ns tplhmx=10ns + tphlty=2ns tphlmx=3ns + ) .model D_LS151_2 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=1ns tphlmx=2ns + ) .model D_LS151_3 ugate ( + tplhty=13ns tplhmx=21ns + tphlty=12ns tphlmx=20ns + ) .model D_LS151_4 ugate ( + tplhty=6ns tplhmx=10ns + tphlty=4ns tphlmx=6ns + ) .model D_LS151_5 ugate ( + tplhty=7ns tplhmx=11ns + tphlty=2ns tphlmx=4ns + ) .model D_LS151_6 ugate ( + tplhty=20ns tplhmx=32ns + tphlty=16ns tphlmx=26ns + ) *--------- * 74S151 Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/28/89 Update interface and model names .subckt 74S151 GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 Y W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + GBAR A B C GBAR_BUF A_BUF B_BUF C_BUF + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + GBAR_BUF G + D_S151_1 IO_S MNTYMXDLY={MNTYMXDLY} U2 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_S151_2 IO_S MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_S151_2 IO_S MNTYMXDLY={MNTYMXDLY} U4 aoi(5,8) DPWR DGND + D0 PBAR QBAR RBAR G + D1 P QBAR RBAR G + D2 PBAR Q RBAR G + D3 P Q RBAR G + D4 PBAR QBAR R G + D5 P QBAR R G + D6 PBAR Q R G + D7 P Q R G + W + D_S151_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 inv DPWR DGND + GBAR_BUF H + D_S151_4 IO_S MNTYMXDLY={MNTYMXDLY} U6 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF L M N + D_S151_5 IO_S MNTYMXDLY={MNTYMXDLY} U7 inva(3) DPWR DGND + A_BUF B_BUF C_BUF LBAR MBAR NBAR + D_S151_5 IO_S MNTYMXDLY={MNTYMXDLY} U8 ao(5,8) DPWR DGND + D0 LBAR MBAR NBAR H + D1 L MBAR NBAR H + D2 LBAR M NBAR H + D3 L M NBAR H + D4 LBAR MBAR N H + D5 L MBAR N H + D6 LBAR M N H + D7 L M N H + Y + D_S151_6 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S151_1 ugate ( + tplhty=4ns tplhmx=5ns + tphlty=4.5ns tphlmx=6ns + ) .model D_S151_2 ugate ( + tplhty=4.5ns tplhmx=6.5ns + tphlty=5.5ns tphlmx=8ns + ) .model D_S151_3 ugate ( + tplhty=4.5ns tplhmx=7ns + tphlty=4.5ns tphlmx=7ns + ) .model D_S151_4 ugate ( + tplhty=3ns tplhmx=4.5ns + tphlty=4ns tphlmx=6ns + ) .model D_S151_5 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=4ns tphlmx=6ns + ) .model D_S151_6 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=8ns tphlmx=12ns + ) *------------------------------------------------------------------------- * 54152A Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 54152A A B C D0 D1 D2 D3 D4 D5 D6 D7 W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_152_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_152_1 IO_STD MNTYMXDLY={MNTYMXDLY} U3 aoi(4,8) DPWR DGND + D0 PBAR QBAR RBAR + D1 P QBAR RBAR + D2 PBAR Q RBAR + D3 P Q RBAR + D4 PBAR QBAR R + D5 P QBAR R + D6 PBAR Q R + D7 P Q R + W + D_152_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_152_1 ugate ( + tplhty=11ns tplhmx=16ns + tphlty=9ns tphlmx=12ns + ) .model D_152_2 ugate ( + tplhty=8ns tplhmx=14ns + tphlty=8ns tphlmx=14ns + ) *--------- * 74HC152 Data Selectors/Multiplexers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/06/89 Update interface and model names .subckt 74HC152 A B C D0 D1 D2 D3 D4 D5 D6 D7 W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + A B C P Q R + D_HC152_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(3) DPWR DGND + P Q R PBAR QBAR RBAR + D0_GATE IO_HC U3 aoi(4,8) DPWR DGND + D0 PBAR QBAR RBAR + D1 P QBAR RBAR + D2 PBAR Q RBAR + D3 P Q RBAR + D4 PBAR QBAR R + D5 P QBAR R + D6 PBAR Q R + D7 P Q R + W + D_HC152_2 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC152_1 ugate ( + tplhty=4ns tplhmx=10ns + tphlty=4ns tphlmx=10ns + ) .model D_HC152_2 ugate ( + tplhty=14ns tplhmx=33ns + tphlty=14ns tphlmx=33ns + ) *--------- * 54LS152 Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 54LS152 A B C D0 D1 D2 D3 D4 D5 D6 D7 W + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(3) DPWR DGND + A B C A_BUF B_BUF C_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 bufa(3) DPWR DGND + A_BUF B_BUF C_BUF P Q R + D_LS152_1 IO_LS MNTYMXDLY={MNTYMXDLY} U2 inva(3) DPWR DGND + A_BUF B_BUF C_BUF PBAR QBAR RBAR + D_LS152_1 IO_LS MNTYMXDLY={MNTYMXDLY} U3 aoi(4,8) DPWR DGND + D0 PBAR QBAR RBAR + D1 P QBAR RBAR + D2 PBAR Q RBAR + D3 P Q RBAR + D4 PBAR QBAR R + D5 P QBAR R + D6 PBAR Q R + D7 P Q R + W + D_LS152_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS152_1 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=1ns tphlmx=2ns + ) .model D_LS152_2 ugate ( + tplhty=13ns tplhmx=21ns + tphlty=12ns tphlmx=20ns + ) *------------------------------------------------------------------------- * 74153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74153 G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_153_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_153_1 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D_153_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(4,4) DPWR DGND + 1C0 PBAR QBAR G1 + 1C1 P QBAR G1 + 1C2 PBAR Q G1 + 1C3 P Q G1 + Y1 + D_153_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(4,4) DPWR DGND + 2C0 PBAR QBAR G2 + 2C1 P QBAR G2 + 2C2 PBAR Q G2 + 2C3 P Q G2 + Y2 + D_153_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_153_1 ugate ( + tplhty=10ns tplhmx=16ns + tphlty=7ns tphlmx=11ns + ) .model D_153_2 ugate ( + tplhty=7ns tplhmx=12ns + ) .model D_153_3 ugate ( + tplhty=12ns tplhmx=18ns + tphlty=15ns tphlmx=23ns + ) *--------- * 74AC153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The FACT Data Book, 1987, FAIRCHILD * cv 06/22/90 Created from LS .subckt 74AC153 EABAR EBBAR S0 S1 I0A I1A I2A I3A I0B I1B I2B I3B ZA ZB + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + S0 S1 S0_BUF S1_BUF + D0_GATE IO_AC IO_LEVEL={IO_LEVEL} U11 bufa(2) DPWR DGND + S0_BUF S1_BUF P Q + D_AC153_1 IO_AC MNTYMXDLY={MNTYMXDLY} U22 inva(2) DPWR DGND + S0_BUF S1_BUF PBAR QBAR + D_AC153_1 IO_AC MNTYMXDLY={MNTYMXDLY} U33 inva(2) DPWR DGND + EABAR EBBAR G1 G2 + D_AC153_2 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U44 ao(4,4) DPWR DGND + I0A PBAR QBAR G1 + I1A P QBAR G1 + I2A PBAR Q G1 + I3A P Q G1 + ZA + D_AC153_3 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U55 ao(4,4) DPWR DGND + I0B PBAR QBAR G2 + I1B P QBAR G2 + I2B PBAR Q G2 + I3B P Q G2 + ZB + D_AC153_3 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC153_1 ugate ( + tplhmn=1ns tplhty=6.5ns + tplhmx=12.5ns tphlmn=1ns + tphlty=6.5ns tphlmx=12ns + ) .model D_AC153_2 ugate ( + tplhmn=1ns tplhty=5.5ns + tplhmx=11ns tphlmn=1ns + tphlty=5ns tphlmx=9ns + ) .model D_AC153_3 ugate ( + tplhmn=1ns tplhty=5.5ns + tplhmx=10.5ns tphlmn=1ns + tphlty=5ns tphlmx=10ns + ) *--------- * 74ACT153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The FACT Data Book, 1987, FAIRCHILD * cv 06/22/90 Created from LS .subckt 74ACT153 EABAR EBBAR S0 S1 I0A I1A I2A I3A I0B I1B I2B I3B ZA ZB + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + S0 S1 S0_BUF S1_BUF + D0_GATE IO_ACT IO_LEVEL={IO_LEVEL} U11 bufa(2) DPWR DGND + S0_BUF S1_BUF P Q + D_ACT153_1 IO_ACT MNTYMXDLY={MNTYMXDLY} U22 inva(2) DPWR DGND + S0_BUF S1_BUF PBAR QBAR + D_ACT153_1 IO_ACT MNTYMXDLY={MNTYMXDLY} U33 inva(2) DPWR DGND + EABAR EBBAR G1 G2 + D_ACT153_2 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U44 ao(4,4) DPWR DGND + I0A PBAR QBAR G1 + I1A P QBAR G1 + I2A PBAR Q G1 + I3A P Q G1 + ZA + D_ACT153_3 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U55 ao(4,4) DPWR DGND + I0B PBAR QBAR G2 + I1B P QBAR G2 + I2B PBAR Q G2 + I3B P Q G2 + ZB + D_ACT153_3 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT153_1 ugate ( + tplhmn=1ns tplhty=7ns + tplhmx=13.5ns tphlmn=1ns + tphlty=7ns tphlmx=13.5ns + ) .model D_ACT153_2 ugate ( + tplhmn=1ns tplhty=6.5ns + tplhmx=12.5ns tphlmn=1ns + tphlty=6ns tphlmx=11ns + ) .model D_ACT153_3 ugate ( + tplhmn=1ns tplhty=5.5ns + tplhmx=11ns tphlmn=1ns + tphlty=5.5ns tphlmx=11ns + ) *--------- * 74ALS153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/06/89 Update interface and model names .subckt 74ALS153 G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_ALS153_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U2 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_ALS153_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D_ALS153_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(4,4) DPWR DGND + 1C0 PBAR QBAR G1 + 1C1 P QBAR G1 + 1C2 PBAR Q G1 + 1C3 P Q G1 + Y1 + D_ALS153_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(4,4) DPWR DGND + 2C0 PBAR QBAR G2 + 2C1 P QBAR G2 + 2C2 PBAR Q G2 + 2C3 P Q G2 + Y2 + D_ALS153_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS153_1 ugate ( + tplhmn=2ns tplhmx=11ns + tphlmn=1ns tphlmx=6ns + ) .model D_ALS153_2 ugate ( + tplhmn=2ns tplhmx=8ns + tphlmn=1ns tphlmx=3ns + ) .model D_ALS153_3 ugate ( + tplhmn=3ns tplhmx=10ns + tphlmn=4ns tphlmx=15ns + ) *--------- * 74AS153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/06/89 Update interface and model names .subckt 74AS153 G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_AS153_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U2 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_AS153_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D_AS153_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(4,4) DPWR DGND + 1C0 PBAR QBAR G1 + 1C1 P QBAR G1 + 1C2 PBAR Q G1 + 1C3 P Q G1 + Y1 + D_AS153_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(4,4) DPWR DGND + 2C0 PBAR QBAR G2 + 2C1 P QBAR G2 + 2C2 PBAR Q G2 + 2C3 P Q G2 + Y2 + D_AS153_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS153_1 ugate ( + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=3ns + ) .model D_AS153_2 ugate ( + tplhmn=1ns tplhmx=4.5ns + tphlmx=1ns + ) .model D_AS153_3 ugate ( + tplhmn=2ns tplhmx=7ns + tphlmn=2ns tphlmx=8ns + ) *--------- * 74F153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The F Logic Data Book, 1987, TI * tdn 07/06/89 Update interface and model names .subckt 74F153 G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_F153_1 IO_F MNTYMXDLY={MNTYMXDLY} U2 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_F153_1 IO_F MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D_F153_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(4,4) DPWR DGND + 1C0 PBAR QBAR G1 + 1C1 P QBAR G1 + 1C2 PBAR Q G1 + 1C3 P Q G1 + Y1 + D_F153_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(4,4) DPWR DGND + 2C0 PBAR QBAR G2 + 2C1 P QBAR G2 + 2C2 PBAR Q G2 + 2C3 P Q G2 + Y2 + D_F153_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F153_1 ugate ( + tplhmn=1.5ns tplhty=2.8ns + tplhmx=4ns tphlmn=1ns + tphlty=1.9ns tphlmx=3ns + ) .model D_F153_2 ugate ( + tplhmn=1.5ns tplhty=1.8ns + tplhmx=2.5ns tphlty=0.6ns + tphlmx=0.5ns + ) .model D_F153_3 ugate ( + tplhmn=2.2ns tplhty=4.9ns + tplhmx=8ns tphlmn=1.7ns + tphlty=4.7ns tphlmx=7.5ns + ) *--------- * 74HC153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/06/89 Update interface and model names .subckt 74HC153 G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U1 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_HC153_1 IO_HC MNTYMXDLY={MNTYMXDLY} U2 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_HC153_1 IO_HC MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D_HC153_2 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,4) DPWR DGND + 1C0 PBAR QBAR + 1C1 P QBAR + 1C2 PBAR Q + 1C3 P Q + J1 + D_HC153_3 IO_HC MNTYMXDLY={MNTYMXDLY} U5 ao(3,4) DPWR DGND + 2C0 PBAR QBAR + 2C1 P QBAR + 2C2 PBAR Q + 2C3 P Q + J2 + D_HC153_3 IO_HC MNTYMXDLY={MNTYMXDLY} U6 anda(2,2) DPWR DGND + J1 G1 J2 G2 Y1 Y2 + D_HC153_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC153_1 ugate ( + tplhty=4ns tplhmx=3ns + tphlty=4ns tphlmx=3ns + ) .model D_HC153_2 ugate ( + tplhty=07ns tplhmx=20ns + tphlty=07ns tphlmx=20ns + ) .model D_HC153_3 ugate ( + tplhty=13ns tplhmx=31ns + tphlty=13ns tphlmx=31ns + ) .model D_HC153_4 ugate ( + tplhty=4ns tplhmx=4ns + tphlty=4ns tphlmx=4ns + ) *--------- * 54L153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 54L153 G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_L153_1 IO_L MNTYMXDLY={MNTYMXDLY} U2 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_L153_1 IO_L MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D_L153_2 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(4,4) DPWR DGND + 1C0 PBAR QBAR G1 + 1C1 P QBAR G1 + 1C2 PBAR Q G1 + 1C3 P Q G1 + Y1 + D_L153_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(4,4) DPWR DGND + 2C0 PBAR QBAR G2 + 2C1 P QBAR G2 + 2C2 PBAR Q G2 + 2C3 P Q G2 + Y2 + D_L153_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L153_1 ugate ( + tplhty=20ns tplhmx=32ns + tphlty=14ns tphlmx=22ns + ) .model D_L153_2 ugate ( + tplhty=14ns tplhmx=24ns + ) .model D_L153_3 ugate ( + tplhty=24ns tplhmx=36ns + tphlty=30ns tphlmx=46ns + ) *--------- * 74LS153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74LS153 G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_LS153_1 IO_LS MNTYMXDLY={MNTYMXDLY} U2 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_LS153_1 IO_LS MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D_LS153_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(4,4) DPWR DGND + 1C0 PBAR QBAR G1 + 1C1 P QBAR G1 + 1C2 PBAR Q G1 + 1C3 P Q G1 + Y1 + D_LS153_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(4,4) DPWR DGND + 2C0 PBAR QBAR G2 + 2C1 P QBAR G2 + 2C2 PBAR Q G2 + 2C3 P Q G2 + Y2 + D_LS153_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS153_1 ugate ( + tplhty=9ns tplhmx=14ns + tphlty=8ns tphlmx=12ns + ) .model D_LS153_2 ugate ( + tplhty=6ns tplhmx=9ns + tphlty=4ns tphlmx=6ns + ) .model D_LS153_3 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=17ns tphlmx=26ns + ) *--------- * 74S153 Dual 4-line to 1-line Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74S153 G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U1 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_S153_1 IO_S MNTYMXDLY={MNTYMXDLY} U2 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_S153_1 IO_S MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D_S153_2 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(4,4) DPWR DGND + 1C0 PBAR QBAR G1 + 1C1 P QBAR G1 + 1C2 PBAR Q G1 + 1C3 P Q G1 + Y1 + D_S153_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(4,4) DPWR DGND + 2C0 PBAR QBAR G2 + 2C1 P QBAR G2 + 2C2 PBAR Q G2 + 2C3 P Q G2 + Y2 + D_S153_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S153_1 ugate ( + tplhty=5.5ns tplhmx=9ns + tphlty=6ns tphlmx=9ns + ) .model D_S153_2 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=3ns tphlmx=4.5ns + ) .model D_S153_3 ugate ( + tplhty=6ns tplhmx=9ns + tphlty=6ns tphlmx=9ns + ) *------------------------------------------------------------------------- * 74154 4-line to 16-line Decoders/Demultiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74154 G1BAR G2BAR A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 + Y13 Y14 Y15 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 nor(2) DPWR DGND + G1BAR G2BAR G + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_154_1 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D_154_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 nanda(5,16) DPWR DGND + PBAR QBAR RBAR SBAR G + P QBAR RBAR SBAR G + PBAR Q RBAR SBAR G + P Q RBAR SBAR G + PBAR QBAR R SBAR G + P QBAR R SBAR G + PBAR Q R SBAR G + P Q R SBAR G + PBAR QBAR RBAR S G + P QBAR RBAR S G + PBAR Q RBAR S G + P Q RBAR S G + PBAR QBAR R S G + P QBAR R S G + PBAR Q R S G + P Q R S G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 + D_154_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_154_1 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=4ns tphlmx=6ns + ) .model D_154_2 ugate ( + tplhty=20ns tplhmx=30ns + tphlty=18ns tphlmx=27ns + ) *--------- * 74HC154 4-line to 16-line Decoders/Demultiplexers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/06/89 Update interface and model names .subckt 74HC154 G1BAR G2BAR A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 + Y13 Y14 Y15 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + G1BAR G2BAR G + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + A B C D P Q R S + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U3 inva(4) DPWR DGND + P Q R S PBAR QBAR RBAR SBAR + D0_GATE IO_HC IO_LEVEL={IO_LEVEL} U4 nanda(5,16) DPWR DGND + PBAR QBAR RBAR SBAR G + P QBAR RBAR SBAR G + PBAR Q RBAR SBAR G + P Q RBAR SBAR G + PBAR QBAR R SBAR G + P QBAR R SBAR G + PBAR Q R SBAR G + P Q R SBAR G + PBAR QBAR RBAR S G + P QBAR RBAR S G + PBAR Q RBAR S G + P Q RBAR S G + PBAR QBAR R S G + P QBAR R S G + PBAR Q R S G + P Q R S G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 + D_HC154 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC154 ugate ( + tplhty=24ns tplhmx=45ns + tphlty=24ns tphlmx=45ns + ) *--------- * 54L154 4-line to 16-line Decoders/Demultiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 54L154 G1BAR G2BAR A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 + Y13 Y14 Y15 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 nor(2) DPWR DGND + G1BAR G2BAR G + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_L154_1 IO_L MNTYMXDLY={MNTYMXDLY} U3 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D_L154_1 IO_L MNTYMXDLY={MNTYMXDLY} U4 nanda(5,16) DPWR DGND + PBAR QBAR RBAR SBAR G + P QBAR RBAR SBAR G + PBAR Q RBAR SBAR G + P Q RBAR SBAR G + PBAR QBAR R SBAR G + P QBAR R SBAR G + PBAR Q R SBAR G + P Q R SBAR G + PBAR QBAR RBAR S G + P QBAR RBAR S G + PBAR Q RBAR S G + P Q RBAR S G + PBAR QBAR R S G + P QBAR R S G + PBAR Q R S G + P Q R S G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 + D_L154_2 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L154_1 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=8ns tphlmx=12ns + ) .model D_L154_2 ugate ( + tplhty=40ns tplhmx=60ns + tphlty=36ns tphlmx=54ns + ) *------------------------------------------------------------------------- * 74155 Dual 2-line to 4-line Decoders/Demultiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74155 G1BAR G2BAR A B C1 C2BAR 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + C1 C1BAR + D_155_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 nora(2,2) DPWR DGND + G1BAR C1BAR G2BAR C2BAR H1 H2 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_155_2 IO_STD MNTYMXDLY={MNTYMXDLY} U4 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D0_GATE IO_STD U5 nanda(3,8) DPWR DGND + PBAR QBAR H1 + P QBAR H1 + PBAR Q H1 + P Q H1 + PBAR QBAR H2 + P QBAR H2 + PBAR Q H2 + P Q H2 + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + D_155_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_155_1 ugate ( + tplhty=3ns tplhmx=4ns + tphlty=2ns tphlmx=3ns + ) .model D_155_2 ugate ( + tplhty=3ns tplhmx=5ns + tphlty=8ns tphlmx=12ns + ) .model D_155_3 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=18ns tphlmx=27ns + ) *--------- * 74LS155A Dual 2-line to 4-line Decoders/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74LS155A G1BAR G2BAR A B C1 C2BAR 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + C1 D + D_LS155A_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(3) DPWR DGND + G1BAR G2BAR C2BAR G1 G2 C2 + D_LS155A_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 anda(2,2) DPWR DGND + G1 D G2 C2 H1 H2 + D0_GATE IO_LS U4 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_LS155A_3 IO_LS MNTYMXDLY={MNTYMXDLY} U5 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_LS155A_2 IO_LS MNTYMXDLY={MNTYMXDLY} U6 nanda(3,8) DPWR DGND + PBAR QBAR H1 + P QBAR H1 + PBAR Q H1 + P Q H1 + PBAR QBAR H2 + P QBAR H2 + PBAR Q H2 + P Q H2 + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + D_LS155A_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS155A_1 ugate ( + tphlty=8ns tphlmx=12ns + ) .model D_LS155A_2 ugate ( + tplhty=1ns tplhmx=3ns + ) .model D_LS155A_3 ugate ( + tplhty=1ns tplhmx=3ns + tphlty=7ns tphlmx=11ns + ) .model D_LS155A_4 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=18ns tphlmx=27ns + ) *------------------------------------------------------------------------- * 74156 Dual 2-line to 4-line Decoders/Demultiplexers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74156 G1BAR G2BAR A B C1 C2BAR 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + C1 D + D_156_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(3) DPWR DGND + G1BAR G2BAR C2BAR G1 G2 C2 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 anda(2,2) DPWR DGND + G1 D G2 C2 H1 H2 + D0_GATE IO_STD U4 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_156_2 IO_STD MNTYMXDLY={MNTYMXDLY} U5 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D0_GATE IO_STD U6 nanda(3,8) DPWR DGND + PBAR QBAR H1 + P QBAR H1 + PBAR Q H1 + P Q H1 + PBAR QBAR H2 + P QBAR H2 + PBAR Q H2 + P Q H2 + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + D_156_3 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_156_1 ugate ( + tplhty=2ns tplhmx=3ns + tphlty=3ns tphlmx=4ns + ) .model D_156_2 ugate ( + tplhty=3ns tplhmx=4ns + tphlty=8ns tphlmx=11ns + ) .model D_156_3 ugate ( + tplhty=15ns tplhmx=23ns + tphlty=20ns tphlmx=30ns + ) *--------- * 74LS156 Dual 2-line to 4-line Decoders/Demultiplexers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74LS156 G1BAR G2BAR A B C1 C2BAR 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + C1 D + D_LS156_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(3) DPWR DGND + G1BAR G2BAR C2BAR G1 G2 C2 + D_LS156_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 anda(2,2) DPWR DGND + G1 D G2 C2 H1 H2 + D0_GATE IO_LS U4 bufa(2) DPWR DGND + A_BUF B_BUF P Q + D_LS156_3 IO_LS MNTYMXDLY={MNTYMXDLY} U5 inva(2) DPWR DGND + A_BUF B_BUF PBAR QBAR + D_LS156_2 IO_LS MNTYMXDLY={MNTYMXDLY} U6 nanda(3,8) DPWR DGND + PBAR QBAR H1 + P QBAR H1 + PBAR Q H1 + P Q H1 + PBAR QBAR H2 + P QBAR H2 + PBAR Q H2 + P Q H2 + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + D_LS156_4 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS156_1 ugate ( + tphlty=7ns tphlmx=8ns + ) .model D_LS156_2 ugate ( + tplhty=2ns tplhmx=3ns + ) .model D_LS156_3 ugate ( + tplhty=2ns tplhmx=3ns + tphlty=6ns tphlmx=6ns + ) .model D_LS156_4 ugate ( + tplhty=25ns tplhmx=40ns + tphlty=32ns tphlmx=48ns + ) *------------------------------------------------------------------------- * 74157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74157 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_157_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_157_1 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_157_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_157_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_157_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_157_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_157_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_157_1 ugate ( + tplhty=6ns tplhmx=9ns + tphlty=9ns tphlmx=13ns + ) .model D_157_2 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=5ns tphlmx=7ns + ) .model D_157_3 ugate ( + tplhty=9ns tplhmx=14ns + tphlty=9ns tphlmx=14ns + ) *--------- * 74AC157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The FACT Data Book, 1987, FAIRCHILD * cv 06/25/90 Created from LS .subckt 74AC157 EBAR I0A I1A I0B I1B I0C I1C I0D I1D S ZA ZB ZC ZD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF buf DPWR DGND + S SB + D0_GATE IO_AC IO_LEVEL={IO_LEVEL} U11 buf DPWR DGND + SB D + D_AC157_1 IO_AC MNTYMXDLY={MNTYMXDLY} U22 inv DPWR DGND + SB DBAR + D_AC157_1 IO_AC MNTYMXDLY={MNTYMXDLY} U33 inv DPWR DGND + EBAR G + D_AC157_2 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + I0A DBAR G I1A D G ZA + D_AC157_3 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + I0B DBAR G I1B D G ZB + D_AC157_3 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + I0C DBAR G I1C D G ZC + D_AC157_3 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + I0D DBAR G I1D D G ZD + D_AC157_3 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AC157_1 ugate ( + tplhmn=1ns tplhty=5.5ns + tplhmx=10ns tphlmn=1ns + tphlty=5ns tphlmx=9.5ns + ) .model D_AC157_2 ugate ( + tplhmn=1ns tplhty=5.5ns + tplhmx=10ns tphlmn=1ns + tphlty=5.5ns tphlmx=9.5ns + ) .model D_AC157_3 ugate ( + tplhmn=1ns tplhty=4ns + tplhmx=7ns tphlmn=1ns + tphlty=4ns tphlmx=7ns + ) *--------- * 74ACT157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The FACT Data Book, 1987, FAIRCHILD * cv 06/25/90 Created from LS .subckt 74ACT157 EBAR I0A I1A I0B I1B I0C I1C I0D I1D S ZA ZB ZC ZD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF buf DPWR DGND + S SB + D0_GATE IO_ACT IO_LEVEL={IO_LEVEL} U11 buf DPWR DGND + SB D + D_ACT157_1 IO_ACT MNTYMXDLY={MNTYMXDLY} U22 inv DPWR DGND + SB DBAR + D_ACT157_1 IO_ACT MNTYMXDLY={MNTYMXDLY} U33 inv DPWR DGND + EBAR G + D_ACT157_2 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + I0A DBAR G I1A D G ZA + D_ACT157_3 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + I0B DBAR G I1B D G ZB + D_ACT157_3 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + I0C DBAR G I1C D G ZC + D_ACT157_3 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + I0D DBAR G I1D D G ZD + D_ACT157_3 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ACT157_1 ugate ( + tplhmn=1ns tplhty=5.5ns + tplhmx=10ns tphlmn=1ns + tphlty=5.5ns tphlmx=10.5ns + ) .model D_ACT157_2 ugate ( + tplhmn=1ns tplhty=6ns + tplhmx=11.5ns tphlmn=1ns + tphlty=5ns tphlmx=9ns + ) .model D_ACT157_3 ugate ( + tplhmn=1ns tplhty=4ns + tplhmx=8.5ns tphlmn=1ns + tphlty=4.5ns tphlmx=8.5ns + ) *--------- * 74ALS157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/06/89 Update interface and model names .subckt 74ALS157 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_ALS157_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_ALS157_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_ALS157_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_ALS157_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_ALS157_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_ALS157_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_ALS157_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS157_1 ugate ( + tplhmn=3ns tplhty=6ns + tplhmx=10ns tphlmn=2ns + tphlty=3ns tphlmx=1ns + ) .model D_ALS157_2 ugate ( + tplhmn=3ns tplhty=5ns + tplhmx=6ns tphlmn=2ns + tphlty=4ns tphlmx=1ns + ) .model D_ALS157_3 ugate ( + tplhmn=4ns tplhty=9ns + tplhmx=14ns tphlmn=2ns + tphlty=6ns tphlmx=12ns + ) *--------- * 74AS157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/06/89 Update interface and model names .subckt 74AS157 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_AS157_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_AS157_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_AS157_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_AS157_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_AS157_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_AS157_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_AS157_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS157_1 ugate ( + tplhmn=1ns tplhmx=5ns + tphlmn=1ns tphlmx=4.5ns + ) .model D_AS157_2 ugate ( + tplhmn=1ns tplhmx=4.5ns + tphlmn=1ns tphlmx=2ns + ) .model D_AS157_3 ugate ( + tplhmn=1ns tplhmx=6ns + tphlmn=1ns tphlmx=5.5ns + ) *--------- * 74F157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The F Logic Data Book, 1987, TI * tdn 07/06/89 Update interface and model names .subckt 74F157 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_F157_1 IO_F MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_F157_1 IO_F MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_F157_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_F157_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_F157_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_F157_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_F157_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F157_1 ugate ( + tplhmn=1.5ns tplhty=2.5ns + tplhmx=4.5ns tphlmn=1ns + tphlty=1ns tphlmx=1ns + ) .model D_F157_2 ugate ( + tplhmn=2.5ns tplhty=2.5ns + tplhmx=4.5ns tphlmn=0.5ns + tphlty=0.5ns tphlmx=1ps + ) .model D_F157_3 ugate ( + tplhmn=1.7ns tplhty=4.1ns + tplhmx=6.5ns tphlmn=1.2ns + tphlty=3.6ns tphlmx=7ns + ) *--------- * 74HC157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/06/89 Update interface and model names .subckt 74HC157 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." U1 buf DPWR DGND + SEL D + D_HC157_2 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + D DBAR + D0_GATE IO_HC U3 inv DPWR DGND + GBAR G + D_HC157_3 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 bufa(8) DPWR DGND + 1A 1B 2A 2B 3A 3B 4A 4B + 5A 5B 6A 6B 7A 7B 8A 8B + D_HC157_1 IO_HC IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + 5A DBAR G 5B D G Y1 + D_HC157_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + 6A DBAR G 6B D G Y2 + D_HC157_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + 7A DBAR G 7B D G Y3 + D_HC157_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 ao(3,2) DPWR DGND + 8A DBAR G 8B D G Y4 + D_HC157_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC157_1 ugate ( + tplhty=10ns tplhmx=20ns + tphlty=10ns tphlmx=20ns + ) .model D_HC157_2 ugate ( + tplhty=15ns tplhmx=19ns + tphlty=15ns tphlmx=19ns + ) .model D_HC157_3 ugate ( + tplhty=13ns tplhmx=17ns + tphlty=13ns tphlmx=17ns + ) .model D_HC157_4 ugate ( + tplhty=3ns tplhmx=12ns + tphlty=3ns tphlmx=12ns + ) *--------- * 54L157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 54L157 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_L IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_L157_1 IO_L MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_L157_1 IO_L MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_L157_2 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_L157_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_L157_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_L157_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_L157_3 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_L157_1 ugate ( + tplhty=12ns tplhmx=18ns + tphlty=18ns tphlmx=26ns + ) .model D_L157_2 ugate ( + tplhty=8ns tplhmx=12ns + tphlty=10ns tphlmx=14ns + ) .model D_L157_3 ugate ( + tplhty=18ns tplhmx=28ns + tphlty=18ns tphlmx=28ns + ) *--------- * 74LS157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74LS157 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_LS157_1 IO_LS MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_LS157_1 IO_LS MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_LS157_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_LS157_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_LS157_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_LS157_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_LS157_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS157_1 ugate ( + tplhty=6ns tplhmx=9ns + tphlty=9ns tphlmx=13ns + ) .model D_LS157_2 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=5ns tphlmx=7ns + ) * .model D_LS157_3 ugate ( + tplhty=9ns tplhmx=14ns + tphlty=9ns tphlmx=14ns + ) *--------- * 74S157 Quadruple 2-line to 1-line Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74S157 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_S157_1 IO_S MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_S157_1 IO_S MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_S157_2 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 ao(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_S157_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 ao(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_S157_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 ao(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_S157_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 ao(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_S157_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S157_1 ugate ( + tplhty=4.5ns tplhmx=7.5ns + tphlty=5ns tphlmx=8.5ns + ) .model D_S157_2 ugate ( + tplhty=3.5ns tplhmx=5ns + tphlty=3ns tphlmx=5.5ns + ) .model D_S157_3 ugate ( + tplhty=5ns tplhmx=7.5ns + tphlty=4.5ns tphlmx=6.5ns + ) *------------------------------------------------------------------------- * 74ALS158 Quadruple 2-line to 1-line Inverting Data Selectors/Multiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/06/89 Update interface and model names .subckt 74ALS158 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_ALS158_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_ALS158_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_ALS158_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 aoi(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_ALS158_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 aoi(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_ALS158_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_ALS158_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 aoi(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_ALS158_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_ALS158_1 ugate ( + tplhmn=3ns tplhty=8ns + tplhmx=10ns tphlmn=1ns + tphlty=4ns tphlmx=3ns + ) .model D_ALS158_2 ugate ( + tplhmn=4ns tplhty=9ns + tplhmx=15ns tphlmn=2ns + tphlty=5ns tphlmx=8ns + ) *--------- * 74AS158 Quadruple 2-line to 1-line Inverting Data Selectors/Multiplexers * * The ALS/AS Data Book, 1986, TI * tdn 07/06/89 Update interface and model names .subckt 74AS158 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_AS158_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_AS158_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_AS158_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 aoi(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_AS158_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 aoi(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_AS158_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_AS158_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 aoi(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_AS158_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_AS158_1 ugate ( + tplhmn=1ns tplhmx=6ns + tphlmn=1ns tphlmx=4.5ns + ) .model D_AS158_2 ugate ( + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=1.5ns + ) .model D_AS158_3 ugate ( + tplhmn=1ns tplhmx=5ns + tphlmn=1ns tphlmx=4.5ns + ) *--------- * 74F158 Quadruple 2-line to 1-line Inverting Data Selectors/Multiplexers * * The F Logic Data Book, 1987, TI * tdn 07/06/89 Update interface and model names .subckt 74F158 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_F158_2 IO_F MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_F158_2 IO_F MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_F158_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 bufa(8) DPWR DGND + 1A 1B 2A 2B 3A 3B 4A 4B + 5A 5B 6A 6B 7A 7B 8A 8B + D_F158_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 aoi(3,2) DPWR DGND + 5A DBAR G 5B D G Y1 + D_F158_4 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(3,2) DPWR DGND + 6A DBAR G 6B D G Y2 + D_F158_4 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 aoi(3,2) DPWR DGND + 7A DBAR G 7B D G Y3 + D_F158_4 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 aoi(3,2) DPWR DGND + 8A DBAR G 8B D G Y4 + D_F158_4 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_F158_1 ugate ( + tplhmn=1ns tplhty=1ns + tplhmx=2ns tphlmn=1ns + tphlty=1ns tphlmx=2ns + ) .model D_F158_2 ugate ( + tplhmn=1ns tplhty=1.5ns + tplhmx=2ns tphlmn=2.2ns + tphlty=4ns tphlmx=7ns + ) .model D_F158_3 ugate ( + tplhmn=0.5ns tplhty=1ns + tplhmx=1.5ns tphlmn=1.7ns + tphlty=3ns tphlmx=4.5ns + ) .model D_F158_4 ugate ( + tplhty=1.1ns tplhmx=2.5ns + tphlmn=0.7ns tphlty=2.6ns + tphlmx=5ns + ) *--------- * 74HC158 Quadruple 2-line to 1-line Inverting Data Selectors/Multiplexers * * The High-Speed CMOS Logic Data Book, 1988, TI * tdn 07/06/89 Update interface and model names .subckt 74HC158 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." U1 buf DPWR DGND + SEL D + D_HC158_2 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + D DBAR + D0_GATE IO_HC U3 inv DPWR DGND + GBAR G + D_HC158_3 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 bufa(8) DPWR DGND + 1A 1B 2A 2B 3A 3B 4A 4B + 5A 5B 6A 6B 7A 7B 8A 8B + D_HC158_1 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 aoi(3,2) DPWR DGND + 5A DBAR G 5B D G Y1 + D_HC158_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(3,2) DPWR DGND + 6A DBAR G 6B D G Y2 + D_HC158_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 aoi(3,2) DPWR DGND + 7A DBAR G 7B D G Y3 + D_HC158_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 aoi(3,2) DPWR DGND + 8A DBAR G 8B D G Y4 + D_HC158_4 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_HC158_1 ugate ( + tplhty=10ns tplhmx=20ns + tphlty=10ns tphlmx=20ns + ) .model D_HC158_2 ugate ( + tplhty=15ns tplhmx=19ns + tphlty=15ns tphlmx=19ns + ) .model D_HC158_3 ugate ( + tplhty=13ns tplhmx=17ns + tphlty=13ns tphlmx=17ns + ) .model D_HC158_4 ugate ( + tplhty=3ns tplhmx=12ns + tphlty=3ns tphlmx=12ns + ) *--------- * 74LS158 Quadruple 2-line to 1-line Inverting Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74LS158 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_LS158_1 IO_LS MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_LS158_1 IO_LS MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_LS158_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 aoi(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_LS158_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 aoi(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_LS158_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_LS158_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 aoi(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_LS158_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_LS158_1 ugate ( + tplhty=6ns tplhmx=9ns + tphlty=6ns tphlmx=8ns + ) .model D_LS158_2 ugate ( + tplhty=8ns tplhmx=9ns + tphlty=4ns tphlmx=5ns + ) .model D_LS158_3 ugate ( + tplhty=7ns tplhmx=12ns + tphlty=10ns tphlmx=15ns + ) *--------- * 74S158 Quadruple 2-line to 1-line Inverting Data Selectors/Multiplexers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74S158 GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: "SEL" in this model is the selector input. Data books often call * this input, "SELECT ABAR/B." UBUF buf DPWR DGND + SEL SB + D0_GATE IO_S IO_LEVEL={IO_LEVEL} U1 buf DPWR DGND + SB D + D_S158_1 IO_S MNTYMXDLY={MNTYMXDLY} U2 inv DPWR DGND + SB DBAR + D_S158_1 IO_S MNTYMXDLY={MNTYMXDLY} U3 inv DPWR DGND + GBAR G + D_S158_2 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 aoi(3,2) DPWR DGND + 1A DBAR G 1B D G Y1 + D_S158_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 aoi(3,2) DPWR DGND + 2A DBAR G 2B D G Y2 + D_S158_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U6 aoi(3,2) DPWR DGND + 3A DBAR G 3B D G Y3 + D_S158_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U7 aoi(3,2) DPWR DGND + 4A DBAR G 4B D G Y4 + D_S158_3 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_S158_1 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=4ns tphlmx=6ns + ) .model D_S158_2 ugate ( + tplhty=3ns tplhmx=6ns + tphlty=2.5ns tphlmx=5.5ns + ) .model D_S158_3 ugate ( + tplhty=4ns tplhmx=6ns + tphlty=4ns tphlmx=6ns + ) *------------------------------------------------------------------------- * 74159 4 to 16-line Decoders/Demultiplexers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/06/89 Update interface and model names .subckt 74159 G1BAR G2BAR A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 + Y13 Y14 Y15 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(4) DPWR DGND + A B C D A_BUF B_BUF C_BUF D_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 nor(2) DPWR DGND + G1BAR G2BAR G + D_159_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 bufa(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF P Q R S + D_159_1 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(4) DPWR DGND + A_BUF B_BUF C_BUF D_BUF PBAR QBAR RBAR SBAR + D_159_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 nanda(5,16) DPWR DGND + PBAR QBAR RBAR SBAR G + P QBAR RBAR SBAR G + PBAR Q RBAR SBAR G + P Q RBAR SBAR G + PBAR QBAR R SBAR G + P QBAR R SBAR G + PBAR Q R SBAR G + P Q R SBAR G + PBAR QBAR RBAR S G + P QBAR RBAR S G + PBAR Q RBAR S G + P Q RBAR S G + PBAR QBAR R S G + P QBAR R S G + PBAR Q R S G + P Q R S G + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 + D_159_2 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_159_1 ugate ( + tplhty=8ns tplhmx=11ns + tphlty=8ns tphlmx=11ns + ) .model D_159_2 ugate ( + tplhty=15ns tplhmx=25ns + tphlty=16ns tphlmx=25ns + ) .model D_159_3 ugate ( + tplhty=6ns tplhmx=11ns + )