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- Newsgroups: comp.lsi.testing
- Path: sparky!uunet!cs.utexas.edu!sun-barr!ames!pacbell.com!charon.amdahl.com!netcomsv!netcom.com!obnoid
- From: obnoid@netcom.com (Michael Kirschner)
- Subject: Re: IDDQ Testing?
- Message-ID: <1993Jan22.160047.21804@netcom.com>
- Organization: Netcom - Online Communication Services (408 241-9760 guest)
- X-Newsreader: TIN [version 1.1 PL6]
- References: <13968@optilink.COM>
- Date: Fri, 22 Jan 1993 16:00:47 GMT
- Lines: 30
-
- Terry Manley (manley@optilink.COM) wrote:
- : In article <1993Jan19.231338.29821@newsgate.sps.mot.com> saari@chdasic.sps.mot.com writes:
- :
- : >IDDQ testing is also necessary for the latent defects and catching faults in
- : >redundant logic...
- :
- : I'm unfamiliar with the term IDDQ testing. Would someone simply state the
- : method of this test and it history?
-
- Iddq is the the current drawn from Vdd while the device is in a static, or
- "quiescent" state, hence "Iddq". It's only useful, to my knowledge, for
- CMOS devices which are designed such that there are no intended resistive
- paths from Vdd to ground while in some known state, e.g. immediately after
- reset, with clock, if there is any, at a DC level.
-
- :
- : Thanks,
- :
- : dave
- : manley@optilink.com
-
- Mike
-
- --
- ----------------
- Michael Kirschner
- 2224 Larkin St. (415)292-3674 (voice)
- San Francisco, CA 94109 Preferred E-Mail address: obnoid@netcom.COM
- [GEnie: M.KIRSCHNER1; well: obnoid]
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