NetNews Usenet Archive 1993 #3/NN_1993_3.iso/spool/comp/lsi/802

Internet Message Format | 1993-01-25 | 1.2 KB

Path: sparky!uunet!math.fu-berlin.de!mailgzrz.TU-Berlin.DE!cs.tu-berlin.de!ronald
From: [e-mail] (Ronald Hindmarsh)
Newsgroups: comp.lsi
Subject: Impact of minimal transistor width 3 or 4 instead of 2?
Date: 25 Jan 1993 19:54:43 GMT
Organization: Technical University of Berlin, Germany
Lines: 18
Message-ID: <[e-mail]>
NNTP-Posting-Host: harry.cs.tu-berlin.de
Keywords: CMOS VLSI


I am working on a CMOS-VLSI layout generator for digital circuits.

For topological reasons I would like to limit the MINIMUM w/l
of a MOS transistor to 3 or 4 (in some physical design rules
of a process I have seen a minimal transistor width of 2).

Do you think, from your experience, this would have a strong
impact on the performance or the power consumption of a circuit?


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 Ronald Hindmarsh                      e-mail: [e-mail]
 Institut fuer Technische Informatik
 TU Berlin FR 3-9
 Franklinstr. 29                            Phone: [phone]
 W-1000 Berlin 10                             Fax: [phone]
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