NetNews Usenet Archive 1993 #3/NN_1993_3.iso/spool/comp/lang/verilog/504

Internet Message Format | 1993-01-21 | 2.1 KB

Path: sparky!uunet!news.tek.com!tekig7!tekeda!cliffc
From: [e-mail] (Clifford E Cummings)
Newsgroups: comp.lang.verilog
Subject: Re: Verilog code for Inverted, Open collector, Output Enable Bus
Keywords: Inverted, Open collector, Output Enable Bus
Message-ID: <[e-mail]>
Date: 21 Jan 93 20:53:48 GMT
References: <[e-mail]>
Sender: [e-mail]
Organization: Tektronix, Inc., Beaverton,  OR.
Lines: 63

In article <[e-mail]> [e-mail] (Tai Phan) writes:
>If anyone knows a simple way to describe in Verilog an Open collector,
>Inverted, with Output enable bus, please help.  The parameters are as follow:
>
>// Verilog code
>
>input [31:0] inp;               // Input bus
>input oen_;                     // Output enable
>output [31:0] outp_;            // Output bus
>
>// When oen_ is 1, outp_ should be 32'hzzzzzzzz
>// when oen_ is 0, outp_ is 0 if inp is 1, and z if inp is 0 (OC inverted)
>// For single bit, I have the code that works:
>
>wire [31:0] outp_;
>assign outp_[31] = (~oen_ && inp[31]) ? 'b0 : 'bz;
>assign outp_[30] = (~oen_ && inp[30]) ? 'b0 : 'bz;
>.......
>and so on
>
>Thanks,
>
>Tai Phan
>--------
>Interphase Corp.
>[phone]
>[e-mail]

Is this what you are looking for? (this example can be run)

`timescale 1ns/100ps
module oc_bus( outp_, inp, oen_);
  // Verilog code
  input [31:0] inp;               // Input bus
  input oen_;                     // Output enable
  output [31:0] outp_;            // Output bus

  triand (strong1, highz0) [31:0] outp_ = (~oen_ ? ~inp : 32'bz);

endmodule

module oc_bus_test;
  reg  [31:0] inbus;
  reg         busen_;
  wire [31:0] outbus;

  oc_bus b1( outbus, inbus, busen_);

  initial
  $monitor("inbus = %h | busen_ = %h | outbus = %h \n",
      inbus, busen_, outbus,
      "                               (binary)= %b \n",
      outbus);

  initial begin
    #000 inbus = 32'hffff0000; busen_ = 1'b1;
    #100 inbus = 32'h0000ffff; busen_ = 1'b0;
    #100 inbus = 32'h00ff5500; busen_ = 1'b0;
    #100 $finish;
  end
endmodule

Regards - Cliff Cummings - [e-mail]