NetNews Usenet Archive 1993 #3/NN_1993_3.iso/spool/comp/lang/verilog/503

Text File | 1993-01-21 | 1.3 KB | 50 lines

Newsgroups: comp.lang.verilog
Path: sparky!uunet!iphase.com!phan
From: [e-mail] (Tai Phan)
Subject: Verilog code for Inverted, Open collector, Output Enable Bus
Message-ID: <[e-mail]>
Followup-To: [e-mail]
Summary: Inverted, Open collector, Output Enable Bus
Keywords: Inverted, Open collector, Output Enable Bus
Sender: [e-mail]
Nntp-Posting-Host: wildcat_ne0
Organization: Interphase Corporation, Dallas Texas
Date: Thu, 21 Jan 1993 16:17:07 GMT
Lines: 35

Greetings,

If anyone knows a simple way to describe in Verilog an Open collector, Inverted,
with Output enable bus, please help.  The parameters are as follow:

// Verilog code

input [31:0] inp;               // Input bus
input oen_;                     // Output enable
output [31:0] outp_;            // Output bus

// When oen_ is 1, outp_ should be 32'hzzzzzzzz
// when oen_ is 0, outp_ is 0 if inp is 1, and z if inp is 0 (OC inverted)
// For single bit, I have the code that works:

wire [31:0] outp_;
assign outp_[31] = (~oen_ && inp[31]) ? 'b0 : 'bz;
assign outp_[30] = (~oen_ && inp[30]) ? 'b0 : 'bz;
.......
and so on
But this takes a lot of space, and typing. I want to use one or two lines
to describe the entire 32 bits bus.

Thanks,

Tai Phan
--------
Interphase Corp.
[phone]
[e-mail]


--
Tai Phan  X218
[e-mail]