NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/comp/sys/amiga/hardware/22044

Internet Message Format | 1992-12-24 | 4.9 KB

Path: sparky!uunet!spool.mu.edu!umn.edu!msus1.msus.edu!msus1.msus.edu!news
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Data/Instruction Cache & BURST modes on 68030? Why/when?
Message-ID: <[e-mail]>
From: [e-mail] (LaMonte Koop)
Date: 24 Dec 92 12:06:34 -0600
Reply-To: [e-mail]
References: <hellerS.724958427@batman> <[e-mail]>,<hellerS.725061488@batman>
Distribution: na
Organization: SCS GP/Engineering Cluster
Nntp-Posting-Host: tigger.stcloud.msus.edu
Lines: 73

In article <hellerS.725061488@batman>, [e-mail] (sjh) writes:
>Thanks to all who wrote me replies on these questions. However, I've gotten
>a few different replies, so I called CSA and asked for the "straight
>answer" and this is what they said. As far as the MMR goes, there is NO
>burst mode capability, regardless of 32-bit memory speed. As far as the
>data/instruction caches go, if you HAVE NO 32-bit memory on the CPU, the
>caches can speed things up a bit, but are essentially useless when working
>with 32-bit DRAM. His suggestion was to LEAVE the CACHES and BURST OFF.

    Well, I don't know who you were talking to, but the suggestion to leaving
the caches themselves off is nonsense.  They will improve performance, even
with a 32-bit ported RAM interface.
    Basically, what the caches do is store data (data cache) and instructions
(instruction cache) which the CPU is utilizing.  If the CPU calls for an
instruction from an address, or data, and finds it in its respective cache,
it can completely avoid a bus cycle to external memory and take the operand
straight from the cache.
    The caches operate at a zero wait state level (actually, in some
circumstances it appears to be less in comparison to an external memory system).
Any access to them will be faster than a corresponding access to memory.
This is even more true as almost any memory system you are bound to have is
going to most likely run a 5 clock memory access cycle or more.  As an example
of the performance increase of using the caches, I ran some tests for
comparison.  The system in question is 68030 based (@ 40 MHz), with a full
complement of 32-bit ported DRAM.  BURST mode is not active:

      Test                Caches off       Caches On         Units/Notes
     ------             --------------   --------------     -------------
   Dhrystone                10057            13813          Dhrystones/Sec
                                                            Higher = Better

     Sieve                  10.90             6.07             Seconds
                                                             Lower = Better


>Several people were pretty certain that 60ns was the magic number for DRAM
>speed to be able to use burst mode. The CSA guy laughed and said that was
>nonsense - it just doesn't exist on the MMR. It was a feature they had
>originally intended to include but decided to leave it out because they
>felt there was virtually no demand for it...why, I don't know. It must work
>on some accellerators, but not the MMR (or the Derringer).

Correct.  60ns is not a magic number here, its merely an access time rating.
BURST mode relies on the ability of the DRAM to respond properly to a special
access cycle initiated by the 68030.  For this to happen, the DRAM must be
under control of a device capable of handling BURST mode cycles (if utilizing
a memory controller arangement), and the memory itself must have some special
properties.  Basically, the DRAM must be capable of holding one element of
its internal addressing mechanism constant, while dynamically altering the
other.   (for example, in SCRAM, the column address inside the device can be
held, while the row address varies).  This eliminates the precharge times for
that access, and allows memory accesses to be 'walked' along a row which
can be quickly fed into a 68030 cache line.  For example, with a BURST capable
memory, assuming a 5 clock normal memory access, using a burst cycle to fill
a cache line can be set up to have: 5 clocks for the first longword access,
followed by 1 clock for the next 3 subsequent accesses.  This allows a cache
line to be filled in 8 clocks, rather than 20 as would be required on normal
cycles.

>So that's the scoop, direct from the tech-support at CSA.

Well, true enough that the MMR does not have a BURST capable memory setup.
However, the bunk about not using the caches is a bit to be put on the list
of "Thinks that make you go hmmmm....".  True, BURST mode should be left off,
as it would not help you in any way...(it won't hurt either), but the caches
themselves should be turned on for best performance.


                 ----------------------------------------
           LaMonte Koop -- SCSU Electrical/Computer Engineering
 Internet: [e-mail] -OR- [e-mail]
              "You mean you want MORE lights on this thing???"
 ---------------------------------------------------------------------------