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- From: udo@umunk.GUN.de (Udo Munk)
- Newsgroups: comp.os.coherent
- Distribution: world
- Subject: Re: Questions regarding swapping and memory
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- References: <9212234989@drktowr.chi.il.us>
- Message-ID: <9212242239@umunk.GUN.de>
- Organization: Udo Munk's private BBS
- Date: Thu, 24 Dec 92 22:29:59 GMT
- Lines: 31
-
- Louis Giliberto (magus@drktowr.chi.il.us) wrote:
- : Udo Munk (udo@umunk.GUN.de) wrote:
- : : COHERENT 4.0 uses a flat 32 bit memory model, there is nothing
- : : like extended/expanded memory. You've linear access to the whole
- : : memory available in your system.
- :
- : Er, just out of curiosity, do they pull the old "1 CS 1 DS make it look
- : like a PDP" trick? The the virtual mem will be page swapped instead
- : of segment swapped I guess.
-
- COHERENT 3.x is 1 CS 1 DS like the good old PDP11, for COHERENT 4.0
- demand paging and segment swapping could be possible.
-
- : : The limitation is that COHERENT supports a maximum of 16 MB memory
- : : yet, because of the DMA controllers with only 24 bit addresses.
- : : This is for ISA bus systems, maybe later it supports more memory
- : : with EISA bus systems.
- :
- : Maybe I'm ignorant, but couldn't this be doubled almost instantly by
- : putting the text segment in higher memory where the DMA doesn't need
- : access and the data seg in lower where it could reach it? For internal
- : kernel buffers you could just DMA to low physical, and page swap it to
- : where you need it. After all, the OS has control over the descriptors
- : and could change the protection ring as needed.
-
- If you have demand paging and swapping the DMA controller also has to
- swap pages in the text segment to/from the disk.
- Sure can it be realized with buffers in the kernel, this is how windows
- and SCO make more then 16MB available. Under SCO you'll find a performance
- loss up to 30% if you increase the memory above 16MB. I guess they copy
- buffers with the CPU to memory above 16MB instead of using the MMU.
- --
- Udo Munk, Oberstr. 21, 4040 Neuss 1, Germany
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