NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/comp/lang/vhdl/606

Text File | 1992-12-22 | 1.5 KB | 42 lines

Newsgroups: comp.lang.vhdl
Path: sparky!uunet!nwnexus!ole!george
From: [e-mail] (George Lippincott)
Subject: wire primitives in VHDL
Message-ID: <[e-mail]>
Organization: Cascade Design Automation
Date: Tue, 22 Dec 1992 01:45:51 GMT
Lines: 32


I am trying to figure out a way in VHDL to merge two bidirectional
signals into one signal.  This is something that most of the major
logic simulators let you do but which as far as I can tell is
impossible in VHDL.

This situation comes up when an entity is implemented in such a way
that two bidirectional ports connect to the same signal.  What I
would like to do is have some way to "short" these two signals together.
Ideally the resolution function would see all of the drivers for
both signals and calculate a value for both nets.

This can be done in Verilog like this:
        module wire(w,w)
        inout w;
        endmodule;

I haven't been able to figure out a way to do the same thing in VHDL.
If I use the code:
        a <= b;
        b <= a;

Then a driver is added to both signals and the value gets stuck at 'U'
due to the nature of the resolution function in the IEEE 1167 package.

Does anyone have any idea on how to work around this?

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George Lippincott               | UUCP:      uunet!ole!george
Cascade Design Automation Corp. | Internet:  [e-mail]
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