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- From: bhandarkar@wrksys.enet.dec.com (Dileep Bhandarkar)
- Subject: Re: DEC Alpha architecture issues
- Message-ID: <1992Nov23.180432.26829@ryn.mro4.dec.com>
- Sender: news@ryn.mro4.dec.com (USENET News System)
- Organization: Digital Equipment Corporation
- References: <1992Nov19.204209.6619@nntpd.lkg.dec.com> <DOCONNOR.92Nov20095251@potato.sedona.intel.com> <1992Nov20.183610.12796@crl.dec.com>
- Date: 23 NOV 92 13:04:41
- Lines: 13
-
-
- >In article <DOCONNOR.92Nov20095251@potato.sedona.intel.com> doconnor@sedona.intel.com (Dennis O'Connor) writes:
- >>
- >>Sounds like a microcoded instruction to me. Except, of course, that
- >>there's no guarantee of what PALcodes are available on a particular
- >>system, and that the microcode may be external to the chip.
- >
- We first used this idea in 1985 in the PRISM architecture as epicode. The intent
- was to implement complex functions (that used to be microcoded on VAX) within
- a RISC architecture. It is like a microcoded instruction, except that it is
- implemented in macrocode that runs in a special mode.
-
- Dileep
-