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- Newsgroups: comp.arch
- Path: sparky!uunet!cs.utexas.edu!swrinde!elroy.jpl.nasa.gov!decwrl!deccrl!news.crl.dec.com!payne
- From: payne@crl.dec.com (Andrew Payne)
- Subject: Re: DEC Alpha architecture issues
- Message-ID: <1992Nov22.002803.15320@crl.dec.com>
- Sender: news@crl.dec.com (USENET News System)
- Organization: DEC Cambridge Research Lab
- References: <DOCONNOR.92Nov20095251@potato.sedona.intel.com> <1992Nov20.183610.12796@crl.dec.com> <1992Nov21.194311.7600@technix.mn.org>
- Date: Sun, 22 Nov 1992 00:28:03 GMT
- Lines: 21
-
- In article <1992Nov21.194311.7600@technix.mn.org> bret@technix.mn.org (Bret Indrelee) writes:
-
- [ text about Alpha's PAL mode deleted ]
-
- >>3. Interrupts are disabled (so you can do atomic operations)
- >
- >Hold it! Disabling interrupts is not usually enough to guarentee that
- >an operation is atomic!
-
- Of course! In context, the statement meant "without disabling interrupts you
- can't do atomic operations."
-
- >Either I am missing something, or PALcode has to do more in order to make
- >sure that the operation is atomic.
-
- For implementing atomic memory operations, Alpha provides a load_locked/
- store_conditional mechanism.
-
- --
- Andrew C. Payne
- DEC Cambridge Research Lab
-