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- Newsgroups: comp.arch
- Subject: Re: DEC Alpha architecture issues
- Message-ID: <By0xy0.FsA.2@cs.cmu.edu>
- From: lindsay+@cs.cmu.edu (Donald Lindsay)
- Date: Fri, 20 Nov 1992 17:01:10 GMT
- Sender: news@cs.cmu.edu (Usenet News System)
- References: <1992Nov18.210416.27212@nntpd.lkg.dec.com> <lgnfc3INNqnt@spim.mti.sgi.com>
- Organization: School of Computer Science, Carnegie Mellon
- Nntp-Posting-Host: gandalf.cs.cmu.edu
- Lines: 17
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-
- woodacre@mips.com (Michael Woodacre) writes:
- [ in reference to PALcode ]
- >Can you explain how this is different from kernel code with interrupts
- >disabled on any other risc processor?
-
- Think of it as a supervisor state. This state doesn't just have
- interrupts disabled: it also has direct access to a large variety of
- implementation-specific internal registers. For example, TLB reloads
- are done by PALcode, whereas the "normal" code in the OS need only
- know architectural things (things that remain constant across
- implementations).
-
- Also, PALcode can be entered from user state - you don't need to do a
- system call, with its heavy-duty state-change overheads.
- --
- Don D.C.Lindsay Carnegie Mellon Computer Science
-