home *** CD-ROM | disk | FTP | other *** search
- Path: sparky!uunet!ornl!rsg1.er.usgs.gov!darwin.sura.net!wupost!cs.utexas.edu!asuvax!chnews!chnews!doconnor
- From: doconnor@sedona.intel.com (Dennis O'Connor)
- Newsgroups: comp.arch
- Subject: Re: DEC Alpha architecture issues
- Date: 20 Nov 92 09:52:51
- Organization: Intel i960(tm) Architecture
- Lines: 15
- Message-ID: <DOCONNOR.92Nov20095251@potato.sedona.intel.com>
- References: <1992Nov19.204209.6619@nntpd.lkg.dec.com>
- NNTP-Posting-Host: potato.intel.com
- In-reply-to: dipirro@star.dec.com's message of Thu, 19 Nov 1992 20:30:12 GMT
-
-
- dipirro@star.dec.com (Steve DiPirro) writes:
- ] ... PALcode "instructions" actually appear as single instructions
- ] in the Istream which is handy for debuggers, etc. PALcode runs
- ] with interrupts disabled, Istream memory management traps disabled,
- ] and complete control over machine state.
-
- Sounds like a microcoded instruction to me. Except, of course, that
- there's no guarantee of what PALcodes are available on a particular
- system, and that the microcode may be external to the chip.
-
- Humoursly : Sounds like an architectural wimp-out to me :-)
-
- --
- Dennis O'Connor doconnor@sedona.intel.com
-