home *** CD-ROM | disk | FTP | other *** search
- Path: sparky!uunet!mcsun!sunic!dkuug!diku!thorinn
- From: thorinn@diku.dk (Lars Henrik Mathiesen)
- Newsgroups: comp.arch
- Subject: Re: PA-RISC ``semantic loading'' (according to DEC)
- Message-ID: <1992Nov19.204612.10316@odin.diku.dk>
- Date: 19 Nov 92 20:46:12 GMT
- References: <1992Nov13.173228.16970@odin.diku.dk> <32580142@hpcuhe.cup.hp.com> <1992Nov19.140334.14589@vbohub.vbo.dec.com>
- Sender: thorinn@tyr.diku.dk
- Organization: Department of Computer Science, U of Copenhagen
- Lines: 24
-
- kaiser@mammal.vbo.dec.com (Peter Kaiser) writes:
- >campbelr@hpcuhe.cup.hp.com (Bob Campbell) writes:
- >>Someone at DEC writes:
- >>>I write:
- >>>> I suspect
- >>>> that PA-RISC can get by with executing fewer instructions as well.
- >>> This is, in a nutshell, the CISC viewpoint.
- >>Some might call it engineering.
- >Touchy? :-)
-
- While this charming little cascade could run for a while, I'll just
- point out that I really think that the first gentleman from DEC was
- stretching it --- I was clearly describing the HP-PA architecture as
- being placed firmly within the RISC sphere, albeit in the less
- aggressively hardware-optimizable end.
-
- Rather than snide remarks, I had hoped to elicit informed comment as
- to how much the statefulness of the HP-PA programmers' model impacts
- (or can be assumed to impact) current and future implementations, in
- development time *and* in achievable speed for a given technology.
-
- Please?
-
- Lars Mathiesen (U of Copenhagen CS Dep) <thorinn@diku.dk> (Humour NOT marked)
-