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C/C++ Source or Header  |  1993-05-30  |  18.2 KB  |  439 lines
  1. /* Table of opcodes for the PA-RISC.
  2.    Copyright (C) 1990, 1991, 1993 Free Software Foundation, Inc.
  3.  
  4.    Contributed by the Center for Software Science at the
  5.    University of Utah (pa-gdb-bugs@cs.utah.edu).
  6.  
  7. This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
  8.  
  9. GAS/GDB is free software; you can redistribute it and/or modify
  10. it under the terms of the GNU General Public License as published by
  11. the Free Software Foundation; either version 1, or (at your option)
  12. any later version.
  13.  
  14. GAS/GDB is distributed in the hope that it will be useful,
  15. but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17. GNU General Public License for more details.
  18.  
  19. You should have received a copy of the GNU General Public License
  20. along with GAS or GDB; see the file COPYING.  If not, write to
  21. the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  22.  
  23. #if !defined(__STDC__) && !defined(const)
  24. #define const
  25. #endif
  26.  
  27. /*
  28.  * Structure of an opcode table entry.
  29.  */
  30.  
  31. /* There are two kinds of delay slot nullification: normal which is
  32.  * controled by the nullification bit, and conditional, which depends
  33.  * on the direction of the branch and its success or failure.
  34.  */
  35. enum delay_type {NONE, NORMAL, CONDITIONAL};
  36. struct pa_opcode
  37. {
  38.     const char *name;
  39.     unsigned long int match;    /* Bits that must be set...  */
  40.     unsigned long int mask;    /* ... in these bits. */
  41.     char *args;
  42.     /* Nonzero if this is a delayed branch instruction.  */
  43.     /* What uses this field?  Nothing in opcodes or gas that I saw.
  44.        If nothing needs it, we could reduce this table by 20% (for
  45.        most machines).  KR */
  46.     char delayed;
  47. };
  48.  
  49. /*
  50.    All hppa opcodes are 32 bits.
  51.  
  52.    The match component is a mask saying which bits must match a
  53.    particular opcode in order for an instruction to be an instance
  54.    of that opcode.
  55.  
  56.    The args component is a string containing one character
  57.    for each operand of the instruction.
  58.  
  59.    Bit positions in this description follow HP usage of lsb = 31,
  60.    "at" is lsb of field.
  61.  
  62.    In the args field, the following characters must match exactly:
  63.  
  64.     '+,() '
  65.  
  66.    In the args field, the following characters are unused:
  67.  
  68.     '  "#$% '  *-  ./   34 6789:; =  @'
  69.     ' B  E  HIJKL N  QR     X  [\] _'
  70.     '    e gh   lm   qr   v  yz{|} '
  71.  
  72.    Here are all the characters:
  73.  
  74.     ' !"#$%&'()*+-,./0123456789:;<=>?@'
  75.     'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
  76.     'abcdefghijklmnopqrstuvwxyz{|}~'
  77.  
  78. Kinds of operands:
  79.    x    register field at 15.
  80.    b    register field at 10.
  81.    t    register field at 31.
  82.    5    5 bit immediate at 15.
  83.    s    2 bit space specifier at 17.
  84.    S    3 bit space specifier at 18.
  85.    c    indexed load completer.
  86.    C    short load and store completer.
  87.    Y    Store Bytes Short completer
  88.    <    non-negated compare/subtract conditions.
  89.    a    compare/subtract conditions
  90.    d    non-negated add conditions
  91.    &    logical instruction conditions
  92.    U    unit instruction conditions
  93.    >    shift/extract/deposit conditions.
  94.    ~    bvb,bb conditions
  95.    V    5 bit immediate value at 31
  96.    i    11 bit immediate value at 31
  97.    j    14 bit immediate value at 31
  98.    k    21 bit immediate value at 31
  99.    n    nullification for branch instructions
  100.    w    12 bit branch displacement
  101.    W    17 bit branch displacement
  102.  
  103. Also these:
  104.    p    5 bit shift count at 26 (to support the SHD instruction) encoded as
  105.         31-p
  106.    P    5 bit bit position at 26
  107.    T    5 bit field length at 31 (encoded as 32-T)
  108.    A    13 bit immediate at 18 (to support the BREAK instruction)
  109.    ^    like b, but describes a control register
  110.    Z    System Control Completer (to support LPA, LHA, etc.)
  111.    D    26 bit immediate at 31 (to support the DIAG instruction)
  112.  
  113.    f    3 bit Special Function Unit identifier at 25
  114.    O    20 bit Special Function Unit operation split between 15 bits at 20
  115.         and 5 bits at 31
  116.    o    15 bit Special Function Unit operation at 20
  117.    2    22 bit Special Function Unit operation split between 17 bits at 20
  118.         and 5 bits at 31
  119.    1    15 bit Special Function Unit operation split between 10 bits at 20
  120.         and 5 bits at 31
  121.    0    10 bit Special Function Unit operation split between 5 bits at 20
  122.         and 5 bits at 31
  123.    u    3 bit coprocessor unit identifier at 25
  124.    F    Source Floating Point Operand Format Completer encoded 2 bits at 20
  125.    G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
  126.    M    Floating-Point Compare Conditions (encoded as 5 bits at 31)
  127. #ifdef GAS
  128.    ?    negated or non-negated compare/subtract conditions
  129.         (used only by 'comb' and 'comib' pseudo-instructions)
  130.    !    negated or non-negated add conditions
  131.         (used only by 'addb' and 'addib' pseudo-instructions)
  132. #else GDB
  133.    ?    negated compare/subtract conditions.
  134.    !    non-negated add conditions.
  135.    @    negated add conditions.
  136. #endif
  137.  
  138. No longer used:
  139.    B    either s,b or b where
  140.  
  141.            s    2 bit space specifier at 17.
  142.            b    register field at 10.
  143.  
  144. */
  145.  
  146. /* The order of the opcodes in this table is significant:
  147.  
  148.    * The assembler requires that all instances of the same mnemonic must be
  149.    consecutive.  If they aren't, the assembler will bomb at runtime.
  150.  
  151.    * The disassembler should not care about the order of the opcodes.  */
  152.  
  153. static const struct pa_opcode pa_opcodes[] =
  154. {
  155.  
  156. /* pseudo-instructions */
  157.  
  158. { "b",        0xe8000000, 0xffe0e000, "nW", NORMAL}, /* bl foo,r0 */
  159. { "ldi",    0x34000000, 0xffe0c000, "j,x"},    /* ldo val(r0),r */
  160. { "comib",     0x84000000, 0xfc000000, "?n5,b,w", CONDITIONAL}, /* comib{tf}*/
  161. { "comb",    0x80000000, 0xfc000000, "?nx,b,w", CONDITIONAL}, /* comb{tf} */
  162. { "addb",    0xa0000000, 0xfc000000, "!nx,b,w", CONDITIONAL}, /* addb{tf} */
  163. { "addib",    0xa4000000, 0xfc000000, "!n5,b,w", CONDITIONAL}, /* addib{tf}*/
  164. { "nop",        0x08000240, 0xffffffff, ""},      /* or 0,0,0 */
  165. { "copy",       0x08000240, 0xffe0ffe0, "x,t"},   /* or r,0,t */
  166. { "mtsar",      0x01601840, 0xffe0ffff, "x"}, /* mtctl r,cr11 */
  167.  
  168. { "ldw",        0x48000000, 0xfc000000, "j(s,b),x"},
  169. { "ldw",        0x48000000, 0xfc000000, "j(b),x"},
  170. { "ldh",        0x44000000, 0xfc000000, "j(s,b),x"},
  171. { "ldh",        0x44000000, 0xfc000000, "j(b),x"},
  172. { "ldb",        0x40000000, 0xfc000000, "j(s,b),x"},
  173. { "ldb",        0x40000000, 0xfc000000, "j(b),x"},
  174. { "stw",        0x68000000, 0xfc000000, "x,j(s,b)"},
  175. { "stw",        0x68000000, 0xfc000000, "x,j(b)"},
  176. { "sth",        0x64000000, 0xfc000000, "x,j(s,b)"},
  177. { "sth",        0x64000000, 0xfc000000, "x,j(b)"},
  178. { "stb",        0x60000000, 0xfc000000, "x,j(s,b)"},
  179. { "stb",        0x60000000, 0xfc000000, "x,j(b)"},
  180. { "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x"},
  181. { "ldwm",       0x4c000000, 0xfc000000, "j(b),x"},
  182. { "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)"},
  183. { "stwm",       0x6c000000, 0xfc000000, "x,j(b)"},
  184. { "ldwx",       0x0c000080, 0xfc001fc0, "cx(s,b),t"},
  185. { "ldwx",       0x0c000080, 0xfc001fc0, "cx(b),t"},
  186. { "ldhx",       0x0c000040, 0xfc001fc0, "cx(s,b),t"},
  187. { "ldhx",       0x0c000040, 0xfc001fc0, "cx(b),t"},
  188. { "ldbx",       0x0c000000, 0xfc001fc0, "cx(s,b),t"},
  189. { "ldbx",       0x0c000000, 0xfc001fc0, "cx(b),t"},
  190. { "ldwax",      0x0c000180, 0xfc00dfc0, "cx(b),t"},
  191. { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cx(s,b),t"},
  192. { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cx(b),t"},
  193. { "ldws",    0x0c001080, 0xfc001fc0, "C5(s,b),t"},
  194. { "ldws",    0x0c001080, 0xfc001fc0, "C5(b),t"},
  195. { "ldhs",    0x0c001040, 0xfc001fc0, "C5(s,b),t"},
  196. { "ldhs",    0x0c001040, 0xfc001fc0, "C5(b),t"},
  197. { "ldbs",    0x0c001000, 0xfc001fc0, "C5(s,b),t"},
  198. { "ldbs",    0x0c001000, 0xfc001fc0, "C5(b),t"},
  199. { "ldwas",    0x0c001180, 0xfc00dfc0, "C5(b),t"},
  200. { "ldcws",    0x0c0011c0, 0xfc001fc0, "C5(s,b),t"},
  201. { "ldcws",    0x0c0011c0, 0xfc001fc0, "C5(b),t"},
  202. { "stws",    0x0c001280, 0xfc001fc0, "Cx,V(s,b)"},
  203. { "stws",    0x0c001280, 0xfc001fc0, "Cx,V(b)"},
  204. { "sths",    0x0c001240, 0xfc001fc0, "Cx,V(s,b)"},
  205. { "sths",    0x0c001240, 0xfc001fc0, "Cx,V(b)"},
  206. { "stbs",    0x0c001200, 0xfc001fc0, "Cx,V(s,b)"},
  207. { "stbs",    0x0c001200, 0xfc001fc0, "Cx,V(b)"},
  208. { "stwas",    0x0c001380, 0xfc00dfc0, "Cx,V(b)"},
  209. { "stbys",    0x0c001300, 0xfc001fc0, "Yx,V(s,b)"},
  210. { "stbys",    0x0c001300, 0xfc001fc0, "Yx,V(b)"},
  211. { "ldo",    0x34000000, 0xfc00c000, "j(b),x"},
  212. { "ldil",    0x20000000, 0xfc000000, "k,b"},
  213. { "addil",    0x28000000, 0xfc000000, "k,b"},
  214. { "bl",        0xe8000000, 0xfc00e000, "nW,b", NORMAL},
  215. { "gate",    0xe8002000, 0xfc00e000, "nW,b", NORMAL},
  216. { "blr",    0xe8004000, 0xfc00e001, "nx,b", NORMAL},
  217. { "bv",        0xe800c000, 0xfc00e001, "n(b)", NORMAL},
  218. { "bv",        0xe800c000, 0xfc00e001, "nx(b)", NORMAL},
  219. { "be",        0xe0000000, 0xfc000000, "nW(S,b)", NORMAL},
  220. { "ble",    0xe4000000, 0xfc000000, "nW(S,b)", NORMAL},
  221. { "movb",    0xc8000000, 0xfc000000, ">nx,b,w", CONDITIONAL},
  222. { "movib",    0xcc000000, 0xfc000000, ">n5,b,w", CONDITIONAL},
  223. { "combt",    0x80000000, 0xfc000000, "<nx,b,w", CONDITIONAL},
  224. { "combf",    0x88000000, 0xfc000000, "<nx,b,w", CONDITIONAL},
  225. { "comibt",    0x84000000, 0xfc000000, "<n5,b,w", CONDITIONAL},
  226. { "comibf",    0x8c000000, 0xfc000000, "<n5,b,w", CONDITIONAL},
  227. { "addbt",    0xa0000000, 0xfc000000, "!nx,b,w", CONDITIONAL},
  228. { "addbf",    0xa8000000, 0xfc000000, "!nx,b,w", CONDITIONAL},
  229. { "addibt",    0xa4000000, 0xfc000000, "!n5,b,w", CONDITIONAL},
  230. { "addibf",    0xac000000, 0xfc000000, "!n5,b,w", CONDITIONAL},
  231. { "bvb",    0xc0000000, 0xffe00000, "~nx,w", CONDITIONAL},
  232. { "bb",        0xc4000000, 0xfc000000, "~nx,b,w", CONDITIONAL}, /* maybe */
  233.  
  234. /* Computation Instructions */
  235.  
  236. { "add",        0x08000600, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  237. { "addl",       0x08000a00, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  238. { "addo",       0x08000e00, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  239. { "addc",       0x08000700, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  240. { "addco",      0x08000f00, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  241. { "sh1add",     0x08000640, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  242. { "sh1addl",    0x08000a40, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  243. { "sh1addo",    0x08000e40, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  244. { "sh2add",     0x08000680, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  245. { "sh2addl",    0x08000a80, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  246. { "sh2addo",    0x08000e80, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  247. { "sh3add",     0x080006c0, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  248. { "sh3addl",    0x08000ac0, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  249. { "sh3addo",    0x08000ec0, 0xfc000fe0, "dx,b,t", CONDITIONAL},
  250. { "sub",        0x08000400, 0xfc000fe0, "ax,b,t", CONDITIONAL},
  251. { "subo",       0x08000c00, 0xfc000fe0, "ax,b,t", CONDITIONAL},
  252. { "subb",       0x08000500, 0xfc000fe0, "ax,b,t", CONDITIONAL},
  253. { "subbo",      0x08000d00, 0xfc000fe0, "ax,b,t", CONDITIONAL},
  254. { "subt",       0x080004c0, 0xfc000fe0, "ax,b,t", CONDITIONAL},
  255. { "subto",      0x08000cc0, 0xfc000fe0, "ax,b,t", CONDITIONAL},
  256. { "ds",         0x08000440, 0xfc000fe0, "ax,b,t", CONDITIONAL},
  257. { "comclr",     0x08000880, 0xfc000fe0, "ax,b,t", CONDITIONAL},
  258. { "or",         0x08000240, 0xfc000fe0, "&x,b,t", CONDITIONAL},
  259. { "xor",        0x08000280, 0xfc000fe0, "&x,b,t", CONDITIONAL},
  260. { "and",        0x08000200, 0xfc000fe0, "&x,b,t", CONDITIONAL},
  261. { "andcm",      0x08000000, 0xfc000fe0, "&x,b,t", CONDITIONAL},
  262. { "uxor",       0x08000380, 0xfc000fe0, "Ux,b,t", CONDITIONAL},
  263. { "uaddcm",     0x08000980, 0xfc000fe0, "Ux,b,t", CONDITIONAL},
  264. { "uaddcmt",    0x080009c0, 0xfc000fe0, "Ux,b,t", CONDITIONAL},
  265. { "dcor",       0x08000b80, 0xfc1f0fe0, "Ub,t",   CONDITIONAL},
  266. { "idcor",      0x08000bc0, 0xfc1f0fe0, "Ub,t",   CONDITIONAL},
  267. { "addi",       0xb4000000, 0xfc000800, "di,b,x", CONDITIONAL},
  268. { "addio",      0xb4000800, 0xfc000800, "di,b,x", CONDITIONAL},
  269. { "addit",      0xb0000000, 0xfc000800, "di,b,x", CONDITIONAL},
  270. { "addito",     0xb0000800, 0xfc000800, "di,b,x", CONDITIONAL},
  271. { "subi",       0x94000000, 0xfc000800, "ai,b,x", CONDITIONAL},
  272. { "subio",      0x94000800, 0xfc000800, "ai,b,x", CONDITIONAL},
  273. { "comiclr",    0x90000000, 0xfc000800, "ai,b,x", CONDITIONAL},
  274.  
  275. /* Extract and Deposit Instructions */
  276.  
  277. { "vshd",       0xd0000000, 0xfc001fe0, ">x,b,t", CONDITIONAL},
  278. { "shd",        0xd0000800, 0xfc001c00, ">x,b,p,t", CONDITIONAL},
  279. { "vextru",     0xd0001000, 0xfc001fe0, ">b,T,x", CONDITIONAL},
  280. { "vextrs",     0xd0001400, 0xfc001fe0, ">b,T,x", CONDITIONAL},
  281. { "extru",      0xd0001800, 0xfc001c00, ">b,P,T,x", CONDITIONAL},
  282. { "extrs",      0xd0001c00, 0xfc001c00, ">b,P,T,x", CONDITIONAL},
  283. { "zvdep",      0xd4000000, 0xfc001fe0, ">x,T,b", CONDITIONAL},
  284. { "vdep",       0xd4000400, 0xfc001fe0, ">x,T,b", CONDITIONAL},
  285. { "zdep",       0xd4000800, 0xfc001c00, ">x,p,T,b", CONDITIONAL},
  286. { "dep",        0xd4000c00, 0xfc001c00, ">x,p,T,b", CONDITIONAL},
  287. { "zvdepi",     0xd4001000, 0xfc001fe0, ">5,T,b", CONDITIONAL},
  288. { "vdepi",      0xd4001400, 0xfc001fe0, ">5,T,b", CONDITIONAL},
  289. { "zdepi",      0xd4001800, 0xfc001c00, ">5,p,T,b", CONDITIONAL},
  290. { "depi",       0xd4001c00, 0xfc001c00, ">5,p,T,b", CONDITIONAL},
  291.  
  292. /* System Control Instructions */
  293.  
  294. { "break",      0x00000000, 0xfc001fe0, "V,A"},
  295. { "rfi",        0x00000c00, 0xffffffff, ""},
  296. { "ssm",        0x00000d60, 0xffe0ffe0, "5,t"},
  297. { "rsm",        0x00000e60, 0xffe0ffe0, "5,t"},
  298. { "mtsm",       0x00001860, 0xffe0ffff, "x"},
  299. { "ldsid",      0x000010a0, 0xfc1f3fe0, "(s,b),t"},
  300. { "ldsid",      0x000010a0, 0xfc1f3fe0, "(b),t"},
  301. { "mtsp",       0x00001820, 0xffe01fff, "x,S"},
  302. { "mtctl",      0x00001840, 0xfc00ffff, "x,^"},
  303. { "mfsp",       0x000004a0, 0xffff1fe0, "S,t"},
  304. { "mfctl",      0x000008a0, 0xfc1fffe0, "^,t"},
  305. { "sync",       0x00000400, 0xffffffff, ""},
  306. { "prober",     0x04001180, 0xfc003fe0, "(s,b),x,t"},
  307. { "prober",     0x04001180, 0xfc003fe0, "(b),x,t"},
  308. { "proberi",    0x04003180, 0xfc003fe0, "(s,b),5,t"},
  309. { "proberi",    0x04003180, 0xfc003fe0, "(b),5,t"},
  310. { "probew",     0x040011c0, 0xfc003fe0, "(s,b),x,t"},
  311. { "probew",     0x040011c0, 0xfc003fe0, "(b),x,t"},
  312. { "probewi",    0x040031c0, 0xfc003fe0, "(s,b),5,t"},
  313. { "probewi",    0x040031c0, 0xfc003fe0, "(b),5,t"},
  314. { "lpa",        0x04001340, 0xfc003fc0, "Zx(s,b),t"},
  315. { "lpa",        0x04001340, 0xfc003fc0, "Zx(b),t"},
  316.  
  317. { "lha",        0x04001300, 0xfc003fc0, "Zx(s,b),t"},
  318. { "lha",        0x04001300, 0xfc003fc0, "Zx(b),t"},
  319.  
  320. { "pdtlb",      0x04001200, 0xfc003fdf, "Zx(s,b)"},
  321. { "pdtlb",      0x04001200, 0xfc003fdf, "Zx(b)"},
  322.  
  323. { "pitlb",      0x04000200, 0xfc003fdf, "Zx(s,b)"},
  324. { "pitlb",      0x04000200, 0xfc003fdf, "Zx(b)"},
  325.  
  326. { "pdtlbe",     0x04001240, 0xfc003fdf, "Zx(s,b)"},
  327. { "pdtlbe",     0x04001240, 0xfc003fdf, "Zx(b)"},
  328.  
  329. { "pitlbe",     0x04000240, 0xfc003fdf, "Zx(s,b)"},
  330. { "pitlbe",     0x04000240, 0xfc003fdf, "Zx(b)"},
  331.  
  332. { "idtlba",     0x04001040, 0xfc003fff, "x,(s,b)"},
  333. { "idtlba",     0x04001040, 0xfc003fff, "x,(b)"},
  334.  
  335. { "iitlba",     0x04000040, 0xfc003fff, "x,(s,b)"},
  336. { "iitlba",     0x04000040, 0xfc003fff, "x,(b)"},
  337.  
  338. { "idtlbp",     0x04001000, 0xfc003fff, "x,(s,b)"},
  339. { "idtlbp",     0x04001000, 0xfc003fff, "x,(b)"},
  340.  
  341. { "iitlbp",     0x04000000, 0xfc003fff, "x,(s,b)"},
  342. { "iitlbp",     0x04000000, 0xfc003fff, "x,(b)"},
  343.  
  344. { "pdc",        0x04001380, 0xfc003fdf, "Zx(s,b)"},
  345. { "pdc",        0x04001380, 0xfc003fdf, "Zx(b)"},
  346.  
  347. { "fdc",        0x04001280, 0xfc003fdf, "Zx(s,b)"},
  348. { "fdc",        0x04001280, 0xfc003fdf, "Zx(b)"},
  349.  
  350. { "fic",        0x04000280, 0xfc003fdf, "Zx(s,b)"},
  351. { "fic",        0x04000280, 0xfc003fdf, "Zx(b)"},
  352.  
  353. { "fdce",       0x040012c0, 0xfc003fdf, "Zx(s,b)"},
  354. { "fdce",       0x040012c0, 0xfc003fdf, "Zx(b)"},
  355.  
  356. { "fice",       0x040002c0, 0xfc003fdf, "Zx(s,b)"},
  357. { "fice",       0x040002c0, 0xfc003fdf, "Zx(b)"},
  358.  
  359. { "diag",       0x14000000, 0xfc000000, "D"},
  360.  
  361. /* Floating Point Coprocessor Instructions */
  362.  
  363. { "fldwx",      0x24000000, 0xfc001fc0, "cx(s,b),t"},
  364. { "fldwx",      0x24000000, 0xfc001fc0, "cx(b),t"},
  365.  
  366. { "flddx",      0x2c000000, 0xfc001fc0, "cx(s,b),t"},
  367. { "flddx",      0x2c000000, 0xfc001fc0, "cx(b),t"},
  368.  
  369. { "fstwx",      0x24000200, 0xfc001fc0, "ct,x(s,b)"},
  370. { "fstwx",      0x24000200, 0xfc001fc0, "ct,x(b)"},
  371.  
  372. { "fstdx",      0x2c000200, 0xfc001fc0, "ct,x(s,b)"},
  373. { "fstdx",      0x2c000200, 0xfc001fc0, "ct,x(b)"},
  374.  
  375. { "fldws",      0x24001000, 0xfc001fc0, "C5(s,b),t"},
  376. { "fldws",      0x24001000, 0xfc001fc0, "C5(b),t"},
  377.  
  378. { "fldds",      0x2c001000, 0xfc001fc0, "C5(s,b),t"},
  379. { "fldds",      0x2c001000, 0xfc001fc0, "C5(b),t"},
  380.  
  381. { "fstws",      0x24001200, 0xfc001fc0, "Ct,5(s,b)"},
  382. { "fstws",      0x24001200, 0xfc001fc0, "Ct,5(b)"},
  383.  
  384. { "fstds",      0x2c001200, 0xfc001fc0, "Ct,5(s,b)"},
  385. { "fstds",      0x2c001200, 0xfc001fc0, "Ct,5(b)"},
  386.  
  387. { "fadd",       0x30000600, 0xfc00e7e0, "Fb,x,t"},
  388. { "fsub",       0x30002600, 0xfc00e7e0, "Fb,x,t"},
  389. { "fmpy",       0x30004600, 0xfc00e7e0, "Fb,x,t"},
  390. { "fdiv",       0x30006600, 0xfc00e7e0, "Fb,x,t"},
  391. { "fsqrt",      0x30008000, 0xfc1fe7e0, "Fb,t"},
  392. { "fabs",       0x30006000, 0xfc1fe7e0, "Fb,t"},
  393. { "frem",       0x30008600, 0xfc00e7e0, "Fb,x,t"},
  394. { "frnd",       0x3000a000, 0xfc1fe7e0, "Fb,t"},
  395. { "fcpy",       0x30004000, 0xfc1fe7e0, "Fb,t"},
  396. { "fcnvff",     0x30000200, 0xfc1f87e0, "FGb,t"},
  397. { "fcnvxf",     0x30008200, 0xfc1f87e0, "FGb,t"},
  398. { "fcnvfx",     0x30010200, 0xfc1f87e0, "FGb,t"},
  399. { "fcnvfxt",    0x30018200, 0xfc1f87e0, "FGb,t"},
  400. { "fcmp",       0x30000400, 0xfc00e7e0, "FMb,x"},
  401. { "ftest",      0x30002420, 0xffffffff, ""},
  402.  
  403. /* Assist Instructions */
  404.  
  405. { "spop0",      0x10000000, 0xfc000600, ",f,On", NORMAL},
  406. { "spop1",      0x10000200, 0xfc000600, ",f,ont", NORMAL},
  407. { "spop2",      0x10000400, 0xfc000600, ",f,1nb", NORMAL},
  408. { "spop3",      0x10000600, 0xfc000600, ",f,0nx,b", NORMAL},
  409. { "copr",       0x30000000, 0xfc000000, ",u,2n", NORMAL},
  410. { "cldwx",      0x24000000, 0xfc001e00, ",u,Zx(s,b),t"},
  411. { "cldwx",      0x24000000, 0xfc001e00, ",u,Zx(b),t"},
  412. { "clddx",      0x2c000000, 0xfc001e00, ",u,Zx(s,b),t"},
  413. { "clddx",      0x2c000000, 0xfc001e00, ",u,Zx(b),t"},
  414. { "cstwx",      0x24000200, 0xfc001e00, ",u,Zt,x(s,b)"},
  415. { "cstwx",      0x24000200, 0xfc001e00, ",u,Zt,x(b)"},
  416. { "cstdx",      0x2c000200, 0xfc001e00, ",u,Zt,x(s,b)"},
  417. { "cstdx",      0x2c000200, 0xfc001e00, ",u,Zt,x(b)"},
  418. { "cldws",      0x24001000, 0xfc001e00, ",u,Z5(s,b),t"},
  419. { "cldws",      0x24001000, 0xfc001e00, ",u,Z5(b),t"},
  420. { "cldds",      0x2c001000, 0xfc001e00, ",u,Z5(s,b),t"},
  421. { "cldds",      0x2c001000, 0xfc001e00, ",u,Z5(b),t"},
  422. { "cstws",      0x24001200, 0xfc001e00, ",u,Zt,5(s,b)"},
  423. { "cstws",      0x24001200, 0xfc001e00, ",u,Zt,5(b)"},
  424. { "cstds",      0x2c001200, 0xfc001e00, ",u,Zt,5(s,b)"},
  425. { "cstds",      0x2c001200, 0xfc001e00, ",u,Zt,5(b)"},
  426. };
  427.  
  428. #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
  429.  
  430. /* SKV 12/18/92. Added some denotations for various operands. */
  431.  
  432. #define PA_IMM11_AT_31 'i'
  433. #define PA_IMM14_AT_31 'j'
  434. #define PA_IMM21_AT_31 'k'
  435. #define PA_DISP12 'w'
  436. #define PA_DISP17 'W'
  437.  
  438. #define N_HPPA_OPERAND_FORMATS 5
  439.