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- Re: the issue of clock-speed specmanship on 68040s vs. clock-speed
- specmanship on 486s, P5s, P6s, etc.
-
- OK, here's the real story. On, say, a 486DX-2/66, the processor
- core--on chip--runs at 66 MHz, while the bus interface runs at
- 33 MHz. This is significant because the core can, therefore,
- execute the most-commonly occuring, simple instructions at a
- rate of one per clock; i.e., under ideal conditions, it can
- really, truly execute instructions at a rate of 66 million per
- second (if only for a short burst). When it must go off chip
- to get, say, a data item, that data reference can only be
- satisfied at the slower 33-MHz rate.
-
- So, a "120-MHz" 486 can, under ideal conditions, execute instructions
- at a rate of 120 million per second.
-
- Now, when Apple decided to start calling its, for example, powerbooks
- "33/66-MHz" PowerBooks, I just had to laugh. This shows just how
- desparate they are. The 68040 does indeed use two different clocks signals.
- This is an implementation choice that does not necessarily have
- anything to do with exactly how the internal processor core operates.
-
- A "33/66-MHz" 68040 (or '040lc) can execute simple instructions
- under ideal circumstances at a maximum rate of 33 million per
- second. Motorola might have chosen to use a 133-Mhz clock input
- to the chip for implementation reasons, but that wouldn't make the
- core faster. The pipeline can retire simple instructions under ideal
- circumstances only at the 33-MHz rate. It's a 33-Mhz chip by any
- real measure.
-
- The "33/66-MHz" 68040 chips are the same chips that used to be called
- "33-MHz" 68040 chips.
-
- bcase
-
-