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TASM instructions definition Table | 1990-06-16 | 8.9 KB | 321 lines |
- "TASM 6800 Assembler. "
- /* This is the instruction set definition table
- /* for the 6800 version of TASM.
- /* K. Bertram. 24-March-1990
- /* First line of this file is a banner that will appear at the
- /* top of each page of the TASM listing file (not the same as
- /* the TITLE). Should be limited to 24 characters.
- /* Any other line that does not start with an uppercase letter is
- /* ignored.
- /* See TASM manual for info on table structure.
- /* Note that there are two classes of extended instructions beyond
- /* the standard set. The classes are assigned bits as follows:
- /* bit 0 = standard set
- /*
- /* THERE ARE SOME DIFFERENCES BETWEEN THE INDUSTRY STANDARD INSTRUCTION
- /* SET FOR THE 6800 AND THE INSTRUCTION SET USED HERE.
- /*
- /* 1. Direct (or zero page mode) requires that an 'R' be placed before
- /* the address. Thus treating it as a Register number instead of an
- /* address. eg: STA A,20 would now be STA A,R20
- /*
- /* 2. Indexed mode requires the register name to be a part of the mnemonic.
- /* eg: STAA 1,X
- /* or STA A1,X
- /*
- /* 3. Indexed mode on memory should include an 'i' after the mnemonic
- /* eg: CLR 0,x
- /* is now
- /* CLRi 0,x
- /*
- /*INSTR ARGS OPCODE BYTES MOD CLASS */
- /*----------------------------------*/
-
- ABA "" 1B 1 NOP 1
-
- ADC A,#* 89 2 NOP 1
- ADC A,R* 99 2 ZPAGE 1
- ADC A,* B9 3 SWAP 1
- ADCA *,X A9 2 NOP 1
- ADC A*,X A9 2 NOP 1
-
- ADC B,#* C9 2 NOP 1
- ADC B,R* D9 2 ZPAGE 1
- ADC B,* F9 3 SWAP 1
- ADCB *,X E9 2 NOP 1
- ADC B*,X E9 2 NOP 1
-
- ADD A,#* 8B 2 NOP 1
- ADD A,R* 9B 2 ZPAGE 1
- ADD A,* BB 3 SWAP 1
- ADDA *,X AB 2 NOP 1
- ADD A*,X AB 2 NOP 1
-
- ADD B,#* CB 2 NOP 1
- ADD B,R* DB 2 ZPAGE 1
- ADD B,* FB 3 SWAP 1
- ADDB *,X EB 2 NOP 1
- ADD B*,X EB 2 NOP 1
-
- AND A,#* 84 2 NOP 1
- AND A,R* 94 2 ZPAGE 1
- AND A,* B4 3 SWAP 1
- ANDA *,X A4 2 NOP 1
- AND A*,X A4 2 NOP 1
-
- AND B,#* C4 2 NOP 1
- AND B,R* D4 2 ZPAGE 1
- AND B,* F4 3 SWAP 1
- ANDB *,X E4 2 NOP 1
- AND B*,X E4 2 NOP 1
-
- ASL A 48 1 NOP 1
- ASL B 58 1 NOP 1
- ASL * 78 3 SWAP 1
- ASLi *,X 68 2 NOP 1
-
- ASR A 47 1 NOP 1
- ASR B 57 1 NOP 1
- ASR * 77 3 SWAP 1
- ASRi *,X 67 2 NOP 1
-
- BCC * 24 2 R1 1
- BCS * 25 2 R1 1
- BEQ * 27 2 R1 1
- BGE * 2C 2 R1 1
- BGT * 2E 2 R1 1
- BHI * 22 2 R1 1
- BLE * 2F 2 R1 1
- BLS * 23 2 R1 1
- BLT * 2D 2 R1 1
- BMI * 2B 2 R1 1
- BNE * 26 2 R1 1
- BPL * 2A 2 R1 1
- BRA * 20 2 R1 1
- BSR * 8D 2 R1 1
- BVC * 28 2 R1 1
- BVS * 29 2 R1 1
-
- BIT A,#* 85 2 NOP 1
- BIT A,R* 95 2 ZPAGE 1
- BIT A,* B5 3 SWAP 1
- BITA *,X A5 2 NOP 1
- BIT A*,X A5 2 NOP 1
-
- BIT B,#* C5 2 NOP 1
- BIT B,R* D5 2 ZPAGE 1
- BIT B,* F5 3 SWAP 1
- BITB *,X E5 2 NOP 1
- BIT B*,X E5 2 NOP 1
-
- CBA "" 11 1 NOP 1
- CLC "" 0C 1 NOP 1
- CLI "" 0E 1 NOP 1
- CLV "" 0A 1 NOP 1
-
- CLR A 4F 1 NOP 1
- CLR B 5F 1 NOP 1
- CLR * 7F 3 SWAP 1
- CLRi *,X 6F 2 NOP 1
-
- CMP A,#* 81 2 NOP 1
- CMP A,R* 91 2 ZPAGE 1
- CMP A,* B1 3 SWAP 1
- CMPA *,X A1 2 NOP 1
- CMP A*,X A1 2 NOP 1
-
- CMP B,#* C1 2 NOP 1
- CMP B,R* D1 2 ZPAGE 1
- CMP B,* F1 3 SWAP 1
- CMPB *,X E1 2 NOP 1
- CMP B*,X E1 2 NOP 1
-
- COM A 43 1 NOP 1
- COM B 53 1 NOP 1
- COM * 73 3 SWAP 1
- COMi *,X 63 2 NOP 1
-
- CPX #* 8C 3 SWAP 1
- CPX R* 9C 2 ZPAGE 1
- CPX * BC 3 SWAP 1
- CPXi *,X AC 2 NOP 1
-
- DAA "" 19 1 NOP 1
-
- DEC A 4A 1 NOP 1
- DEC B 5A 1 NOP 1
- DEC * 7A 3 SWAP 1
- DECi *,X 6A 2 NOP 1
-
- DES "" 34 1 NOP 1
- DEX "" 09 1 NOP 1
-
- EOR A,#* 88 2 NOP 1
- EOR A,R* 98 2 ZPAGE 1
- EOR A,* B8 3 SWAP 1
- EORA *,X A8 2 NOP 1
- EOR A*,X A8 2 NOP 1
-
- EOR B,#* C8 2 NOP 1
- EOR B,R* D8 2 ZPAGE 1
- EOR B,* F8 3 SWAP 1
- EORB *,X E8 2 NOP 1
- EOR B*,X E8 2 NOP 1
-
- INC A 4C 1 NOP 1
- INC B 5C 1 NOP 1
- INC * 7C 3 SWAP 1
- INCi *,X 6C 2 NOP 1
-
- INS "" 31 1 NOP 1
- INX "" 08 1 NOP 1
-
- JMP * 7E 3 SWAP 1
- JMPi *,X 6E 2 NOP 1
-
- JSR * BD 3 SWAP 1
- JSRi *,X AD 2 NOP 1
-
- LDA A,#* 86 2 NOP 1
- LDA A,R* 96 2 ZPAGE 1
- LDA A,* B6 3 SWAP 1
- LDAA *,X A6 2 NOP 1
- LDA A*,X A6 2 NOP 1
-
- LDA B,#* C6 2 NOP 1
- LDA B,R* D6 2 ZPAGE 1
- LDA B,* F6 3 SWAP 1
- LDAB *,X E6 2 NOP 1
- LDA B*,X E6 2 NOP 1
-
- LDS #* 8E 3 SWAP 1
- LDS R* 9E 2 ZPAGE 1
- LDS * BE 3 SWAP 1
- LDSi *,X AE 2 NOP 1
-
- LDX #* CE 3 SWAP 1
- LDX R* DE 2 ZPAGE 1
- LDX * FE 3 SWAP 1
- LDXi *,X EE 2 NOP 1
-
- LSR A 44 1 NOP 1
- LSR B 54 1 NOP 1
- LSR * 74 3 SWAP 1
- LSRi *,X 64 2 NOP 1
-
- NEG A 40 1 NOP 1
- NEG B 50 1 NOP 1
- NEG * 70 3 SWAP 1
- NEGi *,X 60 2 NOP 1
-
- NOP "" 01 1 NOP 1
-
- ORA A,#* 8A 2 NOP 1
- ORA A,R* 9A 2 ZPAGE 1
- ORA A,* BA 3 SWAP 1
- ORAA *,X AA 2 NOP 1
- ORA A*,X AA 2 NOP 1
-
- ORA B,#* CA 2 NOP 1
- ORA B,R* DA 2 ZPAGE 1
- ORA B,* FA 3 SWAP 1
- ORAB *,X EA 2 NOP 1
- ORA B*,X EA 2 NOP 1
-
- PSH A 36 1 NOP 1
- PSH B 37 1 NOP 1
-
- PUL A 32 1 NOP 1
- PUL B 33 1 NOP 1
-
- ROL A 49 1 NOP 1
- ROL B 59 1 NOP 1
- ROL * 79 3 SWAP 1
- ROLi *,X 69 2 NOP 1
-
- ROR A 46 1 NOP 1
- ROR B 56 1 NOP 1
- ROR * 76 3 SWAP 1
- RORi *,X 66 2 NOP 1
-
- RTI "" 3B 1 NOP 1
- RTS "" 39 1 NOP 1
-
- SBA "" 10 1 NOP 1
-
- SBC A,#* 82 2 NOP 1
- SBC A,R* 92 2 ZPAGE 1
- SBC A,* B2 3 SWAP 1
- SBCA *,X A2 2 NOP 1
- SBC A*,X A2 2 NOP 1
-
- SBC B,#* C2 2 NOP 1
- SBC B,R* D2 2 ZPAGE 1
- SBC B,* F2 3 SWAP 1
- SBCB *,X E2 2 NOP 1
- SBC B*,X E2 2 NOP 1
-
- SEC "" 0D 1 NOP 1
- SEI "" 0F 1 NOP 1
- SEV "" 0B 1 NOP 1
-
- STA A,R* 97 2 ZP 1
- STA A,* B7 3 SWAP 1
- STAA *,X A7 2 NOP 1
- STA A*,X A7 2 NOP 1
-
- STA B,R* D7 2 ZP 1
- STA B,* F7 3 SWAP 1
- STAB *,X E7 2 NOP 1
- STA B*,X E7 2 NOP 1
-
- STS R* 9F 2 ZPAGE 1
- STS * BF 3 SWAP 1
- STSi *,X AF 2 NOP 1
-
- STX R* DF 2 ZPAGE 1
- STX * FF 3 SWAP 1
- STXi *,X EF 2 NOP 1
-
- SUB A,#* 80 2 NOP 1
- SUB A,R* 90 2 ZPAGE 1
- SUB A,* B0 3 SWAP 1
- SUBA *,X A0 2 NOP 1
- SUB A*,X A0 2 NOP 1
-
- SUB B,#* C0 2 NOP 1
- SUB B,R* D0 2 ZPAGE 1
- SUB B,* F0 3 SWAP 1
- SUBB *,X E0 2 NOP 1
- SUB B*,X E0 2 NOP 1
-
- SWI "" 3F 1 NOP 1
- TAB "" 16 1 NOP 1
- TAP "" 06 1 NOP 1
- TBA "" 17 1 NOP 1
- TPA "" 07 1 NOP 1
-
- TST A 4D 1 NOP 1
- TST B 5D 1 NOP 1
- TST * 7D 3 SWAP 1
- TSTi *,X 6D 2 NOP 1
-
- TSX "" 30 1 NOP 1
- TXS "" 35 1 NOP 1
- WAI "" 3E 1 NOP 1
-
- /* Special m6800 instruction suitable only for the M6800-Emulator
- /* These opcodes are normally illegal Instructions to a normal
- /* M6800 CPU and could cause the machibe to crash. The assembler
- /* mask is bit ONE or "-x1" softswitch
-
- CHOUT A 41 1 NOP 2
- CHINT A 51 1 NOP 2
-
- IN A,X 61 1 NOP 2
- IN B,X 62 1 NOP 2
-
- OUT X,A 71 1 NOP 2
- OUT X,B 72 1 NOP 2
-
-