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- module limit flag '-r0','-f'
- title 'between limits comparator from MMI PAL handbook
- Michael Holley FutureNet - Data I/O 11 Jan 1986'
-
- L1 device 'P16X4';
-
- Clk,OC2,OC1 pin 1,9,11;
- Load,Clear pin 2,3;
- NE,EQ,LT,GT pin 12,13,18,19;
- B0,B1,B2,B3 pin 4,5,6,7;
- A3,A2,A1,A0 pin 14,15,16,17;
-
- No,Yes,X,C,Z = 1, 0, .X., .C., .Z.;
- Bus = [B3,B2,B1,B0];
- Reg = [A3,A2,A1,A0];
-
- "These macros are used to create a JEDEC file for the
- "arithmetic PALs such as the 16X4 and 16A4. Valid test
- "vectors can be generated for the device programmer
- "but ABEL can not simulate these equations.
-
- "Reduction level -r0 must always be used.
-
- "Fixed symbol macros
- A macro (n) { A?n & !A?n}; " (A)
- NA macro (n) { B?n & !B?n}; " (/A)
- B macro (n) { B?n & A?n}; " (B)
- NB macro (n) {!B?n & !A?n}; " (/B)
-
- A_OR_B macro (n) { A?n}; " (A+B)
- NA_OR_B macro (n) { B?n}; " (/A+B)
- N_OR_NB macro (n) {!A?n}; " (A+/B)
- NA_OR_NB macro (n) {!B?n}; " (/A+/B)
-
- A_AND_B macro (n) { B?n & A?n & !A?n}; " (A*B)
- NA_AND_B macro (n) { B?n & !B?n & A?n}; " (/A*B)
- A_AND_NB macro (n) {!B?n & A?n & !A?n}; " (A*/B)
- NA_AND_NB macro (n) { B?n & !B?n & !A?n}; " (/A*/B)
-
- A_XNOR_B macro (n) { B?n & !A?n}; " (A:*:B)
- A_XOR_B macro (n) {!B?n & A?n}; " (A:+:B)
-
- @page
- equations
- enable [LT,GT,EQ,NE] = !OC2;
-
- !LT = A_AND_NB(3)
- # A_XNOR_B(3) & A_AND_NB(2)
- # A_XNOR_B(3) & A_XNOR_B(2) & A_AND_NB(1)
- # A_XNOR_B(3) & A_XNOR_B(2) & A_XNOR_B(1) & A_AND_NB(0);
-
- !GT = NA_AND_B(3)
- # A_XNOR_B(3) & NA_AND_B(2)
- # A_XNOR_B(3) & A_XNOR_B(2) & NA_AND_B(1)
- # A_XNOR_B(3) & A_XNOR_B(2) & A_XNOR_B(1) & NA_AND_B(0);
-
- !EQ = A_XNOR_B(3) & A_XNOR_B(2) & A_XNOR_B(1) & A_XNOR_B(0);
-
- !NE = A_XOR_B(3) # A_XOR_B(2) # A_XOR_B(1) # A_XOR_B(0);
-
- !A3 := NA(3) * !Load # NB(3) * Load # Clear;
-
- !A2 := NA(2) * !Load # NB(2) * Load # Clear;
-
- !A1 := NA(1) * !Load # NB(1) * Load # Clear;
-
- !A0 := NA(0) * !Load # NB(0) * Load # Clear;
-
- test_vectors 'These are for the programmer only'
- ([Clk,OC1,OC2,Load,Clear, Bus] -> [ Reg, LT, EQ, NE, GT])
- [ C , 0 , 0 , 0 , 1 , X ] -> [ ^h0, X, X, X, X];" Clear
- [ C , 0 , 0 , 1 , 0 , ^h0] -> [ ^h0, X, X, X, X];" Load
- [ 0 , 0 , 0 , 0 , 0 , ^h0] -> [ ^h0, No,Yes, No, No];" 0 = 0
- [ 0 , 0 , 0 , 0 , 0 , ^h1] -> [ ^h0, No, No,Yes,Yes];" 1 > 0
- [ 0 , 0 , 0 , 0 , 0 , X ] -> [ ^h0, X, X, X, X];" Read
-
- [ C , 0 , 0 , 0 , 1 , X ] -> [ ^h0, X, X, X, X];" Clear
- [ C , 0 , 0 , 1 , 0 , ^h5] -> [ ^h5, X, X, X, X];" Load
- [ 0 , 0 , 0 , 0 , 0 , ^h0] -> [ ^h5,Yes, No,Yes, No];" 0 = 5
- [ 0 , 0 , 0 , 0 , 0 , ^h5] -> [ ^h5, No,Yes, No, No];" 5 = 5
- [ 0 , 0 , 0 , 0 , 0 , ^hF] -> [ ^h5, No, No,Yes,Yes];" F > 5
- [ 0 , 0 , 0 , 0 , 0 , X ] -> [ ^h5, X, X, X, X];" Read
-
- [ C , 0 , 0 , 0 , 1 , X ] -> [ ^h0, X, X, X, X];" Clear
- [ C , 0 , 0 , 1 , 0 , ^hA] -> [ ^hA, X, X, X, X];" Load
- [ 0 , 0 , 0 , 0 , 0 , ^h4] -> [ ^hA,Yes, No,Yes, No];" 4 < A
- [ 0 , 0 , 0 , 0 , 0 , ^hA] -> [ ^hA, No,Yes, No, No];" A = A
- [ 0 , 0 , 0 , 0 , 0 , ^hB] -> [ ^hA, No, No,Yes,Yes];" B > A
- [ 0 , 0 , 0 , 0 , 0 , X ] -> [ ^hA, X, X, X, X];" Read
-
- [ C , 0 , 0 , 0 , 1 , X ] -> [ ^h0, X, X, X, X];" Clear
- [ C , 0 , 0 , 1 , 0 , ^hF] -> [ ^hF, X, X, X, X];" Load
- [ 0 , 0 , 0 , 0 , 0 , ^hE] -> [ ^hF,Yes, No,Yes, No];" E < F
- [ 0 , 0 , 0 , 0 , 0 , ^hF] -> [ ^hF, No,Yes, No, No];" F = F
- [ 0 , 0 , 0 , 0 , 0 , X ] -> [ ^hF, X, X, X, X];" Read
-
- [ C , 0 , 0 , 0 , 0 , X ] -> [ ^hF, X, X, X, X];" Hold
- [ 0 , 1 , 0 , 0 , 0 , X ] -> [ Z , X, X, X, X];" Hi Z
- [ 0 , 0 , 1 , 0 , 0 , X ] -> [ X , Z, Z, Z, Z];" Hi Z
- end
-