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- module BGATES flag '-v'
- title 'Basic Gates example from MMI PAL handbook
- Michael Holley Data I/O Corp 08 Mar 1984'
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- P7000 device 'P12H6';
- A,C,D,F,G,I,J,K,M,N,P,Q pin 19,1,2,3,4,9,11,12,5,6,7,8;
- B,E,H,L,O,R pin 18,17,16,13,15,14;
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- equations
- B = !A; " Inverter
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- E = C & D; " And Gate
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- H = F # G; " Or Gate
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- !L = I & J & K; " Nand Gate
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- !O = M # N; " Nor Gate
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- R = P $ Q; " Exclusive Or Gate
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- test_vectors 'Test Inverter'
- ( A -> B )
- 0 -> 1;
- 1 -> 0;
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- test_vectors 'Test And Gate'
- ( [C,D] -> E )
- [0,0] -> 0;
- [0,1] -> 0;
- [1,0] -> 0;
- [1,1] -> 1;
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- test_vectors 'Test Or Gate'
- ( [F,G] -> H )
- [0,0] -> 0;
- [0,1] -> 1;
- [1,0] -> 1;
- [1,1] -> 1;
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- test_vectors 'Test Nand Gate'
- ( [I,J,K] -> L )
- [0,0,0] -> 1;
- [1,0,0] -> 1;
- [0,1,0] -> 1;
- [0,0,1] -> 1;
- [1,1,1] -> 0;
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- test_vectors 'Test Nor Gate'
- ( [M,N] -> O )
- [0,0] -> 1;
- [0,1] -> 0;
- [1,0] -> 0;
- [1,1] -> 0;
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- test_vectors 'Test Exclusive Or Gate'
- ( [P,Q] -> R )
- [0,0] -> 0;
- [0,1] -> 1;
- [1,0] -> 1;
- [1,1] -> 0;
- end BGATES
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