Liren Large Software Subsidy 13/13.iso/p/p195/1.ddi/STANDARD.DOC

Text File | 1989-12-26 | 7.3 KB | 134 lines

        Guidelines for AnaCMOSLib and SCMOSLib Standard Cell Layout

This file has two purposes:

 1) To ensure that custom cells added to the library by the user remain
    design rule correct when placed adjacent to AnaCMOSLib and SCMOSLib cells.

 2) To ensure that custom cells added to the library by the user are
    compatible with L-Edit's Standard Cell Place and Route facility.

Note that some of these rules are a little more restrictive than absolutely
necessary but are written to keep them simple and to keep the designer
from having to do extensive case-analysis on each new cell.

SCMOSLib and AnaCMOSLib cells are 66 lambda high, measured from the bottom of
the lower power rail to the top of the upper power rail.

Each cell must have an Abut port.  This port must extend from the bottom left
corner of the lower power rail to the top right corner of the upper power
rail.  It must be on the icon layer and be called 'Abut' (Note: Capital 'A',
lower case 'but').  This port is used by the Standard Cell Place and Route
module in L-Edit to place the cells side by side correctly.  Note that some
geometry may extend outside of the boundaries of the Abut port (e.g. well).
The lower left corner of the Abut port must be at the origin - coordinate
(0,0).

Power rails are 8 lambda high.  Both must have an 8 lambda high and 0 lambda
wide port at each end.  The upper ones must be named 'Vdd' (Note: capital 'V',
lower case 'dd') and the lower ones 'Gnd' (again, only the 'G' is
capitalized).

This set was designed to conform to the MOSIS scalable CMOS 'simpler' rules.
Therefore the required active surrounding active contact is 2 lambda and the
required poly surrounding poly contact is 2 lambda.  The simpler rules were
chosen to maximize yield, especially in large chips.  Note that some of the
pads use the denser rules, because they can be designed for a specific
technology (e.g. 2um).

In p-well, the well starts from 5 lambda below the bottom of the lower power
rail and is 38 lambda high.  In n-well, the well starts 5 lambda above the top
of the power rail and descends 38 lambda.  The well must extend 5 lambda
beyond the left and right edges of the cell.

In n-well, the select starts 2 lambda below the Abut port and extends upward
for 32 lambda.  In p-well, the select starts 2 lambda above the Abut port and
extends downward for 32 lambda.  Select extends exactly to the edge of the
cell with the possible exception of well and substrate contacts.

All other layers (and combinations of layers, eg. transistor) must stop one
half (rounded up) a separation design rule from the sides of the cell.
(Exception: See substrate and well contacts below.)  Active may be coincedent
with the top or bottom of the Abut port.  Select must extend 2 lambda above
the top or below the bottom of the abut port except for substrate contacts.
Well must extend 5 lambda beyond the top or bottom edges.  Poly may extend 2
lambda above the top or below the bottom edges of the cell.  A Metal1 to
Metal2 contact may be in the channel with the Metal2 as close as 3 lambda from
the top or bottom edge of the Abut port.  Thus all Metal2 within the cell must
stay 1 lambda or more inside the top and bottom of the Abut port.

Substrate and well contacts may touch the sides of the Abut port.  The active
region for such contacts must be 6 lambda high.  They must be flush with the
left or right end and with the bottom of the lower rail or the top of the
upper rail of the power rail that they are attached to.  To state it in
another way, they must be in the corners of the 'Abut' port.  In the case of a
substrate contact, the select is absent from the first 7 lambda up from the
bottom of the bottom power rail or down from the top of the top power rail.
The select extends to the edge of the cell from 7 lambda up to 30 lambda or
from 59 lambda down to 36 lambda.  For well contacts in the corners, the
select extends 1 lambda outside the abut port horizontally and 2 lambda
outside the abut port vertically.  The select extends vertically inside the
abut port for only 5 lambda.

Note that if there is not a substrate or well contact in the corner, then
clearance must be provided for the case where an adjacent cell does have such
a contact.  Since the adjacent contact, consisting of active area is flush
against the boundary of the cell, an area must be clear of active by a full
separation design rule, 3 lambda, in the corner.  For well contacts, the
select extends 1 lambda into the adjacent cell.  Thus separate select regions
must stay 3 lambda inside the abut port near the corners.  Also beware of
transistors near the corners - they must stay 3 lambda away from possible well
or substrate contacts in adjacent cells.

For a simple example, refer to the inverter cell in SCMOSLib.  Run L-Edit and
Open the file SCNLIB.TDB.  Open the cell INV.  In the lower left corner is a
substrate contact.  In the lower right is a clear area.  In the upper left is
a well contact, and in the upper right is a clear area.

All cells must have a well contact for every piece of well in that cell (most
cells have only a single well region).  It is also a good idea to have
multiple well contacts if the cell gets too wide.  We rcommend one about every
50 lambda or so.  Although not strictly required, we recommend a substrate
contact in each cell and more for wide cells.

All inputs and outputs are routed through vias to metal2.  A 4x4 lambda metal2
box is put around each via.  A 4 lambda wide and 0 lambda high port is put
through the center of this metal2 box.  There may not be any metal2 (including
other input and output ports) in a vertical channel 12 lambda wide centered on
the port.  This is because L-Edit's Standard Cell Place and Route utility may
run a wire of metal2 in from the top or the bottom of the cell to meet the
port, and this wire must maintain a minimum design rule separation of 4 lambda
from other metal2 in the cell.  Metal2 may be used in a cell, but room must be
left to access ports both from above and below.  L-Edit does not check for
obstructions within a cell when routing in from above or below.

Cells must be design rule correct by themselves.  No end-caps are placed at
row ends.

As line widths get narrower, there is some indication that bends in
transistors may cause problems and should be avoided.  Knowledgeable sources
agree that at 3um and 2um technologies, bent transistors are not a problem.
There seems to be no clear consensus on what line width technologies it does
become a problem.  We have chosen to design the digital SCMOSLib cells with no
bends in the transistors.  The AnaCMOSLib cells on the other hand are based on
those from Carver Mead, who feels that bends are acceptible for our present
MOSIS fabrication technologies.  We recommend that anyone creating new cells
use only straight transistors to minimize the chance of problems and to
maximize the useful life of your geometry.


If you find any errors or omissions, please call or write to us at the address
below.

AnaCMOSLib, SCMOSLib and L-Edit are trademarks of Tanner Research, Inc.
Other brand and product names are trademarks or registered trademarks of their
respective holders.  Copyright (c) 1989 Tanner Research, Inc.  All rights
reserved.

Tanner Research, Inc.
444 North Altadena Drive
Pasadena, CA  91107

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