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- BIT STREAM CLOCK GENERATOR
-
- Here is an example of a stream used to define a repetitive clock. The
- stream starts with eight ones and ends with eight zeros. In between are
- fifteen sets of the following sequence: three zeros, three one-zero
- cycles, a zero, and six ones. The logic is intended to be driven by a
- counter generating the eight-bit STEP signal.
-
- |PAL16C1 in:STEP[7..0], out:Y
- |
- | Title: "Bit stream clock generator"
- |
- | Stream: STEP[7..0] -> Y
- | { 8(1), 15(3(0), 3(1,0), 0, 6(1)), 8(0) }
- |
- |
- | Vectors:
- | { Display (STEP[7..0])d, Y
- | Test STEP[7..0]
- | End
- | }
-
-