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- ADDRESSABLE FLIP-FLOPS
-
- This set of eight addressable SR flip-flops uses feedback on all outputs,
- so complex mode is not sufficient and registered mode must be selected,
- even though no registers are used in the device.
-
- Whenever the SET line is active, the flip-flop addressed by ADDR[2..0] is
- activated. Whenever the SET line is inactive and the RESET line is
- active, the flip-flop addresses by ADDR[2..0] is cleared. When both SET
- and RESET are inactive, all flip-flops retain their values.
-
- |GAL16V8 in:(ADDR[2..0], SET, RESET), io:Q[7..0]
- |
- | i=7..0: Q[i] = (ADDR[2..0]==i & SET)
- | # (Q[i] & (ADDR[2..0]==i & RESET)')
- |
- | Vectors:
- | { Display (ADDR[2..0])d, SET, RESET, " -> ", Q[7..0]
- | Test ADDR[2..0]; SET, RESET = 00b, 01b, 00b, 10b, 00b
- | End }
-
-