Liren Large Software Subsidy 13

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(***************************************************************************) (* *) (* Copyright (C) 1987-1990 *) (* by Gogesch Micro Systems, INC. *) (* *) (* All rights reserved. *) (* *) (***************************************************************************) ;The following is the HC library. ; ;Unless otherwise stated the delays for the following parts are - ; Tplh and Tphl for 15pf and 50 pf respectively. ; ;Unless otherwise stated, delays for flip flops taken from the national ;databook have the following exceptions to the databook - ;The delays for minimum low level clock was extrapolated - ;period - clock high = clock low. ;The min. removal time preset or clear to clock is entered as zero. ; ;Unless otherwise specified the delays for the following devices were ;taken from the National 1984 Logic Databook. ; ; :74HC00 TTL 14 NAND(P1,P2;P3;15,15,23,23); NAND(P4,P5;P6;15,15,23,23); NAND(P10,P9;P8;15,15,23,23); NAND(P13,P12;P11;15,15,23,23); % :74HC00A TTL 14 NAND(P1,P2;P3;15,15,23,23); NAND(P4,P5;P6;15,15,23,23); NAND(P10,P9;P8;15,15,23,23); NAND(P13,P12;P11;15,15,23,23); % :74HC02 TTL 14 NOR(P2,P3;P1;15,15,23,23); NOR(P5,P6;P4;15,15,23,23); NOR(P8,P9;P10;15,15,23,23); NOR(P11,P12;P13;15,15,23,23); % :74HC02A TTL 14 NOR(P2,P3;P1;15,15,23,23); NOR(P5,P6;P4;15,15,23,23); NOR(P8,P9;P10;15,15,23,23); NOR(P11,P12;P13;15,15,23,23); % :74HC03 TTL 14 SET(RHIGH); NAND(P1,P2;P3;26,20,32,32); NAND(P4,P5;P6;26,20,32,32); NAND(P10,P9;P8;26,20,32,32); NAND(P13,P12;P11;26,20,32,32); % :74HC03A TTL 14 SET(RHIGH); NAND(P1,P2;P3;26,20,32,32); NAND(P4,P5;P6;26,20,32,32); NAND(P10,P9;P8;26,20,32,32); NAND(P13,P12;P11;26,20,32,32); % :74HC04 TTL 14 INV(P1;P2;15,15,24,24); INV(P3;P4;15,15,24,24); INV(P5;P6;15,15,24,24); INV(P9;P8;15,15,24,24); INV(P11;P10;15,15,24,24); INV(P13;P12;15,15,24,24); % :74HC04A TTL 14 INV(P1;P2;15,15,24,24); INV(P3;P4;15,15,24,24); INV(P5;P6;15,15,24,24); INV(P9;P8;15,15,24,24); INV(P11;P10;15,15,24,24); INV(P13;P12;15,15,24,24); % ;Data for the following device was taken from 1988 ;High Speed CMOS Data Book. :74HC05 TTL 14 SET(RHIGH); INV(P1;P2;19,11,29,21); INV(P3;P4;19,11,29,21); INV(P5;P6;19,11,29,21); INV(P9;P8;19,11,29,21); INV(P11;P10;19,11,29,21); INV(P13;P12;19,11,29,21); % :74HC08 TTL 14 AND(P1,P2;P3;15,20,23,30); AND(P4,P5;P6;15,20,23,30); AND(P10,P9;P8;15,20,23,30); AND(P13,P12;P11;15,20,23,30); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC09 TTL 14 SET(RHIGH); AND(P1,P2;P3;21,15,31,25); AND(P4,P5;P6;21,15,31,25); AND(P10,P9;P8;21,15,31,25); AND(P13,P12;P11;21,15,31,25); % :74HC10 TTL 14 NAND(P1,P2,P13;P12;15,15,23,23); NAND(P3,P4,P5;P6;15,15,23,23); NAND(P11,P10,P9;P8;15,15,23,23); % :74HC11 TTL 14 AND(P1,P2,P13;P12;20,20,31,31); AND(P3,P4,P5;P6;20,20,31,31); AND(P11,P10,P9;P8;20,20,31,31); % :74HC14 TTL 14 INV(P1;P2;22,22,31,31); INV(P3;P4;22,22,31,31); INV(P5;P6;22,22,31,31); INV(P9;P8;22,22,31,31); INV(P11;P10;22,22,31,31); INV(P13;P12;22,22,31,31); % :74HC14A TTL 14 INV(P1;P2;22,22,31,31); INV(P3;P4;22,22,31,31); INV(P5;P6;22,22,31,31); INV(P9;P8;22,22,31,31); INV(P11;P10;22,22,31,31); INV(P13;P12;22,22,31,31); % :74HC20 TTL 14 NAND(P1,P2,P4,P5;P6;15,15,23,23); NAND(P9,P10,P12,P13;P8;15,15,23,23); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC21 TTL 14 AND(P1,P2,P4,P5;P6;18,18,28,28); AND(P9,P10,P12,P13;P8;18,18,28,28); % :74HC27 TTL 14 NOR(P1,P2,P13;P12;15,15,23,23); NOR(P3,P4,P5;P6;15,15,23,23); NOR(P11,P10,P9;P8;15,15,23,23); % :74HC30 TTL 14 NAND(P1,P2,P3,P4,P5,P6,P11,P12;P8;30,30,42,42); % :74HC32 TTL 14 OR(P1,P2;P3;18,18,25,25); OR(P4,P5;P6;18,18,25,25); OR(P10,P9;P8;18,18,25,25); OR(P12,P13;P11;18,18,25,25); % :74HC32A TTL 14 OR(P1,P2;P3;18,18,25,25); OR(P4,P5;P6;18,18,25,25); OR(P10,P9;P8;18,18,25,25); OR(P12,P13;P11;18,18,25,25); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC36 TTL 14 NOR(P1,P2;P3;15,15,25,25); NOR(P4,P5;P6;15,15,25,25); NOR(P9,P10;P8;15,15,25,25); NOR(P12,P13;P11;15,15,25,25); % :74HC42 TTL 16 LINV(P15;L1); LINV(P14;L2); LINV(P13;L3); LINV(P12;L4); NAND(L1,L2,L3,L4;P1;25,25,38,38); NAND(P15,L2,L3,L4;P2;25,25,38,38);; NAND(L1,P14,L3,L4;P3;25,25,38,38); NAND(P15,P14,L3,L4;P4;25,25,38,38); NAND(L1,L2,P13,L4;P5;25,25,38,38); NAND(P15,L2,P13,L4;P6;25,25,38,38); NAND(L1,P14,P13,L4;P7;25,25,38,38); NAND(P15,P14,P13,L4;P9;25,25,38,38); NAND(L1,L2,L3,P12;P10;25,25,38,38); NAND(P15,L2,L3,P12;P11;25,25,38,38); % :74HC51 TTL 14 LAND(P2,P3;L1); LAND(P4,P5;L2); LAND(P1,P13,P12;L3); LAND(P11,P10,P9;L4); NOR(L1,L2;P6;20,20,32,32); NOR(L3,L4;P8;20,20,32,32); % :74HC73 TTL 14 INV(P1;N1;0,0,0,0); INV(P5;N2;0,0,0,0); JKFFC(P14,P3,N1,P2;P12,P13;21,21,20,0,16,16,26,26,16,20,32,32,25,0,20,25,39,39,20,25); JKFFC(P7,P10,N2,P6;P9,P8;21,21,20,0,16,16,26,26,16,20,32,32,25,0,20,25,39,39,20,25); % :74HC74 TTL 14 DFFPC(P2,P3,P4,P1;P5,P6;30,30,20,0,16,17,40,40,16,5,44,44,25,0,20,20,58,58,20,6); DFFPC(P12,P11,P10,P13;P9,P8;30,30,20,0,16,17,40,40,16,5,44,44,25,0,20,20,58,58,20,6); % :74HC75 TTL 16 LINV(P2;L1); LINV(P3;L2); LINV(P6;L3); LINV(P7;L4); DLATCH(L1,P13;P1;20,20,23,23,20,0,16,28,28,31,31,25,0,20); DLATCH(L2,P13;P14;20,20,23,23,20,0,16,28,28,31,31,25,0,20); DLATCH(L3,P4;P11;20,20,23,23,20,0,16,28,28,31,31,25,0,20); DLATCH(L4,P4;P8;20,20,23,23,20,0,16,28,28,31,31,25,0,20); DLATCH(P2,P13;P16;20,20,23,23,20,0,16,28,28,31,31,25,0,20); DLATCH(P3,P13;P15;20,20,23,23,20,0,16,28,28,31,31,25,0,20); DLATCH(P6,P4;P10;20,20,23,23,20,0,16,28,28,31,31,25,0,20); DLATCH(P7,P4;P9;20,20,23,23,20,0,16,28,28,31,31,25,0,20); % :74HC76 TTL 16 INV(P1;N1;0,0,0,0); INV(P6;N2;0,0,0,0); JKFFPC(P4,P16,N1,P2,P3;P15,P14;21,21,20,0,16,16,26,26,16,20,31,31,25,0,20,20,39,39,20,25); JKFFPC(P9,P12,N2,P7,P8;P11,P10;21,21,20,0,16,16,26,26,16,20,31,31,25,0,20,20,39,39,20,25); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC77 TTL 14 DLATCH(P1,P12;P14;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(P2,P12;P13;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(P5,P3;P9;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(P6,P3;P8;20,20,23,23,25,5,20,30,30,33,33,25,5,20); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC78 TTL 14 INV(P1;N1;0,0,0,0); JKFFPC(P3,P14,N1,P2,P5;P13,P12;22,22,30,0,20,20,29,29,20,30,32,32,30,0,20,20,39,39,20,30); JKFFPC(P10,P7,N1,P6,P5;P8,P9;22,22,30,0,20,20,29,29,20,30,32,32,30,0,20,20,39,39,20,30); % ;taken from 1984 National Logic Data Book. ;Data for A,B to A=B output is not modeled precisely. :74HC85 TTL 16 LNAND(P15,P1;L1); LNAND(P13,P14;L2); LNAND(P12,P11;L3); LNAND(P10,P9;L4); LAND(P15,L1;L5); LAND(L1,P1;L6); LAND(P13,L2;L7); LAND(L2,P14;L8); LAND(P12,L3;L9); LAND(L3,P11;L10); LAND(P10,L4;L11); LAND(L4,P9;L12); NOR(L5,L6;N1;10,10,14,14); NOR(L7,L8;N2;10,10,14,14); NOR(L9,L10;N3;10,10,14,14); NOR(L11,L12;N4;10,10,14,14); BUF(L6;N5;10,10,14,14); BUF(L5;N6;10,10,14,14); LAND(P14,L2,N1;L13); LAND(P11,L3,N1,N2;L14); LAND(P9,L4,N1,N2,N3;L15); LAND(N1,N2,N3,N4,P2;L16); LAND(N1,N2,N3,N4,P3;L17); LAND(P3,N4,N3,N2,N1;L18); LAND(P4,N4,N2,N3,N1;L19); LAND(N3,N2,N1,L4,P10;L20); LAND(N2,N1,L3,P12;L21); LAND(N1,L2,P13;L22); NOR(N5,L13,L14,L15,L16,L17;P5;26,26,39,39); NOR(L18,L19,L20,L21,L22,N6;P7;26,26,39,39); AND(N1,N2,P3,N3,N4;P6;20,20,32,32); % :74HC86 TTL 14 XOR(P1,P2;P3;20,20,30,30); XOR(P4,P5;P6;20,20,30,30); XOR(P10,P9;P8;20,20,30,30); XOR(P13,P12;P11;20,20,30,30); % :74HC107 TTL 14 INV(P12;N1;0,0,0,0); INV(P9;N2;0,0,0,0); JKFFC(P1,P4,N1,P13;P3,P2;21,21,20,0,16,17,26,26,16,20,32,32,25,0,20,28,39,39,20,25); JKFFC(P8,P11,N2,P10;P5,P6;21,21,20,0,16,17,26,26,16,20,32,32,25,0,20,28,39,39,20,25); % :74HC109 TTL 16 LINV(P3;L1); LINV(P13;L2); JKFFPC(P2,L1,P4,P5,P1;P6,P7;30,30,20,0,16,17,42,42,16,5,44,44,25,0,20,28,58,58,20,6); JKFFPC(P14,L2,P12,P11,P15;P10,P9;30,30,20,0,16,17,42,42,16,5,44,44,25,0,20,28,58,58,20,6); % :74HC109A TTL 16 LINV(P3;L1); LINV(P13;L2); JKFFPC(P2,L1,P4,P5,P1;P6,P7;30,30,20,0,16,17,42,42,16,5,44,44,25,0,20,28,58,58,20,6); JKFFPC(P14,L2,P12,P11,P15;P10,P9;30,30,20,0,16,17,42,42,16,5,44,44,25,0,20,28,58,58,20,6); % :74HC112 TTL 16 INV(P1;N1;0,0,0,0); INV(P13;N2;0,0,0,0); JKFFPC(P3,P2,N1,P4,P15;P5,P6;21,21,20,0,16,17,28,28,16,20,32,32,25,0,20,28,41,41,20,25); JKFFPC(P11,P12,N2,P10,P14;P9,P7;21,21,20,0,16,17,28,28,16,20,32,32,25,0,20,28,41,41,20,25); % :74HC113 TTL 14 INV(P1;N1;0,0,0,0); INV(P13;N2;0,0,0,0); JKFFP(P3,P2,N1,P4;P5,P6;21,21,20,0,16,17,28,28,16,20,32,32,25,0,20,28,41,41,20,25); JKFFP(P11,P12,N2,P10;P9,P8;21,21,20,0,16,17,28,28,16,20,32,32,25,0,20,28,41,41,20,25); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC114 TTL 14 INV(P13;N1;0,0,0,0); JKFFPC(P3,P2,N1,P4,P1;P5,P6;34,34,25,0,25,25,34,34,25,25,44,44,25,0,25,25,44,44,25,25); JKFFPC(P11,P12,N1,P10,P1;P9,P8;34,34,25,0,25,25,34,34,25,25,44,44,25,0,25,25,44,44,25,25); % :74HC125 TTL 14 LINV(P1;L1); LINV(P4;L2); LINV(P10;L3); LINV(P13;L4); BUF(P2;N1;18,18,25,25); BUF(P5;N2;18,18,25,25); BUF(P9;N3;18,18,25,25); BUF(P12;N4;18,18,25,25); TSB(N1,L1;P3;31,31,31,31,31,31,31,31); TSB(N2,L2;P6;31,31,31,31,31,31,31,31); TSB(N3,L3;P8;31,31,31,31,31,31,31,31); TSB(N4,L4;P11;31,31,31,31,31,31,31,31); % :74HC125A TTL 14 LINV(P1;L1); LINV(P4;L2); LINV(P10;L3); LINV(P13;L4); BUF(P2;N1;18,18,25,25); BUF(P5;N2;18,18,25,25); BUF(P9;N3;18,18,25,25); BUF(P12;N4;18,18,25,25); TSB(N1,L1;P3;31,31,31,31,31,31,31,31); TSB(N2,L2;P6;31,31,31,31,31,31,31,31); TSB(N3,L3;P8;31,31,31,31,31,31,31,31); TSB(N4,L4;P11;31,31,31,31,31,31,31,31); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50pF and 150pF are given :74HC126 TTL 14 BUF(P2;N1;30,30,38,38); BUF(P5;N2;30,30,38,38); BUF(P9;N3;30,30,38,38); BUF(P12;N4;30,30,38,38); TSB(N1,P1;P3;30,30,30,30,36,36,36,36); TSB(N2,P4;P6;30,30,30,30,36,36,36,36); TSB(N3,P10;P8;30,30,30,30,36,36,36,36); TSB(N4,P13;P11;30,30,30,30,36,36,36,36); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50pF and 150pF are given :74HC126A TTL 14 BUF(P2;N1;30,30,38,38); BUF(P5;N2;30,30,38,38); BUF(P9;N3;30,30,38,38); BUF(P12;N4;30,30,38,38); TSB(N1,P1;P3;30,30,30,30,36,36,36,36); TSB(N2,P4;P6;30,30,30,30,36,36,36,36); TSB(N3,P10;P8;30,30,30,30,36,36,36,36); TSB(N4,P13;P11;30,30,30,30,36,36,36,36); % :74HC132 TTL 14 NAND(P1,P2;P3;20,20,32,32); NAND(P4,P5;P6;20,20,32,32); NAND(P10,P9;P8;20,20,32,32); NAND(P13,P12;P11;20,20,32,32); % :74HC132A TTL 14 NAND(P1,P2;P3;20,20,32,32); NAND(P4,P5;P6;20,20,32,32); NAND(P10,P9;P8;20,20,32,32); NAND(P13,P12;P11;20,20,32,32); % :74HC133 TTL 16 NAND(P1,P2,P3,P4,P5,P6,P7,P10,P11,P12,P13,P14,P15;P9;30,30,42,42); % ;Data for the following device was taken from ;1988 TI High Speed CMOS Logic Data Book. :74HC137 TTL 16 LINV(P5;L3); LAND(L3,P6;L1); LINV(P4;L2); DLATCH(P1,L2;N3;12,12,12,12,19,5,20,12,12,12,12,19,5,20); DLATCH(P2,L2;N4;12,12,12,12,19,5,20,12,12,12,12,19,5,20); DLATCH(P3,L2;N5;12,12,12,12,19,5,20,12,12,12,12,19,5,20); LINV(N3;L4); LINV(N4;L5); LINV(N5;L6); NAND(L4,L5,L6,L1;P15;26,26,36,36); NAND(N3,L5,L6,L1;P14;26,26,36,36); NAND(L4,N4,L6,L1;P13;26,26,36,36); NAND(N3,N4,L6,L1;P12;26,26,36,36); NAND(L4,L5,N5,L1;P11;26,26,36,36); NAND(N3,L5,N5,L1;P10;26,26,36,36); NAND(L4,N4,N5,L1;P9;26,26,36,36); NAND(N3,N4,N5,L1;P7;26,26,36,36); % ;Delays are modeled for Select to output and Enable to output ;for Low to High going and High to Low going signals. :74HC138 TTL 16 BUF(P1;N1;30,20,35,33); BUF(P2;N2;30,20,35,33); BUF(P3;N3;30,20,35,33); INV(P1;N4;30,20,35,33); INV(P2;N5;30,20,35,33); INV(P3;N6;30,20,35,33); BUF(P6;N7;20,20,33,33); NOR(P4,P5;N8;25,20,39,33); LAND(N7,N8;L1); NAND(N4,N5,N6,L1;P15;5,5,5,5); NAND(N1,N5,N6,L1;P14;5,5,5,5); NAND(N4,N2,N6,L1;P13;5,5,5,5); NAND(N1,N2,N6,L1;P12;5,5,5,5); NAND(N4,N5,N3,L1;P11;5,5,5,5); NAND(N1,N5,N3,L1;P10;5,5,5,5); NAND(N4,N2,N3,L1;P9;5,5,5,5); NAND(N1,N2,N3,L1;P7;5,5,5,5); % ;Delays are modeled for Select to output and Enable to output ;for Low to High going and High to Low going signals. :74HC138A TTL 16 BUF(P1;N1;30,20,35,33); BUF(P2;N2;30,20,35,33); BUF(P3;N3;30,20,35,33); INV(P1;N4;30,20,35,33); INV(P2;N5;30,20,35,33); INV(P3;N6;30,20,35,33); BUF(P6;N7;20,20,33,33); NOR(P4,P5;N8;25,20,39,33); LAND(N7,N8;L1); NAND(N4,N5,N6,L1;P15;5,5,5,5); NAND(N1,N5,N6,L1;P14;5,5,5,5); NAND(N4,N2,N6,L1;P13;5,5,5,5); NAND(N1,N2,N6,L1;P12;5,5,5,5); NAND(N4,N5,N3,L1;P11;5,5,5,5); NAND(N1,N5,N3,L1;P10;5,5,5,5); NAND(N4,N2,N3,L1;P9;5,5,5,5); NAND(N1,N2,N3,L1;P7;5,5,5,5); % ;Delays are modeled for Select to Output for Low to High ;and High to Low going signals. :74HC139 TTL 16 INV(P1;N1;25,25,39,39); BUF(P2;N2;33,33,39,39); BUF(P3;N3;33,33,39,39); INV(P2;N4;25,25,39,39); INV(P3;N5;25,25,39,39); INV(P15;N6;25,25,39,39); BUF(P14;N7;33,33,39,39); BUF(P13;N8;33,33,39,39); INV(P14;N9;25,25,39,39); INV(P13;N10;25,25,39,39); NAND(N4,N5,N1;P4;5,5,5,5); NAND(N2,N5,N1;P5;5,5,5,5); NAND(N4,N3,N1;P6;5,5,5,5); NAND(N2,N3,N1;P7;5,5,5,5); NAND(N9,N10,N6;P12;5,5,5,5); NAND(N10,N7,N6;P11;5,5,5,5); NAND(N9,N8,N6;P10;5,5,5,5); NAND(N7,N8,N6;P9;5,5,5,5); % ;Delays are modeled for Select to Output for Low to High ;and High to Low going signals. :74HC139A TTL 16 INV(P1;N1;25,25,39,39); BUF(P2;N2;33,33,39,39); BUF(P3;N3;33,33,39,39); INV(P2;N4;25,25,39,39); INV(P3;N5;25,25,39,39); INV(P15;N6;25,25,39,39); BUF(P14;N7;33,33,39,39); BUF(P13;N8;33,33,39,39); INV(P14;N9;25,25,39,39); INV(P13;N10;25,25,39,39); NAND(N4,N5,N1;P4;5,5,5,5); NAND(N2,N5,N1;P5;5,5,5,5); NAND(N4,N3,N1;P6;5,5,5,5); NAND(N2,N3,N1;P7;5,5,5,5); NAND(N9,N10,N6;P12;5,5,5,5); NAND(N10,N7,N6;P11;5,5,5,5); NAND(N9,N8,N6;P10;5,5,5,5); NAND(N7,N8,N6;P9;5,5,5,5); % :74HC147 TTL 16 LINV(P11;L1); LINV(P12;L2); LINV(P13;L3); LINV(P1;L4); LINV(P2;L5); LINV(P3;L6); LINV(P4;L7); LAND(P5,P10;L8); LINV(P10;L9); LNAND(L1,P12,P1,P3,L8;L10); LNAND(P1,P3,L3,L8;L11); LNAND(P3,L5,L8;L12); LNAND(L7,L8;L13); LNAND(L2,P2,P1,L8;L14); LNAND(L3,P1,P2,L8;L15); LNAND(L6,L8;L16); LNAND(L4,L8;L17); LNAND(L5,L8;L18); BUF(L8;P14;38,38,55,55); AND(L17,L18,L16,L13;P6;38,38,55,55); AND(L14,L15,L16,L13;P7;38,38,55,55); AND(L10,L11,L12,L13,P10;P9;38,38,55,55); % :74HC148 TTL 16 INV(P11;N1;5,5,5,5); INV(P12;N2;5,5,5,5); INV(P13;N3;5,5,5,5); INV(P1;N4;5,5,5,5); INV(P2;N5;5,5,5,5); INV(P3;N6;5,5,5,5); INV(P4;N7;5,5,5,5); BUF(P11;N8;14,14,14,14); BUF(P12;N9;14,14,14,14); BUF(P13;N10;14,14,14,14); BUF(P1;N11;14,14,14,14); BUF(P2;N12;14,14,14,14); BUF(P3;N13;14,14,14,14); BUF(P4;N14;14,14,14,14); BUF(P10;N15;14,14,14,14); INV(P5;N18;9,9,9,9); LINV(P5;L1); LINV(N2;L2); LINV(N4;L3); LINV(N5;L4); LINV(N6;L5); LAND(N1,L2,L3,L5,N18;L6); LAND(N3,L3,L5,N18;L7); LAND(N5,L5,N18;L8); LAND(N7,N18;L9); LAND(N2,L3,L4,N18;L10); LAND(N3,L3,L4,N18;L11); LAND(N6,N18;L12); LAND(N7,N18;L13); LAND(N4,N18;L14); LAND(N5,N18;L15); LAND(N6,N18;L16); LAND(N7,N18;L17); BUF(L1;N16;2,2,2,2); BUF(L1;N17;17,17,17,17); NAND(N8,N9,N10,N11,N12,N13,N14,N15,N16;P15;14,14,24,24); NAND(P15,N17;P14;24,24,34,34); NOR(L6,L7,L8,L9;P9;30,30,40,40); NOR(L10,L11,L12,L13;P7;30,30,40,40); NOR(L14,L15,L16,L17;P6;30,30,40,40); % :74HC151 TTL 16 INV(P11;N1;6,6,2,2); INV(P10;N2;6,6,2,2); INV(P9;N3;6,6,2,2); INV(P7;N4;2,2,3,3); LINV(N1;L1); LINV(N2;L2); LINV(N3;L3); AND(P4,N1,N2,N3;N5;8,8,17,17); AND(P3,L1,N2,N3;N6;8,8,17,17); AND(P2,N1,L2,N3;N7;8,8,17,17); AND(P1,L1,L2,N3;N8;8,8,17,17); AND(P15,L3,N1,N2;N9;8,8,17,17); AND(P14,L3,L1,N2;N10;8,8,17,17); AND(P13,L3,N1,L2;N11;8,8,17,17); AND(P12,L3,L1,L2;N12;8,8,17,17); LOR(N5,N6,N7,N8,N9,N10,N11,N12;L4); LINV(L4;L5); AND(L4,N4;P5;21,21,32,32); OR(L5,P7;P6;21,21,32,32); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50 and 150pF :74HC152 TTL 14 INV(P10;N1;10,10,10,10); INV(P9;N2;10,10,10,10); INV(P8;N3;10,10,10,10); LINV(N1;L1); LINV(N2;L2); LINV(N3;L3); LAND(P5,N1,N2,N3;L4); LAND(P4,L1,N2,N3;L5); LAND(P3,N1,L2,N3;L6); LAND(P2,L1,L2,N3;L7); LAND(P1,N1,N2,L3;L8); LAND(P13,L1,N2,L3;L9); LAND(P12,N1,L2,L3;L10); LAND(P11,L1,L2,L3;L11); NOR(L4,L5,L6,L7,L8,L9,L10,L11;P6;33,33,54,54); % :74HC153 TTL 16 LINV(P1;L1); LINV(P15;L2); INV(P14;N1;7,7,9,9); INV(P2;N2;7,7,9,9); BUF(P14;N3;7,7,9,9); BUF(P2;N4;7,7,9,9); LNAND(P3,N3,N4;L3); LNAND(P4,N1,N4;L4); LNAND(P5,N3,N2;L5); LNAND(P6,N1,N2;L6); LNAND(P13,N3,N4;L7); LNAND(P12,N1,N4;L8); LNAND(P11,N3,N2;L9); LNAND(P10,N1,N2;L10); NAND(L3,L4,L5,L6;N5;8,8,11,11); NAND(L7,L8,L9,L10;N6;8,8,11,11); AND(L1,N5;P7;15,15,24,24); AND(L2,N6;P9;15,15,24,24); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC154 TTL 24 INV(P23;N1;5,5,5,5); INV(P22;N2;5,5,5,5); INV(P21;N3;5,5,5,5); INV(P20;N4;5,5,5,5); LINV(N1;L1); LINV(N2;L2); LINV(N3;L3); LINV(N4;L4); NOR(P18,P19;N5;5,5,5,5); NAND(N5,N1,N2,N3,N4;P1;30,30,40,40); NAND(N5,L1,N2,N3,N4;P2;30,30,40,40); NAND(N5,N1,L2,N3,N4;P3;30,30,40,40); NAND(N5,L1,L2,N3,N4;P4;30,30,40,40); NAND(N5,N1,N2,L3,N4;P5;30,30,40,40); NAND(N5,L1,N2,L3,N4;P6;30,30,40,40); NAND(N5,N1,L2,L3,N4;P7;30,30,40,40); NAND(N5,L1,L2,L3,N4;P8;30,30,40,40); NAND(N5,N1,N2,N3,L4;P9;30,30,40,40); NAND(N5,L1,N2,N3,L4;P10;30,30,40,40); NAND(N5,N1,L2,N3,L4;P11;30,30,40,40); NAND(N5,L1,L2,N3,L4;P13;30,30,40,40); NAND(N5,N1,N2,L3,L4;P14;30,30,40,40); NAND(N5,L1,N2,L3,L4;P15;30,30,40,40); NAND(N5,N1,L2,L3,L4;P16;30,30,40,40); NAND(N5,L1,L2,L3,L4;P17;30,30,40,40); % ;Delays are modeled for Data to Output, Strobe to Output, and Select to ;Output for Low to High and High to Low going signals. :74HC157 TTL 16 LINV(P15;L1); LINV(P1;L2); LAND(L1,L2;L3); LAND(L1,P1;L4); LAND(P2,L3;L5); LAND(P3,L4;L6); LAND(P5,L3;L7); LAND(P6,L4;L8); LAND(P11,L3;L9); LAND(P10,L4;L10); LAND(P14,L3;L11); LAND(P13,L4;L12); OR(L5,L6;P4;19,19,31,31); OR(L7,L8;P7;19,19,31,31); OR(L9,L10;P9;19,19,31,31); OR(L11,L12;P12;19,19,31,31); % ;Delays are modeled for Data to Output, Strobe to Output, and Select to ;Output for Low to High and High to Low going signals. :74HC157A TTL 16 LINV(P15;L1); LINV(P1;L2); LAND(L1,L2;L3); LAND(L1,P1;L4); LAND(P2,L3;L5); LAND(P3,L4;L6); LAND(P5,L3;L7); LAND(P6,L4;L8); LAND(P11,L3;L9); LAND(P10,L4;L10); LAND(P14,L3;L11); LAND(P13,L4;L12); OR(L5,L6;P4;19,19,31,31); OR(L7,L8;P7;19,19,31,31); OR(L9,L10;P9;19,19,31,31); OR(L11,L12;P12;19,19,31,31); % ;Delays are modeled for Data to Output, Strobe to Output, and Select to ;Output for Low to High and High to Low going signals. :74HC158 TTL 16 LINV(P15;L1); LINV(P1;L2); LAND(L1,L2;L3); LAND(L1,P1;L4); LAND(P2,L3;L5); LAND(P3,L4;L6); LAND(P5,L3;L7); LAND(P6,L4;L8); LAND(P11,L3;L9); LAND(P10,L4;L10); LAND(P14,L3;L11); LAND(P13,L4;L12); NOR(L5,L6;P4;19,19,31,31); NOR(L7,L8;P7;19,19,31,31); NOR(L9,L10;P9;19,19,31,31); NOR(L11,L12;P12;19,19,31,31); % ;Delays are modeled for Data to Output, Strobe to Output, and Select to ;Output for Low to High and High to Low going signals. :74HC158A TTL 16 LINV(P15;L1); LINV(P1;L2); LAND(L1,L2;L3); LAND(L1,P1;L4); LAND(P2,L3;L5); LAND(P3,L4;L6); LAND(P5,L3;L7); LAND(P6,L4;L8); LAND(P11,L3;L9); LAND(P10,L4;L10); LAND(P14,L3;L11); LAND(P13,L4;L12); NOR(L5,L6;P4;19,19,31,31); NOR(L7,L8;P7;19,19,31,31); NOR(L9,L10;P9;19,19,31,31); NOR(L11,L12;P12;19,19,31,31); % :74HC160 TTL 16 INV(P9;N7;0,0,0,0); LINV(N7;L1); AND(P10,P7;N1;0,0,0,0); AND(N3,N6;N2;0,0,0,0); AND(P10,N2;P15;32,32,40,49); LAND(N3,N4;L2); LAND(N3,N4,N5;L3); LAND(N3,N1;L4); LAND(L2,N1;L5); LAND(N3,N6;L6); LNAND(L6,N1;L7); LAND(L3,N1;L8); LXOR(N1,N3;L9); LXOR(L4,N4;L10); LXOR(L5,N5;L11); LXOR(L8,N6;L12); LAND(P3,N7;L13); LAND(L1,L9;L14); LAND(P4,N7;L15); LAND(L1,L7,L10;L16); LAND(P5,N7;L17); LAND(L1,L11;L18); LAND(P6,N7;L19); LAND(L1,L7,L12;L20); LOR(L13,L14;L21); LOR(L15,L16;L22); LOR(L17,L18;L23); LOR(L19,L20;L24); DQFFC(L21,P2,P1;N3;3,3,30,5,16,16,7,7,16,20,4,5,38,13,20,28,8,8,20,32); DQFFC(L22,P2,P1;N4;3,3,30,5,16,16,7,7,16,20,4,5,38,13,20,28,8,8,20,32); DQFFC(L23,P2,P1;N5;3,3,30,5,16,16,7,7,16,20,4,5,38,13,20,28,8,8,20,32); DQFFC(L24,P2,P1;N6;3,3,30,5,16,16,7,7,16,20,4,5,38,13,20,28,8,8,20,32); BUF(N3;P14;31,31,39,47); BUF(N4;P13;31,31,39,47); BUF(N5;P12;31,31,39,47); BUF(N6;P11;31,31,39,47); % :74HC161 TTL 16 AND(P7,P9,P10;N1;0,0,0,0); AND(N3,N4,N5,N6;N2;0,0,0,0); AND(P10,N2;P15;32,32,40,49); LINV(P9;L1); LAND(P9,N3;L2); LXOR(L2,N1;L3); LAND(L1,P3;L4); LOR(L3,L4;L5); LAND(P9,N4;L6); LAND(N1,N3;L7); LXOR(L6,L7;L8); LAND(L1,P4;L9) LOR(L8,L9;L10); LAND(P9,N5;L11); LAND(N1,N3,N4;L12); LXOR(L11,L12;L13); LAND(L1,P5;L14); LOR(L13,L14;L15); LAND(P9,N6;L16); LAND(N1,N3,N4,N5;L17); LXOR(L16,L17;L18); LAND(L1,P6;L19); LOR(L18,L19;L20); DQFFC(L5,P2,P1;N3;3,3,30,5,16,16,7,7,16,20,4,5,38,13,20,28,18,18,20,32); DQFFC(L10,P2,P1;N4;3,3,30,5,16,16,7,7,16,20,4,5,38,13,20,28,18,18,20,32); DQFFC(L15,P2,P1;N5;3,3,30,5,16,16,7,7,16,20,4,5,38,13,20,28,18,18,20,32); DQFFC(L20,P2,P1;N6;3,3,30,5,16,16,7,7,16,20,4,5,38,13,20,28,18,18,20,32); BUF(N3;P14;32,32,40,49); BUF(N4;P13;32,32,40,49); BUF(N5;P12;32,32,40,49); BUF(N6;P11;32,32,40,49); % :74HC162 TTL 16 LINV(P1;L1); LNOR(L1,P9;L2); LNOR(L1,L2;L3); AND(P10,P7;N1;0,0,0,0); AND(N3,N6;N2;0,0,0,0); AND(P10,N2;P15;32,32,40,49); LAND(N3,N4;L4); LAND(N3,N4,N5;L5); LAND(N3,N1;L6); LAND(L4,N1;L7); LAND(N3,N6;L8); LNAND(L8,N1;L9); LAND(L5,N1;L10); LXOR(N1,N3;L11); LXOR(L6,N4;L12); LXOR(L7,N5;L13); LXOR(L10,N6;L14); LAND(P3,L2;L15); LAND(L3,L11;L16); LAND(P4,L2;L17); LAND(L3,L9,L12;L18); LAND(P5,L2;L19); LAND(L3,L13;L20); LAND(P6,L2;L21); LAND(L3,L9,L14;L22); LOR(L15,L16;L23); LOR(L17,L18;L24); LOR(L19,L20;L25); LOR(L21,L22;L26); DQFF(L23,P2;N3;3,3,30,5,16,16,4,5,38,13,20,28); DQFF(L24,P2;N4;3,3,30,5,16,16,4,5,38,13,20,28); DQFF(L25,P2;N5;3,3,30,5,16,16,4,5,38,13,20,28); DQFF(L26,P2;N6;3,3,30,5,16,16,4,5,38,13,20,28); BUF(N3;P14;31,31,39,47); BUF(N4;P13;31,31,39,47); BUF(N5;P12;31,31,39,47); BUF(N6;P11;31,31,39,47); % :74HC163 TTL 16 NAND(P7,P9,P10;N1;0,0,0,0); INV(P9;N2;0,0,0,0); INV(P1;N3;0,0,0,0); LNOR(N1,N3;L1); LNOR(P9,N3;L2); LNOR(N2,N3;L3); AND(N5,N6,N7,N8;N4;0,0,0,0); AND(P10,N4;P15;32,32,40,49); LAND(L3,N5;L4); LXOR(L4,L1;L5); LAND(L2,P3;L6); LOR(L5,L6;L7); LAND(L3,N6;L8); LAND(L1,N5;L9); LXOR(L8,L9;L10); LAND(L2,P4;L11) LOR(L10,L11;L12); LAND(L3,N7;L13); LAND(L1,N5,N6;L14); LXOR(L13,L14;L15); LAND(L2,P5;L16); LOR(L15,L16;L17); LAND(L3,N8;L18); LAND(L1,N5,N6,N7;L19); LXOR(L18,L19;L20); LAND(L2,P6;L21); LOR(L20,L21;L22); DQFF(L7,P2;N5;3,3,30,5,16,16,4,5,38,13,20,28); DQFF(L12,P2;N6;3,3,30,5,16,16,4,5,38,13,20,28); DQFF(L17,P2;N7;3,3,30,5,16,16,4,5,38,13,20,28); DQFF(L22,P2;N8;3,3,30,5,16,16,4,5,38,13,20,28); BUF(N5;P14;31,31,39,47); BUF(N6;P13;31,31,39,47); BUF(N7;P12;31,31,39,47); BUF(N8;P11;31,31,39,47); % ;taken from 1984 National Logic Data book. :74HC164 TTL 14 LAND(P1,P2;L1); DQFFC(L1,P8,P9;N1;10,10,20,5,16,16,15,15,16,0,15,15,25,5,20,20,22,22,20,0); DQFFC(N1,P8,P9;N2;10,10,20,5,16,16,15,15,16,0,15,15,25,5,20,20,22,22,20,0); DQFFC(N2,P8,P9;N3;10,10,20,5,16,16,15,15,16,0,15,15,25,5,20,20,22,22,20,0); DQFFC(N3,P8,P9;N4;10,10,20,5,16,16,15,15,16,0,15,15,25,5,20,20,22,22,20,0); DQFFC(N4,P8,P9;N5;10,10,20,5,16,16,15,15,16,0,15,15,25,5,20,20,22,22,20,0); DQFFC(N5,P8,P9;N6;10,10,20,5,16,16,15,15,16,0,15,15,25,5,20,20,22,22,20,0); DQFFC(N6,P8,P9;N7;10,10,20,5,16,16,15,15,16,0,15,15,25,5,20,20,22,22,20,0); DQFFC(N7,P8,P9;N8;10,10,20,5,16,16,15,15,16,0,15,15,25,5,20,20,22,22,20,0); BUF(N1;P3;20,20,29,29); BUF(N2;P4;20,20,29,29); BUF(N3;P5;20,20,29,29); BUF(N4;P6;20,20,29,29); BUF(N5;P10;20,20,29,29); BUF(N6;P11;20,20,29,29); BUF(N7;P12;20,20,29,29); BUF(N8;P13;20,20,29,29); % :74HC165 TTL 16 INV(P1;N1;0,0,0,0); BUF(P10;N2;0,0,0,0); LAND(P2,P1;L1); AND(P1,P15;N3;0,0,0,0); OR(L1,N3;N4;0,0,0,0); LNAND(N1,P11;L2); LNAND(N1,P12;L3); LNAND(N1,P13;L4); LNAND(N1,P14;L5); LNAND(N1,P3;L6); LNAND(N1,P4;L7); LNAND(N1,P5;L8); LNAND(N1,P6;L9); LNAND(N1,L2;L10); LNAND(N1,L3;L11); LNAND(N1,L4;L12); LNAND(N1,L5;L13); LNAND(N1,L6;L14); LNAND(N1,L7;L15); LNAND(N1,L8;L16); LNAND(N1,L9;L17); DQFFPC(N2,N4,L2,L10;N5;25,25,20,0,16,16,25,25,16,0,38,38,25,0,20,30,44,44,20,0); DQFFPC(N5,N4,L3,L11;N6;25,25,5,0,16,16,25,25,16,0,38,38,5,0,20,30,44,44,20,0); DQFFPC(N6,N4,L4,L12;N7;25,25,5,0,16,16,25,25,16,0,38,38,5,0,20,30,44,44,20,0); DQFFPC(N7,N4,L5,L13;N8;25,25,5,0,16,16,25,25,16,0,38,38,5,0,20,30,44,44,20,0); DQFFPC(N8,N4,L6,L14;N9;25,25,5,0,16,16,25,25,16,0,38,38,5,0,20,30,44,44,20,0); DQFFPC(N9,N4,L7,L15;N10;25,25,5,0,16,16,25,25,16,0,38,38,5,0,20,30,44,44,20,0); DQFFPC(N10,N4,L8,L16;N11;25,25,5,0,16,16,25,25,16,0,38,38,5,0,20,30,44,44,20,0); DFFPC(N11,N4,L9,L17;N12,N13;25,25,5,0,16,16,25,25,16,0,38,38,5,0,20,30,44,44,20,0); BUF(N12;P9;0,0,0,0); BUF(N13;P7;0,0,0,0); % ;Clear to Output delay for 15pF was estimated. :74HC166 TTL 16 BUF(P15;N1;0,0,0,0); INV(P15;N2;0,0,0,0); BUF(P6;N3;0,0,0,0); OR(P7,N3;N4;0,0,0,0); LAND(P1,N1;L1); LAND(N2,P2;L2); LOR(L1,L2;L3); LAND(N5,N1;L4); LAND(N2,P3;L5); LOR(L4,L5;L6); LAND(N6,N1;L7); LAND(N2,P4;L8); LOR(L7,L8;L9); LAND(N7,N1;L10); LAND(N2,P5;L11); LOR(L10,L11;L12); LAND(N8,N1;L13); LAND(N2,P10;L14); LOR(L13,L14;L15); LAND(N9,N1;L16); LAND(N2,P11;L17); LOR(L16,L17;L18); LAND(N10,N1;L19); LAND(N2,P12;L20); LOR(L19,L20;L21); LAND(N11,N1;L22); LAND(N2,P14;L23); LOR(L22,L23;L24); DQFFC(L3,N4,P9;N5;25,25,20,0,16,16,29,29,16,0,38,38,25,0,20,30,44,44,20,0); DQFFC(L6,N4,P9;N6;25,25,20,0,16,16,29,29,16,0,38,38,25,0,20,30,44,44,20,0); DQFFC(L9,N4,P9;N7;25,25,20,0,16,16,29,29,16,0,38,38,25,0,20,30,44,44,20,0); DQFFC(L12,N4,P9;N8;25,25,20,0,16,16,29,29,16,0,38,38,25,0,20,30,44,44,20,0); DQFFC(L15,N4,P9;N9;25,25,20,0,16,16,29,29,16,0,38,38,25,0,20,30,44,44,20,0); DQFFC(L18,N4,P9;N10;25,25,20,0,16,16,29,29,16,0,38,38,25,0,20,30,44,44,20,0); DQFFC(L21,N4,P9;N11;25,25,20,0,16,16,29,29,16,0,38,38,25,0,20,30,44,44,20,0); DQFFC(L24,N4,P9;P13;25,25,20,0,16,16,29,29,16,0,38,38,25,0,20,30,44,44,20,0); % ;taken from 1984 National Logic Data Book. ;Delays are given for 50 and 150pF. :74HC173 TTL 16 LNOR(P9,P10;L16); LNOR(P1,P2;L1); LINV(P15;L2); LINV(L16;L3); LAND(N1,L3;L4); LAND(P14,L16;L5); LOR(L4,L5;L6); LAND(N2,L3;L7); LAND(P13,L16;L8); LOR(L7,L8;L9); LAND(N3,L3;L10); LAND(P12,L16;L11); LOR(L10,L11;L12); LAND(N4,L3;L13); LAND(P11,L16;L14); LOR(L13,L14;L15); DQFFC(L6,P7,L2;N1;16,16,25,0,20,20,10,10,20,23,16,16,25,0,20,20,10,10,20,23); DQFFC(L9,P7,L2;N2;16,16,25,0,20,20,10,10,20,23,16,16,25,0,20,20,10,10,20,23); DQFFC(L12,P7,L2;N3;16,16,25,0,20,20,10,10,20,23,16,16,25,0,20,20,10,10,20,23); DQFFC(L15,P7,L2;N4;16,16,25,0,20,20,10,10,20,23,16,16,25,0,20,20,10,10,20,23); BUF(N1;N5;28,28,40,40); BUF(N2;N6;28,28,40,40); BUF(N3;N7;28,28,40,40); BUF(N4;N8;28,28,40,40); TSB(N5,L1;P3;38,38,38,38,50,50,50,50); TSB(N6,L1;P4;38,38,38,38,50,50,50,50); TSB(N7,L1;P5;38,38,38,38,50,50,50,50); TSB(N8,L1;P6;38,38,38,38,50,50,50,50); % :74HC174 TTL 16 DQFFC(P3,P9,P1;P2;30,30,20,5,16,17,30,30,16,5,41,41,25,5,20,28,41,41,20,5); DQFFC(P4,P9,P1;P5;30,30,20,5,16,17,30,30,16,5,41,41,25,5,20,28,41,41,20,5); DQFFC(P6,P9,P1;P7;30,30,20,5,16,17,30,30,16,5,41,41,25,5,20,28,41,41,20,5); DQFFC(P11,P9,P1;P10;30,30,20,5,16,17,30,30,16,5,41,41,25,5,20,28,41,41,20,5); DQFFC(P13,P9,P1;P12;30,30,20,5,16,17,30,30,16,5,41,41,25,5,20,28,41,41,20,5); DQFFC(P14,P9,P1;P15;30,30,20,5,16,17,30,30,16,5,41,41,25,5,20,28,41,41,20,5); % :74HC175 TTL 16 DFFC(P4,P9,P1;P2,P3;25,25,20,0,16,13,21,21,16,20,38,38,25,0,20,22,32,32,20,25); DFFC(P5,P9,P1;P7,P6;25,25,20,0,16,13,21,21,16,20,38,38,25,0,20,22,32,32,20,25); DFFC(P12,P9,P1;P10,P11;25,25,20,0,16,13,21,21,16,20,38,38,25,0,20,22,32,32,20,25); DFFC(P13,P9,P1;P15,P14;25,25,20,0,16,13,21,21,16,20,38,38,25,0,20,22,32,32,20,25); % ;taken from 1988 TI High-Speed CMOS Logic data book. :74HC180 TTL 14 LXNOR(P8,P9,P10,P11,P12,P13,P1,P2;L1); LINV(L1;L2); LAND(L1,P4;L3); LAND(L2,P3;L4); LAND(P3,L1;L5); LAND(L2,P4;L6); NOR(L3,L4;P5;18,18,28,28); NOR(L5,L6;P6;18,18,28,28); % ;taken from 1984 National Logic Data book. :74HC181 TTL 24 LINV(P18;L1); LINV(P20;L2); LINV(P22;L3); LINV(P1;L4); LINV(P8;L5); LAND(P18,P3,P19;L6); LAND(P19,P4,L1;L7); LAND(L1,P5;L8); LAND(P6,P18;L9); LAND(P20,P3,P21;L10); LAND(P21,P4,L2;L11); LAND(L2,P5;L12); LAND(P6,P20;L13); LAND(P22,P3,P23;L14); LAND(P23,P4,L3;L15); LAND(L3,P5;L16); LAND(P6,P22;L17); LAND(P1,P3,P2;L18); LAND(P2,P4,L4;L19); LAND(L4,P5;L20); LAND(P6,P1;L21); LNOR(L6,L7;L22); LNOR(L8,L9,P19;L23); LNOR(L10,L11;L24); LNOR(L12,L13,P21;L25); LNOR(L14,L15;L26); LNOR(L16,L17,P23;L27); LNOR(L18,L19;L28); LNOR(L20,L21,P2;L29); XOR(L22,L23;N1;7,7,10,10); XOR(L24,L25;N2;7,7,10,10); XOR(L26,L27;N3;7,7,10,10); XOR(L28,L29;N4;7,7,10,10); BUF(P7;N5;5,5,12,12); LAND(L22,L25;L44); LAND(L22,L24,L27;L45); LAND(L22,L24,L26,L29;L46); LNAND(L22,L24,L26,L28,N5;L30); LAND(P7,L28,L26,L24,L5;L31); LAND(L26,L24,L29,L5;L32); LAND(L24,L27,L5;L33); LAND(L25,L5;L34); LAND(P7,L28,L26,L5;L35); LAND(L26,L29,L5;L36); LAND(L27,L5;L37); LAND(P7,L28,L5;L38); LAND(L29,L5;L39); LNAND(P7,L5;L40); LNOR(L31,L32,L33,L34;L41); LNOR(L35,L36,L37;L42); LNOR(L38,L39;L43); NOR(L23,L44,L45,L46;P17;30,30,44,44); NAND(P17,L30;P16;15,15,19,19); NAND(L22,L24,L26,L28;P15;41,41,55,55); XOR(N1,L41;N6;10,10,10,10); XOR(N2,L42;N7;10,10,10,10); XOR(N3,L43;N8;10,10,10,10); XOR(N4,L40;N9;10,10,10,10); BUF(N6;P13;20,20,30,30); BUF(N7;P11;20,20,30,30); BUF(N8;P10;20,20,30,30); BUF(N9;P9;20,20,30,30); BUF(N6;N10;7,7,10,10); BUF(N7;N11;7,7,10,10); BUF(N8;N12;7,7,10,10); SET(RHIGH); AND(N10,N11,N12,P9;P14;20,20,30,30); % :74HC182 TTL 16 INV(P13;N1;3,3,2,2); BUF(P6;N2;11,11,11,11); BUF(P5;N3;11,11,11,11); BUF(P15;N4;11,11,11,11); BUF(P14;N5;11,11,11,11); BUF(P2;N6;11,11,11,11); BUF(P1;N7;11,11,11,11); BUF(P4;N8;11,11,11,11); BUF(P3;N9;11,11,11,11); LAND(N3,N5,N7,N9;L1); LAND(N6,N3,N5,N7;L2); LAND(N4,N3,N5;L3); LAND(N2,N3;L4); LAND(N5,N7,N9,N1;L5); LAND(N8,N5,N7,N9;L6); LAND(N6,N5,N7;L7); LAND(N4,N5;L8); LAND(N7,N9,N1;L9); LAND(N8,N7,N9;L10); LAND(N6,N7;L11); LAND(N9,N1;L12); LAND(N8,N9;L13); OR(P6,P15,P2,P4;P7;24,24,35,35); OR(L1,L2,L3,L4;P10;24,24,35,35); NOR(L5,L6,L7,L8;P9;24,24,35,35); NOR(L9,L10,L11;P11;24,24,35,35); NOR(L12,L13;P12;24,24,35,35); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC190 TTL 16 LINV(P5;L1); LNOR(P5,P4;L2); LNOR(P4,L1;L3); LAND(L1,N4,N10;L4); LAND(P5,N5,N7,N9,N11;L5); LNAND(P15,N3;L6); LNAND(L6,N3;L7); LNAND(P1,N3;L8); LNAND(N7,N9,N11;L9); LNAND(L8,N3;L10); LNAND(P10,N3;L11); LNAND(L11,N3;L12); LNAND(P9,N3;L13); LNAND(L13,N3;L14); LAND(L3,N5,L9;L15); LAND(N4,N11,L2;L16); LAND(L9,L3,N5,N7;L17); LAND(N4,N6,L2;L18); LAND(L3,N5,N7,N9;L19); LAND(N4,N10,L2;L20); LAND(N4,N6,N8,L2;L21); LINV(P4;L22); LOR(L15,L16;L23); LOR(L17,L18;L24); LOR(L19,L20,L21;L25); INV(P14;N1;2,2,12,12); INV(P4;N2;5,5,15,15); INV(P11;N3;6,6,6,6); JKFFPC(L22,L22,P14,L6,L7;N4,N5;15,15,38,5,30,30,27,27,30,38,15,15,38,5,30,30,27,27,30,38); JKFFPC(L23,L23,P14,L8,L10;N6,N7;15,15,38,5,30,30,27,27,30,38,15,15,38,5,30,30,27,27,30,38); JKFFPC(L24,L24,P14,L11,L12;N8,N9;15,15,38,5,30,30,27,27,30,38,15,15,38,5,30,30,27,27,30,38); JKFFPC(L25,L25,P14,L13,L14;N10,N11;15,15,38,5,30,30,27,27,30,38,15,15,38,5,30,30,27,27,30,38); OR(L4,L5;N12;20,20,30,30); BUF(N12;P12;18,18,18,18); NAND(N1,N2,N12;P13;18,18,18,18); BUF(N4;P3;23,23,33,33); BUF(N6;P2;23,23,33,33); BUF(N8;P6;23,23,33,33); BUF(N10;P7;23,23,33,33); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC191 TTL 16 LINV(P5;L1); LNOR(P5,P4;L2); LNOR(P4,L1;L3); LAND(L1,N4,N6,N8,N10;L4); LAND(P5,N5,N7,N9,N11;L5); LNAND(P15,N3;L6); LNAND(L6,N3;L7); LNAND(P1,N3;L8); LNAND(L8,N3;L9); LNAND(P10,N3;L10); LNAND(L10,N3;L11); LNAND(P9,N3;L12); LNAND(L12,N3;L13); LAND(L3,N5;L14); LAND(N4,L2;L15); LAND(L3,N5,N7;L16); LAND(N4,N6,L2;L17); LAND(L3,N5,N7,N9;L18); LAND(N4,N6,N8,L2;L19); LINV(P4;L20); LOR(L14,L15;L21); LOR(L16,L17;L22); LOR(L18,L19;L23); INV(P14;N1;2,2,12,12); INV(P4;N2;5,5,15,15); INV(P11;N3;6,6,6,6); JKFFPC(L20,L20,P14,L6,L7;N4,N5;15,15,38,5,30,30,27,27,30,38,15,15,38,5,30,30,27,27,30,38); JKFFPC(L21,L21,P14,L8,L9;N6,N7;15,15,38,5,30,30,27,27,30,38,15,15,38,5,30,30,27,27,30,38); JKFFPC(L22,L22,P14,L10,L11;N8,N9;15,15,38,5,30,30,27,27,30,38,15,15,38,5,30,30,27,27,30,38); JKFFPC(L23,L23,P14,L12,L13;N10,N11;15,15,38,5,30,30,27,27,30,38,15,15,38,5,30,30,27,27,30,38); OR(L4,L5;N12;20,20,30,30); BUF(N12;P12;18,18,18,18); NAND(N1,N2,N12;P13;18,18,18,18); BUF(N4;P3;23,23,33,33); BUF(N6;P2;23,23,33,33); BUF(N8;P6;23,23,33,33); BUF(N10;P7;23,23,33,33); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC192 TTL 16 LINV(P4;L1); LINV(P5;L2); LNAND(P15,N2,N1;L3); LNAND(P1,N2,N1;L4); LNAND(N10,N12,N14;L5); LNAND(P10,N2,N1;L6); LNAND(P9,N2,N1;L7); LAND(L1,N8,L5;L8); LAND(N7,N14,L2;L9); LAND(L5,L1,N8,N10;L10); LAND(N7,N9,L2;L11); LAND(L1,N8,N10,N12;L12); LAND(N7,N13,L2;L13); LAND(N7,N9,N11,L2;L14); LNAND(L3,N2;L15); LNAND(L4,N2;L16); LNAND(L6,N2;L17); LNAND(L7,N2;L18); LAND(N1,L15;L19); LAND(N1,L16;L20); LAND(N1,L17;L21); LAND(N1,L18;L22); INV(P14;N1;5,5,5,5); INV(P11;N2;10,10,10,10); NOR(L1,L2;N3;0,0,0,0); NOR(L8,L9;N4;0,0,0,0); NOR(L10,L11;N5;0,0,0,0); NOR(L12,L13,L14;N6;0,0,0,0); JKFFPC(ONE,ONE,N3,L3,L19;N7,N8;23,23,28,5,30,30,15,15,30,28,23,23,28,5,30,30,15,15,30,28); JKFFPC(ONE,ONE,N4,L4,L20;N9,N10;23,23,28,5,30,30,15,15,30,28,23,23,28,5,30,30,15,15,30,28); JKFFPC(ONE,ONE,N5,L6,L21;N11,N12;23,23,28,5,30,30,15,15,30,28,23,23,28,5,30,30,15,15,30,28); JKFFPC(ONE,ONE,N6,L7,L22;N13,N14;23,23,28,5,30,30,15,15,30,28,23,23,28,5,30,30,15,15,30,28); NAND(L1,N8,N10,N12,N14;P13;31,31,41,41); NAND(N7,N13,L2;P12;31,31,41,41); BUF(N7;P3;30,30,40,40); BUF(N9;P2;30,30,40,40); BUF(N11;P6;30,30,40,40); BUF(N13;P7;30,30,40,40); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC193 TTL 16 LINV(P4;L1); LINV(P5;L2); LNAND(P15,N2,N1;L3); LNAND(P1,N2,N1;L4); LNAND(P10,N2,N1;L5); LNAND(P9,N2,N1;L6); LAND(L1,N8;L7); LAND(N7,L2;L8); LAND(L1,N8,N10;L9); LAND(N7,N9,L2;L10); LAND(L1,N8,N10,N12;L11); LAND(N7,N9,N11,L2;L12); LNAND(L3,N2;L13); LNAND(L4,N2;L14); LNAND(L5,N2;L15); LNAND(L6,N2;L16); LAND(N1,L13;L17); LAND(N1,L14;L18); LAND(N1,L15;L19); LAND(N1,L16;L20); INV(P14;N1;5,5,5,5); INV(P11;N2;10,10,10,10); NOR(L1,L2;N3;0,0,0,0); NOR(L7,L8;N4;0,0,0,0); NOR(L9,L10;N5;0,0,0,0); NOR(L11,L12;N6;0,0,0,0); JKFFPC(ONE,ONE,N3,L3,L17;N7,N8;23,23,28,5,30,30,15,15,30,28,23,23,28,5,30,30,15,15,30,28); JKFFPC(ONE,ONE,N4,L4,L18;N9,N10;23,23,28,5,30,30,15,15,30,28,23,23,28,5,30,30,15,15,30,28); JKFFPC(ONE,ONE,N5,L5,L19;N11,N12;23,23,28,5,30,30,15,15,30,28,23,23,28,5,30,30,15,15,30,28); JKFFPC(ONE,ONE,N6,L6,L20;N13,N14;23,23,28,5,30,30,15,15,30,28,23,23,28,5,30,30,15,15,30,28); NAND(L1,N8,N10,N12,N14;P13;31,31,41,41); NAND(N7,N9,N11,N13,L2;P12;31,31,41,41); BUF(N7;P3;30,30,40,40); BUF(N9;P2;30,30,40,40); BUF(N11;P6;30,30,40,40); BUF(N13;P7;30,30,40,40); % :74HC194 TTL 16 LINV(P10;L1); LINV(P9;L2); AND(P10,P9;N1;0,0,0,0); AND(P10,L2;N2;0,0,0,0); AND(L1,P9;N3;0,0,0,0); AND(L1,L2;N4;0,0,0,0); LAND(P2,N3;L4); LAND(N2,N6;L5); LAND(N1,P3;L6); LAND(N4,N5;L7); LOR(L4,L5,L6,L7;L8); LAND(N5,N3;L9); LAND(N2,N7;L10); LAND(N1,P4;L11); LAND(N4,N6;L12); LOR(L9,L10,L11,L12;L13); LAND(N6,N3;L14); LAND(N2,N8;L15); LAND(N1,P5;L16); LAND(N4,N7;L17); LOR(L14,L15,L16,L17;L18); LAND(N7,N3;L19); LAND(N2,P7;L20); LAND(N1,P6;L21); LAND(N4,N8;L22); LOR(L19,L20,L21,L22;L23); DQFFC(L8,P11,P1;N5;8,8,20,0,16,16,9,9,16,5,15,15,25,0,20,20,15,15,20,5); DQFFC(L13,P11,P1;N6;8,8,20,0,16,16,9,9,16,5,15,15,25,0,20,20,15,15,20,5); DQFFC(L18,P11,P1;N7;8,8,20,0,16,16,9,9,16,5,15,15,25,0,20,20,15,15,20,5); DQFFC(L23,P11,P1;N8;8,8,20,0,16,16,9,9,16,5,15,15,25,0,20,20,15,15,20,5); BUF(N5;P15;16,16,22,22); BUF(N6;P14;16,16,22,22); BUF(N7;P13;16,16,22,22); BUF(N8;P12;16,16,22,22); % :74HC195 TTL 16 INV(P9;N1;0,0,0,0); BUF(P9;N2;0,0,0,0); LINV(N3;L1); LAND(L1,P2,N2;L2); LAND(N2,P3,N3;L3); LAND(N1,P4;L4); LOR(L2,L3,L4;L5); LAND(N3,N2;L6); LAND(N1,P5;L7); LOR(L6,L7;L8); LAND(N4,N2;L9); LAND(N1,P6;L10); LOR(L9,L10;L11); LAND(N5,N2;L12); LAND(N1,P7;L13); LOR(L12,L13;L14); DQFFC(L5,P10,P1;N3;10,10,20,0,16,16,11,11,16,5,10,10,25,0,20,22,11,11,20,5); DQFFC(L8,P10,P1;N4;10,10,20,0,16,16,11,11,16,5,10,10,25,0,20,22,11,11,20,5); DQFFC(L11,P10,P1;N5;10,10,20,0,16,16,11,11,16,5,10,10,25,0,20,22,11,11,20,5); DQFFC(L14,P10,P1;N6;10,10,20,0,16,16,11,11,16,5,10,10,25,0,20,22,11,11,20,5); BUF(N3;P15;14,14,27,27); BUF(N4;P14;14,14,27,27); BUF(N5;P13;14,14,27,27); BUF(N6;P12;14,14,27,27); INV(N6;P11;14,14,27,27); % ;Propagation delays and Enable/Disable times are modeled. Propagation ;delays are for 50pf and 150pf and the Enable/Disable times are for ;50pf loading. :74HC240 TTL 20 INV(P2;N1;25,25,38,38); INV(P4;N2;25,25,38,38); INV(P6;N3;25,25,38,38); INV(P8;N4;25,25,38,38); INV(P11;N5;25,25,38,38); INV(P13;N6;25,25,38,38); INV(P15;N7;25,25,38,38); INV(P17;N8;25,25,38,38); LINV(P1;L1); LINV(P19;L2); TSB(N1,L1;P18;38,38,38,38,38,38,38,38); TSB(N2,L1;P16;38,38,38,38,38,38,38,38); TSB(N3,L1;P14;38,38,38,38,38,38,38,38); TSB(N4,L1;P12;38,38,38,38,38,38,38,38); TSB(N5,L2;P9;38,38,38,38,38,38,38,38); TSB(N6,L2;P7;38,38,38,38,38,38,38,38); TSB(N7,L2;P5;38,38,38,38,38,38,38,38); TSB(N8,L2;P3;38,38,38,38,38,38,38,38); % ;Propagation delays and Enable/Disable times are modeled. Propagation ;delays are for 50pf and 150pf and the Enable/Disable times are for ;50pf loading. :74HC240A TTL 20 INV(P2;N1;25,25,38,38); INV(P4;N2;25,25,38,38); INV(P6;N3;25,25,38,38); INV(P8;N4;25,25,38,38); INV(P11;N5;25,25,38,38); INV(P13;N6;25,25,38,38); INV(P15;N7;25,25,38,38); INV(P17;N8;25,25,38,38); LINV(P1;L1); LINV(P19;L2); TSB(N1,L1;P18;38,38,38,38,38,38,38,38); TSB(N2,L1;P16;38,38,38,38,38,38,38,38); TSB(N3,L1;P14;38,38,38,38,38,38,38,38); TSB(N4,L1;P12;38,38,38,38,38,38,38,38); TSB(N5,L2;P9;38,38,38,38,38,38,38,38); TSB(N6,L2;P7;38,38,38,38,38,38,38,38); TSB(N7,L2;P5;38,38,38,38,38,38,38,38); TSB(N8,L2;P3;38,38,38,38,38,38,38,38); % ;Propagation delays for 50pf and 150pf are modeled. Also modeled are ;Enable/Disable times for 50pf loading. :74HC241 TTL 20 BUF(P2;N1;29,29,42,42); BUF(P4;N2;29,29,42,42); BUF(P6;N3;29,29,42,42); BUF(P8;N4;29,29,42,42); BUF(P11;N5;29,29,42,42); BUF(P13;N6;29,29,42,42); BUF(P15;N7;29,29,42,42); BUF(P17;N8;29,29,42,42); LINV(P1;L1); TSB(N1,L1;P18;38,38,38,38,38,38,38,38); TSB(N2,L1;P16;38,38,38,38,38,38,38,38); TSB(N3,L1;P14;38,38,38,38,38,38,38,38); TSB(N4,L1;P12;38,38,38,38,38,38,38,38); TSB(N5,P19;P9;38,38,38,38,38,38,38,38); TSB(N6,P19;P7;38,38,38,38,38,38,38,38); TSB(N7,P19;P5;38,38,38,38,38,38,38,38); TSB(N8,P19;P3;38,38,38,38,38,38,38,38); % ;Propagation delays for 50pf and 150pf are modeled. Also modeled are ;Enable/Disable times for 50pf loading. :74HC242 TTL 14 LINV(P1;L1); INV(P3;N1;25,25,38,38); INV(P4;N2;25,25,38,38); INV(P5;N3;25,25,38,38); INV(P6;N4;25,25,38,38); INV(P8;N5;25,25,38,38); INV(P9;N6;25,25,38,38); INV(P10;N7;25,25,38,38); INV(P11;N8;25,25,38,38); TSB(N1,L1;P11;38,38,38,38,38,38,38,38); TSB(N2,L1;P10;38,38,38,38,38,38,38,38); TSB(N3,L1;P9;38,38,38,38,38,38,38,38); TSB(N4,L1;P8;38,38,38,38,38,38,38,38); TSB(N5,P13;P6;38,38,38,38,38,38,38,38); TSB(N6,P13;P5;38,38,38,38,38,38,38,38); TSB(N7,P13;P4;38,38,38,38,38,38,38,38); TSB(N8,P13;P3;38,38,38,38,38,38,38,38); % ;Propagation delays for 50pf and 150pf are modeled. Also modeled are ;Enable/Disable times for 50pf loading. :74HC243 TTL 14 LINV(P1;L1); BUF(P3;N1;25,25,38,38); BUF(P4;N2;25,25,38,38); BUF(P5;N3;25,25,38,38); BUF(P6;N4;25,25,38,38); BUF(P8;N5;25,25,38,38); BUF(P9;N6;25,25,38,38); BUF(P10;N7;25,25,38,38); BUF(P11;N8;25,25,38,38); TSB(N1,L1;P11;38,38,38,38,38,38,38,38); TSB(N2,L1;P10;38,38,38,38,38,38,38,38); TSB(N3,L1;P9;38,38,38,38,38,38,38,38); TSB(N4,L1;P8;38,38,38,38,38,38,38,38); TSB(N5,P13;P6;38,38,38,38,38,38,38,38); TSB(N6,P13;P5;38,38,38,38,38,38,38,38); TSB(N7,P13;P4;38,38,38,38,38,38,38,38); TSB(N8,P13;P3;38,38,38,38,38,38,38,38); % ;Propagation delays and Enable/Disable times are modeled. Propagation ;delays are for 50pf and 150pf and the Enable/Disable times are for ;50pf loading. :74HC244 TTL 20 BUF(P2;N1;29,29,42,42); BUF(P4;N2;29,29,42,42); BUF(P6;N3;29,29,42,42); BUF(P8;N4;29,29,42,42); BUF(P11;N5;29,29,42,42); BUF(P13;N6;29,29,42,42); BUF(P15;N7;29,29,42,42); BUF(P17;N8;29,29,42,42); LINV(P1;L1); LINV(P19;L2); TSB(N1,L1;P18;38,38,38,38,38,38,38,38); TSB(N2,L1;P16;38,38,38,38,38,38,38,38); TSB(N3,L1;P14;38,38,38,38,38,38,38,38); TSB(N4,L1;P12;38,38,38,38,38,38,38,38); TSB(N5,L2;P9;38,38,38,38,38,38,38,38); TSB(N6,L2;P7;38,38,38,38,38,38,38,38); TSB(N7,L2;P5;38,38,38,38,38,38,38,38); TSB(N8,L2;P3;38,38,38,38,38,38,38,38); % ;Propagation delays and Enable/Disable times are modeled. Propagation ;delays are for 50pf and 150pf and the Enable/Disable times are for ;50pf loading. :74HC244A TTL 20 BUF(P2;N1;29,29,42,42); BUF(P4;N2;29,29,42,42); BUF(P6;N3;29,29,42,42); BUF(P8;N4;29,29,42,42); BUF(P11;N5;29,29,42,42); BUF(P13;N6;29,29,42,42); BUF(P15;N7;29,29,42,42); BUF(P17;N8;29,29,42,42); LINV(P1;L1); LINV(P19;L2); TSB(N1,L1;P18;38,38,38,38,38,38,38,38); TSB(N2,L1;P16;38,38,38,38,38,38,38,38); TSB(N3,L1;P14;38,38,38,38,38,38,38,38); TSB(N4,L1;P12;38,38,38,38,38,38,38,38); TSB(N5,L2;P9;38,38,38,38,38,38,38,38); TSB(N6,L2;P7;38,38,38,38,38,38,38,38); TSB(N7,L2;P5;38,38,38,38,38,38,38,38); TSB(N8,L2;P3;38,38,38,38,38,38,38,38); % ;Propagation delays for 50pf and 150pf are modeled and Enable/Disable ;times for 50pf are modeled. :74HC245 TTL 20 LINV(P19;L1); LINV(P1;L2); LAND(P1,L1;L3); LAND(L1,L2;L4); BUF(P2;N1;22,22,29,29); BUF(P3;N2;22,22,29,29); BUF(P4;N3;22,22,29,29); BUF(P5;N4;22,22,29,29); BUF(P6;N5;22,22,29,29); BUF(P7;N6;22,22,29,29); BUF(P8;N7;22,22,29,29); BUF(P9;N8;22,22,29,29); BUF(P11;N9;22,22,29,29); BUF(P12;N10;22,22,29,29); BUF(P13;N11;22,22,29,29); BUF(P14;N12;22,22,29,29); BUF(P15;N13;22,22,29,29); BUF(P16;N14;22,22,29,29); BUF(P17;N15;22,22,29,29); BUF(P18;N16;22,22,29,29); TSB(N1,L3;P18;56,56,52,52,56,56,52,52); TSB(N2,L3;P17;56,56,52,52,56,56,52,52); TSB(N3,L3;P16;56,56,52,52,56,56,52,52); TSB(N4,L3;P15;56,56,52,52,56,56,52,52); TSB(N5,L3;P14;56,56,52,52,56,56,52,52); TSB(N6,L3;P13;56,56,52,52,56,56,52,52); TSB(N7,L3;P12;56,56,52,52,56,56,52,52); TSB(N8,L3;P11;56,56,52,52,56,56,52,52); TSB(N9,L4;P9;56,56,52,52,56,56,52,52); TSB(N10,L4;P8;56,56,52,52,56,56,52,52); TSB(N11,L4;P7;56,56,52,52,56,56,52,52); TSB(N12,L4;P6;56,56,52,52,56,56,52,52); TSB(N13,L4;P5;56,56,52,52,56,56,52,52); TSB(N14,L4;P4;56,56,52,52,56,56,52,52); TSB(N15,L4;P3;56,56,52,52,56,56,52,52); TSB(N16,L4;P2;56,56,52,52,56,56,52,52); % ;Propagation delays for 50pf and 150pf are modeled and Enable/Disable ;times for 50pf are modeled. :74HC245A TTL 20 LINV(P19;L1); LINV(P1;L2); LAND(P1,L1;L3); LAND(L1,L2;L4); BUF(P2;N1;22,22,29,29); BUF(P3;N2;22,22,29,29); BUF(P4;N3;22,22,29,29); BUF(P5;N4;22,22,29,29); BUF(P6;N5;22,22,29,29); BUF(P7;N6;22,22,29,29); BUF(P8;N7;22,22,29,29); BUF(P9;N8;22,22,29,29); BUF(P11;N9;22,22,29,29); BUF(P12;N10;22,22,29,29); BUF(P13;N11;22,22,29,29); BUF(P14;N12;22,22,29,29); BUF(P15;N13;22,22,29,29); BUF(P16;N14;22,22,29,29); BUF(P17;N15;22,22,29,29); BUF(P18;N16;22,22,29,29); TSB(N1,L3;P18;56,56,52,52,56,56,52,52); TSB(N2,L3;P17;56,56,52,52,56,56,52,52); TSB(N3,L3;P16;56,56,52,52,56,56,52,52); TSB(N4,L3;P15;56,56,52,52,56,56,52,52); TSB(N5,L3;P14;56,56,52,52,56,56,52,52); TSB(N6,L3;P13;56,56,52,52,56,56,52,52); TSB(N7,L3;P12;56,56,52,52,56,56,52,52); TSB(N8,L3;P11;56,56,52,52,56,56,52,52); TSB(N9,L4;P9;56,56,52,52,56,56,52,52); TSB(N10,L4;P8;56,56,52,52,56,56,52,52); TSB(N11,L4;P7;56,56,52,52,56,56,52,52); TSB(N12,L4;P6;56,56,52,52,56,56,52,52); TSB(N13,L4;P5;56,56,52,52,56,56,52,52); TSB(N14,L4;P4;56,56,52,52,56,56,52,52); TSB(N15,L4;P3;56,56,52,52,56,56,52,52); TSB(N16,L4;P2;56,56,52,52,56,56,52,52); % ;Delays are modeled for Dx to Outputs W and Y, Select to Outputs W and Y, ;and Strobe to Outputs W and Y, for Low to High and High to Low going signals. ;All delays for this part are specified for 15pf and 50pf. :74HC251 TTL 16 LINV(P7;L1); INV(P11;N1;4,4,3,3); INV(P10;N2;4,4,3,3); INV(P9;N3;4,4,3,3); LINV(N1;L2); LINV(N2;L3); LINV(N3;L4); LNAND(P4,N1,N2,N3,L1;L5); LNAND(P3,L2,N2,N3,L1;L6); LNAND(P2,N1,L3,N3,L1;L7); LNAND(P1,L2,L3,N3,L1;L8); LNAND(P15,N1,N2,L4,L1;L9); LNAND(P14,L2,N2,L4,L1;L10); LNAND(P13,N1,L3,L4,L1;L11); LNAND(P12,L2,L3,L4,L1;L12); LNOR(L5,L6,L7,L8,L9,L10,L11,L12;L13); INV(L13;N4;29,29,49,49); BUF(L13;N5;32,32,46,46); TSB(N4,L1;P5;26,26,35,35,26,26,35,35); TSB(N5,L1;P6;27,27,40,40,27,27,40,40); % ;The delays modeled for this part are - Data to Y, Select to Y, and ;Output Control to Y. All delays for this part are modeled for 15pf ;and 50pf. :74HC253 TTL 16 LINV(P1;L1); LINV(P15;L4); INV(P2;N1;7,7,9,9); INV(P14;N2;7,7,9,9); LINV(N1;L2); LINV(N2;L3); LAND(N1,N2,P6,L1;L5); LAND(N1,P5,L3,L1;L6); LAND(N2,P4,L2,L1;L7); LAND(P3,L3,L2,L1;L8); LAND(N1,N2,P10,L4;L9); LAND(N1,P11,L3,L4;L10); LAND(N2,P12,L2,L4;L11); LAND(P13,L3,L2,L4;L12); OR(L5,L6,L7,L8;N3;23,23,35,35); OR(L9,L10,L11,L12;N4;23,23,35,35); TSB(N3,L1;P7;25,25,38,38,25,25,38,38); TSB(N4,L4;P9;25,25,38,38,25,25,38,38); % ;The delays modeled for this part are - Data to Y, Select to Y, and ;Output Control to Y. All delays for this part are modeled for 15pf ;and 50pf. :74HC253B TTL 16 LINV(P1;L1); LINV(P15;L4); INV(P2;N1;7,7,9,9); INV(P14;N2;7,7,9,9); LINV(N1;L2); LINV(N2;L3); LAND(N1,N2,P6,L1;L5); LAND(N1,P5,L3,L1;L6); LAND(N2,P4,L2,L1;L7); LAND(P3,L3,L2,L1;L8); LAND(N1,N2,P10,L4;L9); LAND(N1,P11,L3,L4;L10); LAND(N2,P12,L2,L4;L11); LAND(P13,L3,L2,L4;L12); OR(L5,L6,L7,L8;N3;23,23,35,35); OR(L9,L10,L11,L12;N4;23,23,35,35); TSB(N3,L1;P7;25,25,38,38,25,25,38,38); TSB(N4,L4;P9;25,25,38,38,25,25,38,38); % ;The delays modeled for this part are - propagation delay from Data to ;Output, Select to Output, Also modeled are the enable and disable times ;for the 3-state drivers. Propagation delays are repeated for 50pf ;and 150pf. Enable/disable times are 50pf. :74HC257 TTL 16 LINV(P15;L1); LINV(P1;L11); LINV(L11;L2); LAND(P2,L11;L3); LAND(P3,L2;L4); LAND(P5,L11;L5); LAND(P6,L2;L6); LAND(P11,L11;L7); LAND(P10,L2;L8); LAND(P14,L11;L9); LAND(P13,L2;L10); OR(L3,L4;N1;29,29,38,38); OR(L5,L6;N2;29,29,38,38); OR(L7,L8;N3;29,29,38,38); OR(L9,L10;N4;29,29,38,38); TSB(N1,L1;P4;38,38,38,38,38,38,38,38); TSB(N2,L1;P7;38,38,38,38,38,38,38,38); TSB(N3,L1;P9;38,38,38,38,38,38,38,38); TSB(N4,L1;P12;38,38,38,38,38,38,38,38); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50pF and 150pF :74HC258 TTL 16 LINV(P15;L1); INV(P1;N1;4,4,4,4); LINV(N1;L2); LAND(P2,N1;L3); LAND(P3,L2;L4); LAND(P5,N1;L5); LAND(P6,L2;L6); LAND(P11,N1;L7); LAND(P10,L2;L8); LAND(P14,N1;L9); LAND(P13,L2;L10); OR(L3,L4;N2;25,25,38,38); OR(L5,L6;N3;25,25,38,38); OR(L7,L8;N4;25,25,38,38); OR(L9,L10;N5;25,25,38,38); ITSB(N2,L1;P4;38,38,38,38,50,50,50,50); ITSB(N3,L1;P7;38,38,38,38,50,50,50,50); ITSB(N4,L1;P9;38,38,38,38,50,50,50,50); ITSB(N5,L1;P12;38,38,38,38,50,50,50,50); % :74HC259 TTL 16 INV(P3;N1;3,3,4,4); INV(P2;N2;3,3,4,4); INV(P1;N3;3,3,4,4); LINV(N1;L1); LINV(N2;L2); LINV(N3;L3); LINV(P14;L4); LAND(L1,L2,L3,L4;L5); LAND(L1,L2,N3,L4;L6); LAND(L1,N2,L3,L4;L7); LAND(L1,N2,N3,L4;L8); LAND(N1,L2,L3,L4;L9); LAND(N1,L2,N3,L4;L10); LAND(N1,N2,L3,L4;L11); LAND(N1,N2,N3,L4;L12); DLATCHPC(P13,L5,ONE,P15;P12;32,32,35,35,20,0,16,27,27,16,46,46,50,50,25,0,20,39,39,20); DLATCHPC(P13,L6,ONE,P15;P11;32,32,35,35,20,0,16,27,27,16,46,46,50,50,25,0,20,39,39,20); DLATCHPC(P13,L7,ONE,P15;P10;32,32,35,35,20,0,16,27,27,16,46,46,50,50,25,0,20,39,39,20); DLATCHPC(P13,L8,ONE,P15;P9;32,32,35,35,20,0,16,27,27,16,46,46,50,50,25,0,20,39,39,20); DLATCHPC(P13,L9,ONE,P15;P7;32,32,35,35,20,0,16,27,27,16,46,46,50,50,25,0,20,39,39,20); DLATCHPC(P13,L10,ONE,P15;P6;32,32,35,35,20,0,16,27,27,16,46,46,50,50,25,0,20,39,39,20); DLATCHPC(P13,L11,ONE,P15;P5;32,32,35,35,20,0,16,27,27,16,46,46,50,50,25,0,20,39,39,20); DLATCHPC(P13,L12,ONE,P15;P4;32,32,35,35,20,0,16,27,27,16,46,46,50,50,25,0,20,39,39,20); % :74HC266 TTL 14 SET(RHIGH); XNOR(P1,P2;P3;21,15,31,25); XNOR(P5,P6;P4;21,15,31,25); XNOR(P8,P9;P10;21,15,31,25); XNOR(P12,P13;P11;21,15,31,25); % :74HC266A TTL 14 SET(RHIGH); XNOR(P1,P2;P3;21,15,31,25); XNOR(P5,P6;P4;21,15,31,25); XNOR(P8,P9;P10;21,15,31,25); XNOR(P12,P13;P11;21,15,31,25); % :74HC273 TTL 20 DQFFC(P3,P11,P1;P2;27,27,20,0,16,17,27,27,16,20,40,40,25,0,20,28,40,40,20,25); DQFFC(P4,P11,P1;P5;27,27,20,0,16,17,27,27,16,20,40,40,25,0,20,28,40,40,20,25); DQFFC(P7,P11,P1;P6;27,27,20,0,16,17,27,27,16,20,40,40,25,0,20,28,40,40,20,25); DQFFC(P8,P11,P1;P9;27,27,20,0,16,17,27,27,16,20,40,40,25,0,20,28,40,40,20,25); DQFFC(P13,P11,P1;P12;27,27,20,0,16,17,27,27,16,20,40,40,25,0,20,28,40,40,20,25); DQFFC(P14,P11,P1;P15;27,27,20,0,16,17,27,27,16,20,40,40,25,0,20,28,40,40,20,25); DQFFC(P17,P11,P1;P16;27,27,20,0,16,17,27,27,16,20,40,40,25,0,20,28,40,40,20,25); DQFFC(P18,P11,P1;P19;27,27,20,0,16,17,27,27,16,20,40,40,25,0,20,28,40,40,20,25); % :74HC280 TTL 14 LXOR(P8,P9,P10,P11,P12,P13,P1,P2,P4;L1); INV(L1;P5;35,35,52,52); BUF(L1;P6;35,35,52,52); % ;Data for the following device was taken from ;Motorola High Speed CMOS Logic Data book. ;Delays for 15 pF were calculated using the following equation. ;Tp=Tp(given)-(0.5)(4.5)(15-50)pF/14 :74HC283 TTL 16 INV(P7;N1;15,15,15,15); INV(P7;N10;11,11,11,11); NOR(P5,P6;N2;30,30,30,30); NAND(P5,P6;N3;30,30,30,30); NOR(P2,P3;N4;30,30,30,30); NAND(P2,P3;N5;30,30,30,30); NOR(P14,P15;N6;30,30,30,30); NAND(P14,P15;N7;30,30,30,30); NOR(P11,P12;N8;30,30,30,30); NAND(P11,P12;N9;30,30,30,30); LINV(N1;L1); LINV(N2;L2); LAND(L2,N3;L3); LAND(N1,N3;L4); LINV(N4;L5); LAND(L5,N5;L6); LAND(N1,N3,N5;L7); LAND(N5,N2;L8); LINV(N6;L9); LAND(L9,N7;L10); LAND(N1,N3,N5,N7;L11); LAND(N5,N7,N2;L12); LAND(N7,N4;L13); LINV(N8;L14); LAND(L14,N9;L15); LAND(N10,N3,N5,N7,N9;L16); LAND(N5,N7,N9,N2;L17); LAND(N7,N9,N4;L18); LAND(N9,N6;L19); LNOR(L4,N2;L20); LNOR(L7,L8,N4;L21); LNOR(L11,L12,L13,N6;L22); XOR(L1,L3;P4;32,32,38,38); XOR(L20,L6;P1;32,32,38,38); XOR(L21,L10;P13;32,32,38,38); XOR(L22,L15;P10;32,32,38,38); NOR(L16,L17,L18,L19,N8;P9;20,20,26,26); % ;taken from 1984 National Logic Data Book. :74HC298 TTL 16 INV(P11;N1;0,0,0,0); LINV(P10;L1); LAND(P3,L1;L2); LAND(P2,P10;L3); LAND(P4,L1;L4); LAND(P1,P10;L5); LAND(P9,L1;L6); LAND(P5,P10;L7); LAND(P7,L1;L8); LAND(P6,P10;L9); LOR(L2,L3;L10); LOR(L4,L5;L11); LOR(L6,L7;L12); LOR(L8,L9;L13); DQFF(L10,N1;P15;32,32,20,0,16,16,46,46,25,0,20,20); DQFF(L11,N1;P14;32,32,20,0,16,16,46,46,25,0,20,20); DQFF(L12,N1;P13;32,32,20,0,16,16,46,46,25,0,20,20); DQFF(L13,N1;P12;32,32,20,0,16,16,46,46,25,0,20,20); % :74HC299 TTL 20 LINV(P19;L1); LINV(P1;L2); AND(P19,P1;N1;0,0,0,0); AND(P19,L2;N2;0,0,0,0); AND(L1,P1;N3;0,0,0,0); AND(L1,L2;N4;0,0,0,0); NAND(P19,P1;N5;0,0,0,0); NOR(P2,P3;N6;0,0,0,0); LAND(N5,N6;L3); LAND(P11,N3;L4); LAND(N2,N8;L5); LAND(N1,P7;L6); LAND(N4,N7;L7); LOR(L4,L5,L6,L7;L8); LAND(N7,N3;L9); LAND(N2,N9;L10); LAND(N1,P13;L11); LAND(N4,N8;L12); LOR(L9,L10,L11,L12;L13); LAND(N8,N3;L14); LAND(N2,N10;L15); LAND(N1,P6;L16); LAND(N4,N9;L17); LOR(L14,L15,L16,L17;L18); LAND(N9,N3;L19); LAND(N2,N11;L20); LAND(N1,P14;L21); LAND(N4,N10;L22); LOR(L19,L20,L21,L22;L23); LAND(N10,N3;L24); LAND(N2,N12;L25); LAND(N1,P5;L26); LAND(N4,N11;L27); LOR(L24,L25,L26,L27;L28); LAND(N11,N3;L29); LAND(N2,N13;L30); LAND(N1,P15;L31); LAND(N4,N12;L32); LOR(L29,L30,L31,L32;L33); LAND(N12,N3;L34); LAND(N2,N14;L35); LAND(N1,P4;L36); LAND(N4,N13;L37); LOR(L34,L35,L36,L37;L38); LAND(N13,N3;L39); LAND(N2,P18;L40); LAND(N1,P16;L41); LAND(N4,N14;L42); LOR(L39,L40,L41,L42;L43); DQFFC(L8,P12,P9;N7;25,25,20,0,20,20,30,30,20,10,38,38,25,0,25,25,45,45,25,10); DQFFC(L13,P12,P9;N8;25,25,5,0,20,20,30,30,20,10,38,38,5,0,25,25,45,45,25,10);); DQFFC(L18,P12,P9;N9;25,25,5,0,20,20,30,30,20,10,38,38,5,0,25,25,45,45,25,10);); DQFFC(L23,P12,P9;N10;25,25,5,0,20,20,30,30,20,10,38,38,5,0,25,25,45,45,25,10);); DQFFC(L28,P12,P9;N11;25,25,5,0,20,20,30,30,20,10,38,38,5,0,25,25,45,45,25,10);); DQFFC(L33,P12,P9;N12;25,25,5,0,20,20,30,30,20,10,38,38,5,0,25,25,45,45,25,10);); DQFFC(L38,P12,P9;N13;25,25,5,0,20,20,30,30,20,10,38,38,5,0,25,25,45,45,25,10);); DQFFC(L43,P12,P9;N14;25,25,5,0,20,20,30,30,20,10,38,38,5,0,25,25,45,45,25,10);); BUF(N7;N15;10,10,10,10); BUF(N8;N16;10,10,10,10); BUF(N9;N17;10,10,10,10); BUF(N10;N18;10,10,10,10); BUF(N11;N19;10,10,10,10); BUF(N12;N20;10,10,10,10); BUF(N13;N21;10,10,10,10); BUF(N14;N22;10,10,10,10); TSB(N15,L3;P7;40,40,40,40,40,40,40,40); TSB(N16,L3;P13;40,40,40,40,40,40,40,40); TSB(N17,L3;P6;40,40,40,40,40,40,40,40); TSB(N18,L3;P14;40,40,40,40,40,40,40,40); TSB(N19,L3;P5;40,40,40,40,40,40,40,40); TSB(N20,L3;P15;40,40,40,40,40,40,40,40); TSB(N21,L3;P4;40,40,40,40,40,40,40,40); TSB(N22,L3;P16;40,40,40,40,40,40,40,40); BUF(N7;P8;10,10,10,10); BUF(N14;P17;10,10,10,10); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50pf and 150pF :74HC352 TTL 16 LINV(P1;L1); LINV(P15;L2); INV(P2;N1;2,2,4,4); INV(P14;N2;2,2,4,4); LINV(N1;L3); LINV(N2;L4); AND(L1,N1,N2,P6;N3;10,10,8,8); AND(L1,N1,L4,P5;N4;10,10,8,8); AND(L1,L3,N2,P4;N5;10,10,8,8); AND(L1,L3,L4,P3;N6;10,10,8,8); AND(P10,N1,N2,L2;N7;10,10,8,8); AND(P11,N1,L4,L2;N8;10,10,8,8); AND(P12,L3,N2,L2;N9;10,10,8,8); AND(P13,L3,L4,L2;N10;10,10,8,8); NOR(N3,N4,N5,N6;P7;34,34,55,55); NOR(N7,N8,N9,N10;P9;34,34,55,55); % ;taken from 1988 TI High-Speed CMOS Logic data book. :74HC353 TTL 16 INV(P2;N1;2,2,4,4); INV(P14;N2;2,2,4,4); LINV(N1;L1); LINV(N2;L2); LINV(P1;L3); LINV(P15;L4); LAND(L3,N1,N2,P6;L5); LAND(L3,N1,L2,P5;L6); LAND(L3,L1,N2,P4;L7); LAND(L3,L1,L2,P3;L8); LAND(P10,N1,N2,L4;L9); LAND(P11,N1,L2,L4;L10); LAND(P12,L1,N2,L4;L11); LAND(P13,L1,L2,L4;L12); NOR(L3,L4,L5,L6;N3;44,44,63,63); NOR(L7,L8,L9,L10;N4;44,44,63,63); TSB(N3,L3;P7;34,34,34,34,55,55,55,55); TSB(N4,L4;P9;34,34,34,34,55,55,55,55); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC354 TTL 20 LINV(P17;L1); INV(P11;N15;6,6,6,6); LNOR(P15,P16,L1;L3); DLATCH(P14,N15;N1;32,32,30,30,19,5,20,32,32,20,20,19,5,20); DLATCH(P13,N15;N2;32,32,30,30,19,5,20,32,32,20,20,19,5,20); DLATCH(P12,N15;N3;32,32,30,30,19,5,20,32,32,20,20,19,5,20); LINV(N1;L4); LINV(N2;L5); LINV(N3;L6); LINV(P9;L7); DLATCH(P8,L7;N4;20,20,30,30,19,5,20,20,20,30,30,19,5,20); DLATCH(P7,L7;N5;20,20,30,30,19,5,20,20,20,30,30,19,5,20); DLATCH(P6,L7;N6;20,20,30,30,19,5,20,20,20,30,30,19,5,20); DLATCH(P5,L7;N7;20,20,30,30,19,5,20,20,20,30,30,19,5,20); DLATCH(P4,L7;N8;20,20,30,30,19,5,20,20,20,30,30,19,5,20); DLATCH(P3,L7;N9;20,20,30,30,19,5,20,20,20,30,30,19,5,20); DLATCH(P2,L7;N10;20,20,30,30,19,5,20,20,20,30,30,19,5,20); DLATCH(P1,L7;N11;20,20,30,30,19,5,20,20,20,30,30,19,5,20); LAND(L4,L5,L6,N4;L8); LAND(N1,L5,L6,N5;L9); LAND(L4,N2,L6,N6;L10); LAND(N1,N2,L6,N7;L11); LAND(L4,L5,N3,N8;L12); LAND(N1,L5,N3,N9;L13); LAND(L4,N2,N3,N10;L14); LAND(N1,N2,N3,N11;L15); NOR(L8,L9,L10,L11,L12,L13,L14,L15;N12;20,20,20,20); INV(N12;N13;19,19,28,28); BUF(N12;N14;19,19,28,28); TSB(N13,L3;P19;31,31,41,41,31,31,41,41); TSB(N14,L3;P18;31,31,41,41,31,31,41,41); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are for 50 and 150pF, :74HC356 TTL 20 LINV(P17;L1); INV(P11;N15;12,0,12,0); LNOR(P15,P16,L1;L3); DLATCH(P14,N15;N1;28,28,20,20,19,5,20,28,28,20,20,19,5,20); DLATCH(P13,N15;N2;28,28,20,20,19,5,20,28,28,20,20,19,5,20); DLATCH(P12,N15;N3;28,28,20,20,19,5,20,28,28,20,20,19,5,20); LINV(N1;L4); LINV(N2;L5); LINV(N3;L6); DQFF(P8,P9;N4;20,20,19,5,20,20,20,20,19,5,20,20); DQFF(P7,P9;N5;20,20,19,5,20,20,20,20,19,5,20,20); DQFF(P6,P9;N6;20,20,19,5,20,20,20,20,19,5,20,20); DQFF(P5,P9;N7;20,20,19,5,20,20,20,20,19,5,20,20); DQFF(P4,P9;N8;20,20,19,5,20,20,20,20,19,5,20,20); DQFF(P3,P9;N9;20,20,19,5,20,20,20,20,19,5,20,20); DQFF(P2,P9;N10;20,20,19,5,20,20,20,20,19,5,20,20); DQFF(P1,P9;N11;20,20,19,5,20,20,20,20,19,5,20,20); LAND(L4,L5,L6,N4;L8); LAND(N1,L5,L6,N5;L9); LAND(L4,N2,L6,N6;L10); LAND(N1,N2,L6,N7;L11); LAND(L4,L5,N3,N8;L12); LAND(N1,L5,N3,N9;L13); LAND(L4,N2,N3,N10;L14); LAND(N1,N2,N3,N11;L15); NOR(L8,L9,L10,L11,L12,L13,L14,L15;N14;30,30,30,30); INV(N14;N12;13,23,13,23); BUF(N14;N13;13,23,13,23); TSB(N12,L3;P19;31,31,41,41,31,31,41,41); TSB(N13,L3;P18;31,31,41,41,31,31,41,41); % :74HC365 TTL 16 LNOR(P1,P15;L1); BUF(P2;N1;22,22,30,30); BUF(P4;N2;22,22,30,30); BUF(P6;N3;22,22,30,30); BUF(P10;N4;22,22,30,30); BUF(P12;N5;22,22,30,30); BUF(P14;N6;22,22,30,30); TSB(N1,L1;P3;55,55,55,55,55,55,55,55); TSB(N2,L1;P5;55,55,55,55,55,55,55,55); TSB(N3,L1;P7;55,55,55,55,55,55,55,55); TSB(N4,L1;P9;55,55,55,55,55,55,55,55); TSB(N5,L1;P11;55,55,55,55,55,55,55,55); TSB(N6,L1;P13;55,55,55,55,55,55,55,55); % :74HC366 TTL 16 LNOR(P1,P15;L1); INV(P2;N1;18,18,24,24); INV(P4;N2;18,18,24,24); INV(P6;N3;18,18,24,24); INV(P10;N4;18,18,24,24); INV(P12;N5;18,18,24,24); INV(P14;N6;18,18,24,24); TSB(N1,L1;P3;55,55,55,55,55,55,55,55); TSB(N2,L1;P5;55,55,55,55,55,55,55,55); TSB(N3,L1;P7;55,55,55,55,55,55,55,55); TSB(N4,L1;P9;55,55,55,55,55,55,55,55); TSB(N5,L1;P11;55,55,55,55,55,55,55,55); TSB(N6,L1;P13;55,55,55,55,55,55,55,55); % :74HC367 TTL 16 LINV(P1;L1); LINV(P15;L2); BUF(P2;N1;22,22,30,30); BUF(P4;N2;22,22,30,30); BUF(P6;N3;22,22,30,30); BUF(P10;N4;22,22,30,30); BUF(P12;N5;22,22,30,30); BUF(P14;N6;22,22,30,30); TSB(N1,L1;P3;47,47,44,44,47,47,44,44); TSB(N2,L1;P5;47,47,44,44,47,47,44,44); TSB(N3,L1;P7;47,47,44,44,47,47,44,44); TSB(N4,L1;P9;47,47,44,44,47,47,44,44); TSB(N5,L2;P11;47,47,44,44,47,47,44,44); TSB(N6,L2;P13;47,47,44,44,47,47,44,44); % :74HC368 TTL 16 LINV(P1;L1); LINV(P15;L2); INV(P2;N1;18,18,24,24); INV(P4;N2;18,18,24,24); INV(P6;N3;18,18,24,24); INV(P10;N4;18,18,24,24); INV(P12;N5;18,18,24,24); INV(P14;N6;18,18,24,24); TSB(N1,L1;P3;47,47,44,44,47,47,44,44); TSB(N2,L1;P5;47,47,44,44,47,47,44,44); TSB(N3,L1;P7;47,47,44,44,47,47,44,44); TSB(N4,L1;P9;47,47,44,44,47,47,44,44); TSB(N5,L2;P11;47,47,44,44,47,47,44,44); TSB(N6,L2;P13;47,47,44,44,47,47,44,44); % :74HC373 TTL 20 LINV(P1;L1); DLATCH(P3,P11;N1;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P4,P11;N2;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P7,P11;N3;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P8,P11;N4;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P13,P11;N5;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P14,P11;N6;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P17,P11;N7;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P18,P11;N8;25,25,30,30,5,10,16,37,37,44,44,6,13,20); TSB(N1,L1;P2;37,37,37,37,37,37,37,37); TSB(N2,L1;P5;37,37,37,37,37,37,37,37); TSB(N3,L1;P6;37,37,37,37,37,37,37,37); TSB(N4,L1;P9;37,37,37,37,37,37,37,37); TSB(N5,L1;P12;37,37,37,37,37,37,37,37); TSB(N6,L1;P15;37,37,37,37,37,37,37,37); TSB(N7,L1;P16;37,37,37,37,37,37,37,37); TSB(N8,L1;P19;37,37,37,37,37,37,37,37); % ;The Propagation delays modeled are as follows - Delay form Clock to Q, ;set up and hold time, and the minimum pulse width of the clock. These ;delays are repeated for 50pf and 150pf. The Enable/Disable time for ;the 3-state drivers are also modeled for 50pf. :74HC374 TTL 20 LINV(P1;L1); DQFF(P3,P11;N1;45,45,25,5,22,22,57,57,25,5,20,22); DQFF(P4,P11;N2;45,45,25,5,22,22,57,57,25,5,20,22); DQFF(P7,P11;N3;45,45,25,5,22,22,57,57,25,5,20,22); DQFF(P8,P11;N4;45,45,25,5,22,22,57,57,25,5,20,22); DQFF(P13,P11;N5;45,45,25,5,22,22,57,57,25,5,20,22); DQFF(P14,P11;N6;45,45,25,5,22,22,57,57,25,5,20,22); DQFF(P17,P11;N7;45,45,25,5,22,22,57,57,25,5,20,22); DQFF(P18,P11;N8;45,45,25,5,22,22,57,57,25,5,20,22); TSB(N1,L1;P2;37,37,37,37,37,37,37,37); TSB(N2,L1;P5;37,37,37,37,37,37,37,37); TSB(N3,L1;P6;37,37,37,37,37,37,37,37); TSB(N4,L1;P9;37,37,37,37,37,37,37,37); TSB(N5,L1;P12;37,37,37,37,37,37,37,37); TSB(N6,L1;P15;37,37,37,37,37,37,37,37); TSB(N7,L1;P16;37,37,37,37,37,37,37,37); TSB(N8,L1;P19;37,37,37,37,37,37,37,37); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pf were extrapolated :74HC375 TTL 16 LINV(P1;L1); LINV(P7;L2); LINV(P9;L3); LINV(P15;L4); DLATCH(L1,P4;P2;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(L2,P4;P6;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(L3,P12;P10;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(L4,P12;P14;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(P1,P4;P3;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(P7,P4;P5;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(P9,P12;P11;20,20,23,23,25,5,20,30,30,33,33,25,5,20); DLATCH(P15,P12;P13;20,20,23,23,25,5,20,30,30,33,33,25,5,20); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC377 TTL 20 LINV(P1;L1); AND(L1,P11;N2;0,0,0,0); DQFF(P3,N2;P2;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P4,N2;P5;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P7,N2;P6;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P8,N2;P9;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P13,N2;P12;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P14,N2;P15;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P17,N2;P16;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P18,N2;P19;30,30,25,5,25,25,40,40,25,5,25,25); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC378 TTL 16 LINV(P1;L1); AND(L1,P9;N2;0,0,0,0); DQFF(P3,N2;P2;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P4,N2;P5;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P6,N2;P7;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P11,N2;P10;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P13,N2;P12;30,30,25,5,25,25,40,40,25,5,25,25); DQFF(P14,N2;P15;30,30,25,5,25,25,40,40,25,5,25,25); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC379 TTL 16 LINV(P1;L1); AND(L1,P9;N2;0,0,0,0); DFF(P4,N2;P2,P3;30,30,25,5,25,25,40,40,25,5,25,25); DFF(P5,N2;P7,P6;30,30,25,5,25,25,40,40,25,5,25,25); DFF(P12,N2;P10,P11;30,30,25,5,25,25,40,40,25,5,25,25); DFF(P13,N2;P15,P14;30,30,25,5,25,25,40,40,25,5,25,25); % :74HC390 TTL 16 LINV(P2;L1); LINV(P14;L2); LINV(N7;L9); LINV(N8;L10); LINV(N9;L11); LINV(N10;L12); LINV(N11;L13); LINV(N12;L14); LINV(N13;L15); LINV(N14;L16); LAND(L10,L12;L3); LAND(L11,L12;L4); LNOR(L3,L4;L7); LAND(L14,L16;L5); LAND(L15,L16;L6); LNOR(L5,L6;L8); INV(P1;N1;0,0,0,0); INV(P15;N2;0,0,0,0); NAND(P4,L12;N3;0,0,0,0); NAND(P12,L16;N5;0,0,0,0); NAND(P4,L7;N4;0,0,0,0); NAND(P12,L8;N6;0,0,0,0); DQFFC(L9,N1,L1;N7;10,10,10,0,16,16,18,18,16,5,10,10,10,0,16,16,21,21,20,5); DFFC(L10,N3,L1;N8,N15;11,11,10,0,16,16,18,18,16,5,13,13,10,0,20,20,21,21,20,5); DQFFC(L11,N15,L1;N9;11,11,10,0,16,16,0,0,16,5,13,13,10,0,20,20,0,0,20,5); DQFFC(L12,N4,L1;N10;11,11,10,0,16,16,18,18,16,5,13,13,10,0,20,20,21,21,20,5); DQFFC(L13,N2,L2;N11;10,10,10,0,16,16,18,18,16,5,10,10,10,0,16,16,21,21,20,5); DFFC(L14,N5,L2;N12,N16;11,11,10,0,16,16,18,18,16,5,13,13,10,0,20,20,21,21,20,5); DQFFC(L15,N16,L2;N13;11,11,10,0,16,16,0,0,16,5,13,13,10,0,20,20,0,0,20,5); DQFFC(L16,N6,L2;N14;11,11,10,0,16,16,18,18,16,5,13,13,10,0,20,20,21,21,20,5); BUF(N7;P3;10,10,20,20); BUF(N8;P5;10,10,20,20); BUF(N9;P6;10,10,20,20); BUF(N10;P7;10,10,20,20); BUF(N11;P13;10,10,20,20); BUF(N12;P11;10,10,20,20); BUF(N13;P10;10,10,20,20); BUF(N14;P9;10,10,20,20); % :74HC393 TTL 14 INV(P1;N1;0,0,0,0); INV(P13;N2;0,0,0,0); LINV(P2;L1); LINV(P12;L2); LINV(N9;L3); LINV(N10;L4); LINV(N11;L5); LINV(N12;L6); LINV(N13;L7); LINV(N14;L8); LINV(N15;L9); LINV(N16;L10); DQFFP(L3,N1,L1;N9;10,10,10,0,20,20,18,18,20,25,10,10,10,0,20,20,21,21,20,25); DQFFP(L4,N9,L1;N10;15,15,10,0,20,20,0,0,20,25,17,17,10,0,20,20,0,0,20,25); DQFFP(L5,N10,L1;N11;7,7,10,0,20,20,0,0,20,25,13,13,10,0,20,20,0,0,20,25); DQFFP(L6,N11,L1;N12;8,8,10,0,20,20,0,0,20,25,12,12,10,0,20,20,0,0,20,25); DQFFP(L7,N2,L2;N13;10,10,10,0,20,20,18,18,20,25,10,10,10,0,20,20,21,21,20,25); DQFFP(L8,N13,L2;N14;15,15,10,0,20,20,0,0,20,25,17,17,10,0,20,20,0,0,20,25); DQFFP(L9,N14,L2;N15;7,7,10,0,20,20,0,0,20,25,13,13,10,0,20,20,0,0,20,25); DQFFP(L10,N15,L2;N16;8,8,10,0,20,20,0,0,20,25,12,12,10,0,20,20,0,0,20,25); INV(N9;P3;10,10,20,20); INV(N10;P4;10,10,20,20); INV(N11;P5;10,10,20,20); INV(N12;P6;10,10,20,20); INV(N13;P11;10,10,20,20); INV(N14;P10;10,10,20,20); INV(N15;P9;10,10,20,20); INV(N16;P8;10,10,20,20); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC490 TTL 16 LINV(P4;L1); LINV(P12;L2); LINV(P2;L3); LINV(P14;L4); LAND(L3,L1;L5); LAND(L4,L2;L6); LINV(N7;L13); LINV(N8;L14); LINV(N9;L15); LINV(N10;L16); LINV(N11;L17); LINV(N12;L18); LINV(N13;L19); LINV(N14;L20); LAND(L14,L16;L7); LAND(L16,L15;L8); LAND(L18,L20;L9); LAND(L20,L19;L10); LNOR(L7,L8;L11); LNOR(L9,L10;L12); INV(P1;N1;0,0,0,0); INV(P15;N2;0,0,0,0); NAND(N7,L16;N3;0,0,0,0); NAND(N7,L11;N4;0,0,0,0); NAND(N11,L20;N5;0,0,0,0); NAND(N11,L12;N6;0,0,0,0); INV(N8;N15;0,0,0,0); INV(N12;N16;0,0,0,0); DQFFPC(L13,N1,L1,L3;N7;3,3,5,0,20,20,18,5,20,0,3,3,5,0,20,20,18,5,20,0); DQFFC(L14,N3,L5;N8;15,15,5,0,20,20,7,5,20,0,15,15,5,0,20,20,7,5,20,0); DQFFC(L15,N15,L5;N9;13,13,5,0,20,20,7,5,20,0,13,13,5,0,20,20,7,5,20,0); DQFFPC(L16,N4,L1,L3;N10;15,15,5,0,20,20,18,5,20,0,15,15,5,0,20,20,18,5,20,0); DQFFPC(L17,N2,L2,L4;N11;3,3,5,0,20,20,18,5,20,0,3,3,5,0,20,20,18,5,20,0); DQFFC(L18,N5,L6;N12;15,15,5,0,20,20,7,5,20,0,15,15,5,0,20,20,7,5,20,0); DQFFC(L19,N16,L6;N13;13,13,5,0,20,20,7,5,20,0,13,13,5,0,20,20,7,5,20,0); DQFFPC(L20,N6,L2,L4;N14;15,15,5,0,20,20,18,5,20,0,15,15,5,0,20,20,18,5,20,0); BUF(N7;P3;18,18,28,28); BUF(N8;P5;18,18,28,28); BUF(N9;P6;18,18,28,28); BUF(N10;P7;18,18,28,28); BUF(N11;P13;18,18,28,28); BUF(N12;P11;18,18,28,28); BUF(N13;P10;18,18,28,28); BUF(N14;P9;18,18,28,28); % :74HC521 TTL 20 XNOR(P2,P3;N1;10,10,14,14); XNOR(P4,P5;N2;10,10,14,14); XNOR(P6,P7;N3;10,10,14,14); XNOR(P8,P9;N4;10,10,14,14); XNOR(P11,P12;N5;10,10,14,14); XNOR(P13,P14;N6;10,10,14,14); XNOR(P15,P16;N7;10,10,14,14); XNOR(P17,P18;N8;10,10,14,14); LINV(P1;L1); NAND(N1,N2,N3,N4,N5,N6,N7,N8,L1;P19;20,20,30,30); % :74HC533 TTL 20 LINV(P1;L1); DLATCH(P3,P11;N1;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P4,P11;N2;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P7,P11;N3;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P8,P11;N4;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P13,P11;N5;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P14,P11;N6;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P17,P11;N7;25,25,30,30,5,10,16,37,37,44,44,6,13,20); DLATCH(P18,P11;N8;25,25,30,30,5,10,16,37,37,44,44,6,13,20); ITSB(N1,L1;P2;37,37,37,37,37,37,37,37); ITSB(N2,L1;P5;37,37,37,37,37,37,37,37); ITSB(N3,L1;P6;37,37,37,37,37,37,37,37); ITSB(N4,L1;P9;37,37,37,37,37,37,37,37); ITSB(N5,L1;P12;37,37,37,37,37,37,37,37); ITSB(N6,L1;P15;37,37,37,37,37,37,37,37); ITSB(N7,L1;P16;37,37,37,37,37,37,37,37); ITSB(N8,L1;P19;37,37,37,37,37,37,37,37); % :74HC534 TTL 20 LINV(P1;L1); DQFF(P3,P11;N1;32,32,20,5,16,16,45,45,25,5,20,20); DQFF(P4,P11;N2;32,32,20,5,16,16,45,45,25,5,20,20); DQFF(P7,P11;N3;32,32,20,5,16,16,45,45,25,5,20,20); DQFF(P8,P11;N4;32,32,20,5,16,16,45,45,25,5,20,20); DQFF(P13,P11;N5;32,32,20,5,16,16,45,45,25,5,20,20); DQFF(P14,P11;N6;32,32,20,5,16,16,45,45,25,5,20,20); DQFF(P17,P11;N7;32,32,20,5,16,16,45,45,25,5,20,20); DQFF(P18,P11;N8;32,32,20,5,16,16,45,45,25,5,20,20); ITSB(N1,L1;P2;37,37,37,37,37,37,37,37); ITSB(N2,L1;P5;37,37,37,37,37,37,37,37); ITSB(N3,L1;P6;37,37,37,37,37,37,37,37); ITSB(N4,L1;P9;37,37,37,37,37,37,37,37); ITSB(N5,L1;P12;37,37,37,37,37,37,37,37); ITSB(N6,L1;P15;37,37,37,37,37,37,37,37); ITSB(N7,L1;P16;37,37,37,37,37,37,37,37); ITSB(N8,L1;P19;37,37,37,37,37,37,37,37); % :74HC540 TTL 20 LNOR(P1,P19;L1); INV(P2;N1;18,18,25,25); INV(P3;N2;18,18,25,25); INV(P4;N3;18,18,25,25); INV(P5;N4;18,18,25,25); INV(P6;N5;18,18,25,25); INV(P7;N6;18,18,25,25); INV(P8;N7;18,18,25,25); INV(P9;N8;18,18,25,25); TSB(N1,L1;P18;38,38,38,38,38,38,38,38); TSB(N2,L1;P17;38,38,38,38,38,38,38,38); TSB(N3,L1;P16;38,38,38,38,38,38,38,38); TSB(N4,L1;P15;38,38,38,38,38,38,38,38); TSB(N5,L1;P14;38,38,38,38,38,38,38,38); TSB(N6,L1;P13;38,38,38,38,38,38,38,38); TSB(N7,L1;P12;38,38,38,38,38,38,38,38); TSB(N8,L1;P11;38,38,38,38,38,38,38,38); % :74HC541 TTL 20 LNOR(P1,P19;L1); BUF(P2;N1;20,20,29,29); BUF(P3;N2;20,20,29,29); BUF(P4;N3;20,20,29,29); BUF(P5;N4;20,20,29,29); BUF(P6;N5;20,20,29,29); BUF(P7;N6;20,20,29,29); BUF(P8;N7;20,20,29,29); BUF(P9;N8;20,20,29,29); TSB(N1,L1;P18;38,38,38,38,38,38,38,38); TSB(N2,L1;P17;38,38,38,38,38,38,38,38); TSB(N3,L1;P16;38,38,38,38,38,38,38,38); TSB(N4,L1;P15;38,38,38,38,38,38,38,38); TSB(N5,L1;P14;38,38,38,38,38,38,38,38); TSB(N6,L1;P13;38,38,38,38,38,38,38,38); TSB(N7,L1;P12;38,38,38,38,38,38,38,38); TSB(N8,L1;P11;38,38,38,38,38,38,38,38); % :74HC563 TTL 20 LINV(P1;L1); DLATCH(P2,P11;N1;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P3,P11;N2;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P4,P11;N3;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P5,P11;N4;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P6,P11;N5;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P7,P11;N6;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P8,P11;N7;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P9,P11;N8;19,19,20,20,15,5,16,28,28,29,29,19,6,20); ITSB(N1,L1;P19;35,35,31,31,35,35,31,31); ITSB(N2,L1;P18;35,35,31,31,35,35,31,31); ITSB(N3,L1;P17;35,35,31,31,35,35,31,31); ITSB(N4,L1;P16;35,35,31,31,35,35,31,31); ITSB(N5,L1;P15;35,35,31,31,35,35,31,31); ITSB(N6,L1;P14;35,35,31,31,35,35,31,31); ITSB(N7,L1;P13;35,35,31,31,35,35,31,31); ITSB(N8,L1;P12;35,35,31,31,35,35,31,31); % :74HC564 TTL 20 LINV(P1;L1); DQFF(P2,P11;N1;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P3,P11;N2;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P4,P11;N3;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P5,P11;N4;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P6,P11;N5;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P7,P11;N6;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P8,P11;N7;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P9,P11;N8;20,20,20,0,16,13,29,29,25,0,20,22); ITSB(N1,L1;P19;35,35,31,31,35,35,31,31); ITSB(N2,L1;P18;35,35,31,31,35,35,31,31); ITSB(N3,L1;P17;35,35,31,31,35,35,31,31); ITSB(N4,L1;P16;35,35,31,31,35,35,31,31); ITSB(N5,L1;P15;35,35,31,31,35,35,31,31); ITSB(N6,L1;P14;35,35,31,31,35,35,31,31); ITSB(N7,L1;P13;35,35,31,31,35,35,31,31); ITSB(N8,L1;P12;35,35,31,31,35,35,31,31); % :74HC573 TTL 20 LINV(P1;L1); DLATCH(P2,P11;N1;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P3,P11;N2;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P4,P11;N3;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P5,P11;N4;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P6,P11;N5;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P7,P11;N6;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P8,P11;N7;19,19,20,20,15,5,16,28,28,29,29,19,6,20); DLATCH(P9,P11;N8;19,19,20,20,15,5,16,28,28,29,29,19,6,20); TSB(N1,L1;P19;35,35,31,31,35,35,31,31); TSB(N2,L1;P18;35,35,31,31,35,35,31,31); TSB(N3,L1;P17;35,35,31,31,35,35,31,31); TSB(N4,L1;P16;35,35,31,31,35,35,31,31); TSB(N5,L1;P15;35,35,31,31,35,35,31,31); TSB(N6,L1;P14;35,35,31,31,35,35,31,31); TSB(N7,L1;P13;35,35,31,31,35,35,31,31); TSB(N8,L1;P12;35,35,31,31,35,35,31,31); % :74HC574 TTL 20 LINV(P1;L1); DQFF(P2,P11;N1;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P3,P11;N2;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P4,P11;N3;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P5,P11;N4;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P6,P11;N5;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P7,P11;N6;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P8,P11;N7;20,20,20,0,16,13,29,29,25,0,20,22); DQFF(P9,P11;N8;20,20,20,0,16,13,29,29,25,0,20,22); TSB(N1,L1;P19;35,35,31,31,35,35,31,31); TSB(N2,L1;P18;35,35,31,31,35,35,31,31); TSB(N3,L1;P17;35,35,31,31,35,35,31,31); TSB(N4,L1;P16;35,35,31,31,35,35,31,31); TSB(N5,L1;P15;35,35,31,31,35,35,31,31); TSB(N6,L1;P14;35,35,31,31,35,35,31,31); TSB(N7,L1;P13;35,35,31,31,35,35,31,31); TSB(N8,L1;P12;35,35,31,31,35,35,31,31); % ;The following is an "A" type device and was taken from 1988 TI High ;Speed CMOS Logic Data book. :74HC590 TTL 16 LINV(P14;L1); LINV(P12;L2); LINV(N1;L3); LINV(N9;L4); LINV(N10;L5); LINV(N11;L6); LINV(N12;L7); LINV(N13;L8); LINV(N14;L9); LINV(N15;L10); LINV(N16;L11); DLATCH(P11,L2;N1;3,3,1,1,0,0,1,3,3,1,1,0,0,1); NAND(N9,L3;N2;0,0,0,0); NAND(N9,L3,N10;N3;0,0,0,0); NAND(N9,L3,N10,N11;N4;0,0,0,0); NAND(N9,L3,N10,N11,N12;N5;0,0,0,0); NAND(N9,L3,N10,N11,N12,N13;N6;0,0,0,0); NAND(N9,L3,N10,N11,N12,N13,N14;N7;0,0,0,0); NAND(N9,L3,N10,N11,N12,N13,N14,N15;N8;0,0,0,0); DQFFC(L4,N1,P10;N9;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L5,N2,P10;N10;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L6,N3,P10;N11;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L7,N4,P10;N12;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L8,N5,P10;N13;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L9,N6,P10;N14;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L10,N7,P10;N15;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L11,N8,P10;N16;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFF(N9,P13;N17;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N10,P13;N18;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N11,P13;N19;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N12,P13;N20;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N13,P13;N21;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N14,P13;N22;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N15,P13;N23;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N16,P13;N24;25,25,0,0,31,31,25,25,0,0,31,31); BUF(N17;N25;5,5,10,10); BUF(N18;N26;5,5,10,10); BUF(N19;N27;5,5,10,10); BUF(N20;N28;5,5,10,10); BUF(N21;N29;5,5,10,10); BUF(N22;N30;5,5,10,10); BUF(N23;N31;5,5,10,10); BUF(N24;N32;5,5,10,10); TSB(N25,L1;P15;31,31,31,31,31,31,31,31); TSB(N26,L1;P1;31,31,31,31,31,31,31,31); TSB(N27,L1;P2;31,31,31,31,31,31,31,31); TSB(N28,L1;P3;31,31,31,31,31,31,31,31); TSB(N29,L1;P4;31,31,31,31,31,31,31,31); TSB(N30,L1;P5;31,31,31,31,31,31,31,31); TSB(N31,L1;P6;31,31,31,31,31,31,31,31); TSB(N32,L1;P7;31,31,31,31,31,31,31,31); NAND(N16,N15,N14,N13,N12,N11,N10,N9;P9;5,5,10,10); % ;taken from 1988 TI High Speed CMOS Logic Data book. :74HC590A TTL 16 LINV(P14;L1); LINV(P12;L2); LINV(N1;L3); LINV(N9;L4); LINV(N10;L5); LINV(N11;L6); LINV(N12;L7); LINV(N13;L8); LINV(N14;L9); LINV(N15;L10); LINV(N16;L11); DLATCH(P11,L2;N1;3,3,1,1,0,0,1,3,3,1,1,0,0,1); NAND(N9,L3;N2;0,0,0,0); NAND(N9,L3,N10;N3;0,0,0,0); NAND(N9,L3,N10,N11;N4;0,0,0,0); NAND(N9,L3,N10,N11,N12;N5;0,0,0,0); NAND(N9,L3,N10,N11,N12,N13;N6;0,0,0,0); NAND(N9,L3,N10,N11,N12,N13,N14;N7;0,0,0,0); NAND(N9,L3,N10,N11,N12,N13,N14,N15;N8;0,0,0,0); DQFFC(L4,N1,P10;N9;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L5,N2,P10;N10;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L6,N3,P10;N11;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L7,N4,P10;N12;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L8,N5,P10;N13;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L9,N6,P10;N14;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L10,N7,P10;N15;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFFC(L11,N8,P10;N16;25,25,25,12,31,31,23,23,25,25,25,25,25,12,31,31,23,23,25,25); DQFF(N9,P13;N17;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N10,P13;N18;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N11,P13;N19;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N12,P13;N20;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N13,P13;N21;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N14,P13;N22;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N15,P13;N23;25,25,0,0,31,31,25,25,0,0,31,31); DQFF(N16,P13;N24;25,25,0,0,31,31,25,25,0,0,31,31); BUF(N17;N25;5,5,10,10); BUF(N18;N26;5,5,10,10); BUF(N19;N27;5,5,10,10); BUF(N20;N28;5,5,10,10); BUF(N21;N29;5,5,10,10); BUF(N22;N30;5,5,10,10); BUF(N23;N31;5,5,10,10); BUF(N24;N32;5,5,10,10); TSB(N25,L1;P15;31,31,31,31,31,31,31,31); TSB(N26,L1;P1;31,31,31,31,31,31,31,31); TSB(N27,L1;P2;31,31,31,31,31,31,31,31); TSB(N28,L1;P3;31,31,31,31,31,31,31,31); TSB(N29,L1;P4;31,31,31,31,31,31,31,31); TSB(N30,L1;P5;31,31,31,31,31,31,31,31); TSB(N31,L1;P6;31,31,31,31,31,31,31,31); TSB(N32,L1;P7;31,31,31,31,31,31,31,31); NAND(N16,N15,N14,N13,N12,N11,N10,N9;P9;5,5,10,10); % ;Data for the following device was taken from ;Motorola HIGH SPEED CMOS Logic Data Book. ;Delays for 15 pF were calculated as follows- ;Tp=Tp(at 50pF) + 0.5(4.5V)(15-50)pF/14 :74HC595 TTL 16 LINV(P13;L1); DQFFC(P14,P11,P10;N1;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N1,P11,P10;N2;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N2,P11,P10;N3;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N3,P11,P10;N4;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N4,P11,P10;N5;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N5,P11,P10;N6;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N6,P11,P10;N7;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N7,P11,P10;N8;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFF(N1,P12;N9;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N2,P12;N10;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N3,P12;N11;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N4,P12;N12;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N5,P12;N13;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N6,P12;N14;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N7,P12;N15;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N8,P12;N16;38,38,25,5,20,20,44,44,25,5,20,20); BUF(N8;P9;32,32,38,38); TSB(N9,L1;P15;38,38,38,38,38,38,38,38); TSB(N10,L1;P1;38,38,38,38,38,38,38,38); TSB(N11,L1;P2;38,38,38,38,38,38,38,38); TSB(N12,L1;P3;38,38,38,38,38,38,38,38); TSB(N13,L1;P4;38,38,38,38,38,38,38,38); TSB(N14,L1;P5;38,38,38,38,38,38,38,38); TSB(N15,L1;P6;38,38,38,38,38,38,38,38); TSB(N16,L1;P7;38,38,38,38,38,38,38,38); % ;Data for the following device was taken from ;Motorola HIGH SPEED CMOS Logic Data Book. ;Delays for 15 pF were calculated as follows- ;Tp=Tp(at 50pF) + 0.5(4.5V)(15-50)pF/14 :74HC595A TTL 16 LINV(P13;L1); DQFFC(P14,P11,P10;N1;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N1,P11,P10;N2;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N2,P11,P10;N3;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N3,P11,P10;N4;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N4,P11,P10;N5;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N5,P11,P10;N6;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N6,P11,P10;N7;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFFC(N7,P11,P10;N8;15,15,25,5,20,20,6,6,20,13,15,15,25,5,20,20,6,6,20,13); DQFF(N1,P12;N9;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N2,P12;N10;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N3,P12;N11;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N4,P12;N12;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N5,P12;N13;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N6,P12;N14;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N7,P12;N15;38,38,25,5,20,20,44,44,25,5,20,20); DQFF(N8,P12;N16;38,38,25,5,20,20,44,44,25,5,20,20); BUF(N8;P9;32,32,38,38); TSB(N9,L1;P15;38,38,38,38,38,38,38,38); TSB(N10,L1;P1;38,38,38,38,38,38,38,38); TSB(N11,L1;P2;38,38,38,38,38,38,38,38); TSB(N12,L1;P3;38,38,38,38,38,38,38,38); TSB(N13,L1;P4;38,38,38,38,38,38,38,38); TSB(N14,L1;P5;38,38,38,38,38,38,38,38); TSB(N15,L1;P6;38,38,38,38,38,38,38,38); TSB(N16,L1;P7;38,38,38,38,38,38,38,38); % :74HC597 TTL 16 INV(P13;N1;0,0,0,0); DFF(P15,P12;N2,N3;15,15,20,0,16,16,21,21,25,0,20,20); DFF(P1,P12;N4,N5;15,15,20,0,16,16,21,21,25,0,20,20); DFF(P2,P12;N6,N7;15,15,20,0,16,16,21,21,25,0,20,20); DFF(P3,P12;N8,N9;15,15,20,0,16,16,21,21,25,0,20,20); DFF(P4,P12;N10,N11;15,15,20,0,16,16,21,21,25,0,20,20); DFF(P5,P12;N12,N13;15,15,20,0,16,16,21,21,25,0,20,20); DFF(P6,P12;N14,N15;15,15,20,0,16,16,21,21,25,0,20,20); DFF(P7,P12;N16,N17;15,15,20,0,16,16,21,21,25,0,20,20); LNAND(N2,N1;L1); LNAND(N1,N3;L2); LNAND(N4,N1;L4); LNAND(N1,N5;L5); LNAND(N6,N1;L7); LNAND(N1,N7;L8); LNAND(N8,N1;L10); LNAND(N1,N9;L11); LNAND(N10,N1;L13; LNAND(N1,N11;L14); LNAND(N12,N1;L16); LNAND(N1,N13;L17); LNAND(N14,N1;L19); LNAND(N1,N15;L20); LNAND(N16,N1;L22); LNAND(N1,N17;L23); LAND(L2,P10;L3); LAND(L5,P10;L6); LAND(L8,P10;L9); LAND(L11,P10;L12); LAND(L14,P10;L15); LAND(L17,P10;L18); LAND(L20,P10;L21); LAND(L23,P10;L24); DQFFPC(P14,P11,L1,L3;N18;10,10,20,0,16,16,10,10,20,20,10,10,25,0,20,20,10,10,20,25); DQFFPC(N18,P11,L4,L6;N19;10,10,20,0,16,16,10,10,20,20,10,10,25,0,20,20,10,10,20,25); DQFFPC(N19,P11,L7,L9;N20;10,10,20,0,16,16,10,10,20,20,10,10,25,0,20,20,10,10,20,25); DQFFPC(N20,P11,L10,L12;N21;10,10,20,0,16,16,10,10,20,20,10,10,25,0,20,20,10,10,20,25); DQFFPC(N21,P11,L13,L15;N22;10,10,20,0,16,16,10,10,20,20,10,10,25,0,20,20,10,10,20,25); DQFFPC(N22,P11,L16,L18;N23;10,10,20,0,16,16,10,10,20,20,10,10,25,0,20,20,10,10,20,25); DQFFPC(N23,P11,L19,L21;N24;10,10,20,0,16,16,10,10,20,20,10,10,25,0,20,20,10,10,20,25); DQFFPC(N24,P11,L22,L24;N25;10,10,20,0,16,16,10,10,20,20,10,10,25,0,20,20,10,10,20,25); BUF(N25;P9;20,20,34,34); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50 and 150pF :74HC604 TTL 28 LINV(P2;L1); DQFF(P4,P1;N1;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P3,P1;N2;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P6,P1;N3;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P5,P1;N4;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P8,P1;N5;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P7,P1;N6;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P10,P1;N7;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P9,P1;N8;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P26,P1;N9;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P27,P1;N10;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P24,P1;N11;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P25,P1;N12;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P22,P1;N13;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P23,P1;N14;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P20,P1;N15;10,10,19,5,25,25,10,10,19,5,25,25); DQFF(P21,P1;N16;10,10,19,5,25,25,10,10,19,5,25,25); AND(N1,L1;N17;33,33,54,54); AND(N3,L1;N19;33,33,54,54); AND(N5,L1;N21;33,33,54,54); AND(N7,L1;N23;33,33,54,54); AND(N9,L1;N25;33,33,54,54); AND(N11,L1;N27;33,33,54,54); AND(N13,L1;N29;33,33,54,54); AND(N15,L1;N31;33,33,54,54); AND(N2,P2;N18;33,33,54,54); AND(N4,P2;N20;33,33,54,54); AND(N6,P2;N22;33,33,54,54); AND(N8,P2;N24;33,33,54,54); AND(N10,P2;N26;33,33,54,54); AND(N12,P2;N28;33,33,54,54); AND(N14,P2;N30;33,33,54,54); AND(N16,P2;N32;33,33,54,54); LOR(N17,N18;L2); LOR(N19,N20;L3); LOR(N21,N22;L4); LOR(N23,N24;L5); LOR(N25,N26;L6); LOR(N27,N28;L7); LOR(N29,N30;L8); LOR(N31,N32;L9); TSB(L2,P1;P15;49,49,50,50,49,49,50,50); TSB(L3,P1;P13;49,49,50,50,49,49,50,50); TSB(L4,P1;P12;49,49,50,50,49,49,50,50); TSB(L5,P1;P11;49,49,50,50,49,49,50,50); TSB(L6,P1;P16;49,49,50,50,49,49,50,50); TSB(L7,P1;P17;49,49,50,50,49,49,50,50); TSB(L8,P1;P18;49,49,50,50,49,49,50,50); TSB(L9,P1;P19;49,49,50,50,49,49,50,50); % ;Data was taken from 1983 Motorola High Speed Cmos Logic Data book. ;Propagation Delay for Tplh and Tphl at 15pF was calculated- ;Tp = Tp(at 50pF) + 0.5(4.5)(15 - 50)pF/14 :74HC620 TTL 20 INV(P2;N1;19,19,25,25); INV(P3;N2;19,19,25,25); INV(P4;N3;19,19,25,25); INV(P5;N4;19,19,25,25); INV(P6;N5;19,19,25,25); INV(P7;N6;19,19,25,25); INV(P8;N7;19,19,25,25); INV(P9;N8;19,19,25,25); INV(P11;N9;19,19,25,25); INV(P12;N10;19,19,25,25); INV(P13;N11;19,19,25,25); INV(P14;N12;19,19,25,25); INV(P15;N13;19,19,25,25); INV(P16;N14;19,19,25,25); INV(P17;N15;19,19,25,25); INV(P18;N16;19,19,25,25); LINV(P19;L1); TSB(N1,P1;P18;38,38,38,38,38,38,38,38); TSB(N2,P1;P17;38,38,38,38,38,38,38,38); TSB(N3,P1;P16;38,38,38,38,38,38,38,38); TSB(N4,P1;P15;38,38,38,38,38,38,38,38); TSB(N5,P1;P14;38,38,38,38,38,38,38,38); TSB(N6,P1;P13;38,38,38,38,38,38,38,38); TSB(N7,P1;P12;38,38,38,38,38,38,38,38); TSB(N8,P1;P11;38,38,38,38,38,38,38,38); TSB(N9,L1;P9;38,38,38,38,38,38,38,38); TSB(N10,L1;P8;38,38,38,38,38,38,38,38); TSB(N11,L1;P7;38,38,38,38,38,38,38,38); TSB(N12,L1;P6;38,38,38,38,38,38,38,38); TSB(N13,L1;P5;38,38,38,38,38,38,38,38); TSB(N14,L1;P4;38,38,38,38,38,38,38,38); TSB(N15,L1;P3;38,38,38,38,38,38,38,38); TSB(N16,L1;P2;38,38,38,38,38,38,38,38); % ;Data taken from 1986 Motorola High Speed Cmos Logic ;Data book. ;Delays for 15pF were calculated as follows- ;Tp = Tp(at 50pF) + 0.5(4.5V)(15 - 50)pF/14 :74HC623 TTL 20 LINV(P19;L1); BUF(P2;N1;19,19,25,25); BUF(P3;N2;19,19,25,25); BUF(P4;N3;19,19,25,25); BUF(P5;N4;19,19,25,25); BUF(P6;N5;19,19,25,25); BUF(P7;N6;19,19,25,25); BUF(P8;N7;19,19,25,25); BUF(P9;N8;19,19,25,25); BUF(P11;N9;19,19,25,25); BUF(P12;N10;19,19,25,25); BUF(P13;N11;19,19,25,25); BUF(P14;N12;19,19,25,25); BUF(P15;N13;19,19,25,25); BUF(P16;N14;19,19,25,25); BUF(P17;N15;19,19,25,25); BUF(P18;N16;19,19,25,25); TSB(N1,P1;P18;38,38,38,38,38,38,38,38); TSB(N2,P1;P17;38,38,38,38,38,38,38,38); TSB(N3,P1;P16;38,38,38,38,38,38,38,38); TSB(N4,P1;P15;38,38,38,38,38,38,38,38); TSB(N5,P1;P14;38,38,38,38,38,38,38,38); TSB(N6,P1;P13;38,38,38,38,38,38,38,38); TSB(N7,P1;P12;38,38,38,38,38,38,38,38); TSB(N8,P1;P11;38,38,38,38,38,38,38,38); TSB(N9,L1;P9;38,38,38,38,38,38,38,38); TSB(N10,L1;P8;38,38,38,38,38,38,38,38); TSB(N11,L1;P7;38,38,38,38,38,38,38,38); TSB(N12,L1;P6;38,38,38,38,38,38,38,38); TSB(N13,L1;P5;38,38,38,38,38,38,38,38); TSB(N14,L1;P4;38,38,38,38,38,38,38,38); TSB(N15,L1;P3;38,38,38,38,38,38,38,38); TSB(N16,L1;P2;38,38,38,38,38,38,38,38); % :74HC640 TTL 20 LINV(P19;L1); LINV(P1;L2); LAND(L1,P1;L4); LAND(L1,L2;L3); INV(P2;N1;17,17,22,22); INV(P3;N2;17,17,22,22); INV(P4;N3;17,17,22,22); INV(P5;N4;17,17,22,22); INV(P6;N5;17,17,22,22); INV(P7;N6;17,17,22,22); INV(P8;N7;17,17,22,22); INV(P9;N8;17,17,22,22); INV(P11;N9;17,17,22,22) INV(P12;N10;17,17,22,22); INV(P13;N11;17,17,22,22) INV(P14;N12;17,17,22,22) INV(P15;N13;17,17,22,22) INV(P16;N14;17,17,22,22) INV(P17;N15;17,17,22,22) INV(P18;N16;17,17,22,22) TSB(N1,L4;P18;56,56,52,52,56,56,52,52); TSB(N2,L4;P17;56,56,52,52,56,56,52,52); TSB(N3,L4;P16;56,56,52,52,56,56,52,52); TSB(N4,L4;P15;56,56,52,52,56,56,52,52); TSB(N5,L4;P14;56,56,52,52,56,56,52,52); TSB(N6,L4;P13;56,56,52,52,56,56,52,52); TSB(N7,L4;P12;56,56,52,52,56,56,52,52); TSB(N8,L4;P11;56,56,52,52,56,56,52,52); TSB(N9,L3;P9;56,56,52,52,56,56,52,52); TSB(N10,L3;P8;56,56,52,52,56,56,52,52); TSB(N11,L3;P7;56,56,52,52,56,56,52,52); TSB(N12,L3;P6;56,56,52,52,56,56,52,52); TSB(N13,L3;P5;56,56,52,52,56,56,52,52); TSB(N14,L3;P4;56,56,52,52,56,56,52,52); TSB(N15,L3;P3;56,56,52,52,56,56,52,52); TSB(N16,L3;P2;56,56,52,52,56,56,52,52); % :74HC640A TTL 20 LINV(P19;L1); LINV(P1;L2); LAND(L1,P1;L4); LAND(L1,L2;L3); INV(P2;N1;17,17,22,22); INV(P3;N2;17,17,22,22); INV(P4;N3;17,17,22,22); INV(P5;N4;17,17,22,22); INV(P6;N5;17,17,22,22); INV(P7;N6;17,17,22,22); INV(P8;N7;17,17,22,22); INV(P9;N8;17,17,22,22); INV(P11;N9;17,17,22,22) INV(P12;N10;17,17,22,22); INV(P13;N11;17,17,22,22) INV(P14;N12;17,17,22,22) INV(P15;N13;17,17,22,22) INV(P16;N14;17,17,22,22) INV(P17;N15;17,17,22,22) INV(P18;N16;17,17,22,22) TSB(N1,L4;P18;56,56,52,52,56,56,52,52); TSB(N2,L4;P17;56,56,52,52,56,56,52,52); TSB(N3,L4;P16;56,56,52,52,56,56,52,52); TSB(N4,L4;P15;56,56,52,52,56,56,52,52); TSB(N5,L4;P14;56,56,52,52,56,56,52,52); TSB(N6,L4;P13;56,56,52,52,56,56,52,52); TSB(N7,L4;P12;56,56,52,52,56,56,52,52); TSB(N8,L4;P11;56,56,52,52,56,56,52,52); TSB(N9,L3;P9;56,56,52,52,56,56,52,52); TSB(N10,L3;P8;56,56,52,52,56,56,52,52); TSB(N11,L3;P7;56,56,52,52,56,56,52,52); TSB(N12,L3;P6;56,56,52,52,56,56,52,52); TSB(N13,L3;P5;56,56,52,52,56,56,52,52); TSB(N14,L3;P4;56,56,52,52,56,56,52,52); TSB(N15,L3;P3;56,56,52,52,56,56,52,52); TSB(N16,L3;P2;56,56,52,52,56,56,52,52); % :74HC643 TTL 20 LINV(P19;L1); LINV(P1;L2); LAND(L1,L2;L3); LAND(L1,P1;L4); INV(P2;N1;17,17,22,22); INV(P3;N2;17,17,22,22); INV(P4;N3;17,17,22,22); INV(P5;N4;17,17,22,22); INV(P6;N5;17,17,22,22); INV(P7;N6;17,17,22,22); INV(P8;N7;17,17,22,22); INV(P9;N8;17,17,22,22); BUF(P11;N9;17,17,22,22); BUF(P12;N10;17,17,22,22); BUF(P13;N11;17,17,22,22); BUF(P14;N12;17,17,22,22); BUF(P15;N13;17,17,22,22); BUF(P16;N14;17,17,22,22); BUF(P17;N15;17,17,22,22); BUF(P18;N16;17,17,22,22); TSB(N1,L4;P18;56,56,52,52,56,56,52,52); TSB(N2,L4;P17;56,56,52,52,56,56,52,52); TSB(N3,L4;P16;56,56,52,52,56,56,52,52); TSB(N4,L4;P15;56,56,52,52,56,56,52,52); TSB(N5,L4;P14;56,56,52,52,56,56,52,52); TSB(N6,L4;P13;56,56,52,52,56,56,52,52); TSB(N7,L4;P12;56,56,52,52,56,56,52,52); TSB(N8,L4;P11;56,56,52,52,56,56,52,52); TSB(N9,L3;P9;56,56,52,52,56,56,52,52); TSB(N10,L3;P8;56,56,52,52,56,56,52,52); TSB(N11,L3;P7;56,56,52,52,56,56,52,52); TSB(N12,L3;P6;56,56,52,52,56,56,52,52); TSB(N13,L3;P5;56,56,52,52,56,56,52,52); TSB(N14,L3;P4;56,56,52,52,56,56,52,52); TSB(N15,L3;P3;56,56,52,52,56,56,52,52); TSB(N16,L3;P2;56,56,52,52,56,56,52,52); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50pF and 150pF :74HC645 TTL 20 LINV(P19;L1); LINV(P1;L2); LAND(L1,L2;L3); LAND(L1,P1;L4); BUF(P2;N1;26,26,34,34); BUF(P3;N2;26,26,34,34); BUF(P4;N3;26,26,34,34); BUF(P5;N4;26,26,34,34); BUF(P6;N5;26,26,34,34); BUF(P7;N6;26,26,34,34); BUF(P8;N7;26,26,34,34); BUF(P9;N8;26,26,34,34); BUF(P11;N9;26,26,34,34); BUF(P12;N10;26,26,34,34); BUF(P13;N11;26,26,34,34); BUF(P14;N12;26,26,34,34); BUF(P15;N13;26,26,34,34); BUF(P16;N14;26,26,34,34); BUF(P17;N15;26,26,34,34); BUF(P18;N16;26,26,34,34); TSB(N1,L4;P18;58,58,50,50,58,58,50,50); TSB(N2,L4;P17;58,58,50,50,58,58,50,50); TSB(N3,L4;P16;58,58,50,50,58,58,50,50); TSB(N4,L4;P15;58,58,50,50,58,58,50,50); TSB(N5,L4;P14;58,58,50,50,58,58,50,50); TSB(N6,L4;P13;58,58,50,50,58,58,50,50); TSB(N7,L4;P12;58,58,50,50,58,58,50,50); TSB(N8,L4;P11;58,58,50,50,58,58,50,50); TSB(N9,L3;P9;58,58,50,50,58,58,50,50); TSB(N10,L3;P8;58,58,50,50,58,58,50,50); TSB(N11,L3;P7;58,58,50,50,58,58,50,50); TSB(N12,L3;P6;58,58,50,50,58,58,50,50); TSB(N13,L3;P5;58,58,50,50,58,58,50,50); TSB(N14,L3;P4;58,58,50,50,58,58,50,50); TSB(N15,L3;P3;58,58,50,50,58,58,50,50); TSB(N16,L3;P2;58,58,50,50,58,58,50,50); % ;Delays are given for 50 and 150pF :74HC646 TTL 24 INV(P22;N1;35,35,35,35); INV(P2;N2;35,35,35,35); BUF(P22;N3;35,35,35,35); BUF(P2;N4;35,35,35,35); LNOR(P21,P3;L33); LINV(P21;L34); LAND(L34,P3;L35); LAND(N3,N5;L1); LAND(N1,P20;L2); LAND(N3,N7;L3); LAND(N1,P19;L4); LAND(N3,N9;L5); LAND(N1,P18;L6); LAND(N3,N11;L7); LAND(N1,P17;L8); LAND(N3,N13;L9); LAND(N1,P16;L10); LAND(N3,N15;L11); LAND(N1,P15;L12); LAND(N3,N17;L13); LAND(N1,P14;L14); LAND(N3,N19;L15); LAND(N1,P13;L16); LAND(N4,N6;L17); LAND(N2,P4;L18); LAND(N4,N8;L19); LAND(N2,P5;L20); LAND(N4,N10;L21); LAND(N2,P6;L22); LAND(N4,N12;L23); LAND(N2,P7;L24); LAND(N4,N14;L25); LAND(N2,P8;L26); LAND(N4,N16;L27); LAND(N2,P9;L28); LAND(N4,N18;L29); LAND(N2,P10;L30); LAND(N4,N20;L31); LAND(N2,P11;L32); DQFF(P20,P23;N5;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P19,P23;N7;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P18,P23;N9;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P17,P23;N11;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P16,P23;N13;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P15,P23;N15;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P14,P23;N17;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P13,P23;N19;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P4,P1;N6;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P5,P1;N8;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P6,P1;N10;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P7,P1;N12;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P8,P1;N14;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P9,P1;N16;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P10,P1;N18;18,18,25,0,20,20,18,18,25,0,20,20); DQFF(P11,P1;N20;18,18,25,0,20,20,18,18,25,0,20,20); OR(L1,L2;N21;37,37,50,50); OR(L3,L4;N22;37,37,50,50); OR(L5,L6;N23;37,37,50,50); OR(L7,L8;N24;37,37,50,50); OR(L9,L10;N25;37,37,50,50); OR(L11,L12;N26;37,37,50,50); OR(L13,L14;N27;37,37,50,50); OR(L15,L16;N28;37,37,50,50); OR(L17,L18;N29;37,37,50,50); OR(L19,L20;N30;37,37,50,50); OR(L21,L22;N31;37,37,50,50); OR(L23,L24;N32;37,37,50,50); OR(L25,L26;N33;37,37,50,50); OR(L27,L28;N34;37,37,50,50); OR(L29,L30;N35;37,37,50,50); OR(L31,L32;N36;37,37,50,50); TSB(N21,L33;P4;44,44,44,44,44,44,44,44); TSB(N22,L33;P5;44,44,44,44,44,44,44,44); TSB(N23,L33;P6;44,44,44,44,44,44,44,44); TSB(N24,L33;P7;44,44,44,44,44,44,44,44); TSB(N25,L33;P8;44,44,44,44,44,44,44,44); TSB(N26,L33;P9;44,44,44,44,44,44,44,44); TSB(N27,L33;P10;44,44,44,44,44,44,44,44); TSB(N28,L33;P11;44,44,44,44,44,44,44,44); TSB(N29,L35;P20;44,44,44,44,44,44,44,44); TSB(N30,L35;P19;44,44,44,44,44,44,44,44); TSB(N31,L35;P18;44,44,44,44,44,44,44,44); TSB(N32,L35;P17;44,44,44,44,44,44,44,44); TSB(N33,L35;P16;44,44,44,44,44,44,44,44); TSB(N34,L35;P15;44,44,44,44,44,44,44,44); TSB(N35,L35;P14;44,44,44,44,44,44,44,44); TSB(N36,L35;P13;44,44,44,44,44,44,44,44); % ;Delays are given for 50 and 150pF :74HC648 TTL 24 INV(P22;N1;35,25,35,25); INV(P2;N2;35,25,35,25); BUF(P22;N3;35,25,35,25); BUF(P2;N4;35,25,35,25); LNOR(P21,P3;L33); LINV(P21;L34); LAND(L34,P3;L35); LAND(N3,N5;L1); LAND(N1,P20;L2); LAND(N3,N7;L3); LAND(N1,P19;L4); LAND(N3,N9;L5); LAND(N1,P18;L6); LAND(N3,N11;L7); LAND(N1,P17;L8); LAND(N3,N13;L9); LAND(N1,P16;L10); LAND(N3,N15;L11); LAND(N1,P15;L12); LAND(N3,N17;L13); LAND(N1,P14;L14); LAND(N3,N19;L15); LAND(N1,P13;L16); LAND(N4,N6;L17); LAND(N2,P4;L18); LAND(N4,N8;L19); LAND(N2,P5;L20); LAND(N4,N10;L21); LAND(N2,P6;L22); LAND(N4,N12;L23); LAND(N2,P7;L24); LAND(N4,N14;L25); LAND(N2,P8;L26); LAND(N4,N16;L27); LAND(N2,P9;L28); LAND(N4,N18;L29); LAND(N2,P10;L30); LAND(N4,N20;L31); LAND(N2,P11;L32); DQFF(P20,P23;N5;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P19,P23;N7;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P18,P23;N9;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P17,P23;N11;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P16,P23;N13;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P15,P23;N15;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P14,P23;N17;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P13,P23;N19;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P4,P1;N6;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P5,P1;N8;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P6,P1;N10;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P7,P1;N12;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P8,P1;N14;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P9,P1;N16;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P10,P1;N18;18,15,25,0,20,20,18,15,25,0,20,20); DQFF(P11,P1;N20;18,15,25,0,20,20,18,15,25,0,20,20); NOR(L1,L2;N21;25,50,25,50); NOR(L3,L4;N22;25,50,25,50); NOR(L5,L6;N23;25,50,25,50); NOR(L7,L8;N24;25,50,25,50); NOR(L9,L10;N25;25,50,25,50); NOR(L11,L12;N26;25,50,25,50); NOR(L13,L14;N27;25,50,25,50); NOR(L15,L16;N28;25,50,25,50); NOR(L17,L18;N29;25,50,25,50); NOR(L19,L20;N30;25,50,25,50); NOR(L21,L22;N31;25,50,25,50); NOR(L23,L24;N32;25,50,25,50); NOR(L25,L26;N33;25,50,25,50); NOR(L27,L28;N34;25,50,25,50); NOR(L29,L30;N35;25,50,25,50); NOR(L31,L32;N36;25,50,25,50); TSB(N21,L33;P4;33,33,30,30,33,33,30,30); TSB(N22,L33;P5;33,33,30,30,33,33,30,30); TSB(N23,L33;P6;33,33,30,30,33,33,30,30); TSB(N24,L33;P7;33,33,30,30,33,33,30,30); TSB(N25,L33;P8;33,33,30,30,33,33,30,30); TSB(N26,L33;P9;33,33,30,30,33,33,30,30); TSB(N27,L33;P10;33,33,30,30,33,33,30,30); TSB(N28,L33;P11;33,33,30,30,33,33,30,30); TSB(N29,L35;P20;33,33,30,30,33,33,30,30); TSB(N30,L35;P19;33,33,30,30,33,33,30,30); TSB(N31,L35;P18;33,33,30,30,33,33,30,30); TSB(N32,L35;P17;33,33,30,30,33,33,30,30); TSB(N33,L35;P16;33,33,30,30,33,33,30,30); TSB(N34,L35;P15;33,33,30,30,33,33,30,30); TSB(N35,L35;P14;33,33,30,30,33,33,30,30); TSB(N36,L35;P13;33,33,30,30,33,33,30,30); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC651 TTL 24 INV(P22;N1;14,14,14,14); INV(P2;N2;14,14,14,14); BUF(P22;N3;14,14,14,14); BUF(P2;N4;14,14,14,14); LINV(P21;L33); LAND(N3,N5;L1); LAND(N1,P20;L2); LAND(N3,N7;L3); LAND(N1,P19;L4); LAND(N3,N9;L5); LAND(N1,P18;L6); LAND(N3,N11;L7); LAND(N1,P17;L8); LAND(N3,N13;L9); LAND(N1,P16;L10); LAND(N3,N15;L11); LAND(N1,P15;L12); LAND(N3,N17;L13); LAND(N1,P14;L14); LAND(N3,N19;L15); LAND(N1,P13;L16); LAND(N4,N6;L17); LAND(N2,P4;L18); LAND(N4,N8;L19); LAND(N2,P5;L20); LAND(N4,N10;L21); LAND(N2,P6;L22); LAND(N4,N12;L23); LAND(N2,P7;L24); LAND(N4,N14;L25); LAND(N2,P8;L26); LAND(N4,N16;L27); LAND(N2,P9;L28); LAND(N4,N18;L29); LAND(N2,P10;L30); LAND(N4,N20;L31); LAND(N2,P11;L32); DQFF(P20,P23;N5;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P19,P23;N7;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P18,P23;N9;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P17,P23;N11;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P16,P23;N13;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P15,P23;N15;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P14,P23;N17;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P13,P23;N19;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P4,P1;N6;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P5,P1;N8;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P6,P1;N10;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P7,P1;N12;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P8,P1;N14;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P9,P1;N16;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P10,P1;N18;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P11,P1;N20;11,11,25,5,19,19,11,11,25,5,19,19); NOR(L1,L2;N21;24,24,34,34); NOR(L3,L4;N22;24,24,34,34); NOR(L5,L6;N23;24,24,34,34); NOR(L7,L8;N24;24,24,34,34); NOR(L9,L10;N25;24,24,34,34); NOR(L11,L12;N26;24,24,34,34); NOR(L13,L14;N27;24,24,34,34); NOR(L15,L16;N28;24,24,34,34); NOR(L17,L18;N29;24,24,34,34); NOR(L19,L20;N30;24,24,34,34); NOR(L21,L22;N31;24,24,34,34); NOR(L23,L24;N32;24,24,34,34); NOR(L25,L26;N33;24,24,34,34); NOR(L27,L28;N34;24,24,34,34); NOR(L29,L30;N35;24,24,34,34); NOR(L31,L32;N36;24,24,34,34); TSB(N21,L33;P4;61,61,61,61,61,61,61,61); TSB(N22,L33;P5;61,61,61,61,61,61,61,61); TSB(N23,L33;P6;61,61,61,61,61,61,61,61); TSB(N24,L33;P7;61,61,61,61,61,61,61,61); TSB(N25,L33;P8;61,61,61,61,61,61,61,61); TSB(N26,L33;P9;61,61,61,61,61,61,61,61); TSB(N27,L33;P10;61,61,61,61,61,61,61,61); TSB(N28,L33;P11;61,61,61,61,61,61,61,61); TSB(N29,P3;P20;61,61,61,61,61,61,61,61); TSB(N30,P3;P19;61,61,61,61,61,61,61,61); TSB(N31,P3;P18;61,61,61,61,61,61,61,61); TSB(N32,P3;P17;61,61,61,61,61,61,61,61); TSB(N33,P3;P16;61,61,61,61,61,61,61,61); TSB(N34,P3;P15;61,61,61,61,61,61,61,61); TSB(N35,P3;P14;61,61,61,61,61,61,61,61); TSB(N36,P3;P13;61,61,61,61,61,61,61,61); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC652 TTL 24 INV(P22;N1;14,14,14,14); INV(P2;N2;14,14,14,14); BUF(P22;N3;14,14,14,14); BUF(P2;N4;14,14,14,14); LINV(P21;L33); LAND(N3,N5;L1); LAND(N1,P20;L2); LAND(N3,N7;L3); LAND(N1,P19;L4); LAND(N3,N9;L5); LAND(N1,P18;L6); LAND(N3,N11;L7); LAND(N1,P17;L8); LAND(N3,N13;L9); LAND(N1,P16;L10); LAND(N3,N15;L11); LAND(N1,P15;L12); LAND(N3,N17;L13); LAND(N1,P14;L14); LAND(N3,N19;L15); LAND(N1,P13;L16); LAND(N4,N6;L17); LAND(N2,P4;L18); LAND(N4,N8;L19); LAND(N2,P5;L20); LAND(N4,N10;L21); LAND(N2,P6;L22); LAND(N4,N12;L23); LAND(N2,P7;L24); LAND(N4,N14;L25); LAND(N2,P8;L26); LAND(N4,N16;L27); LAND(N2,P9;L28); LAND(N4,N18;L29); LAND(N2,P10;L30); LAND(N4,N20;L31); LAND(N2,P11;L32); DQFF(P20,P23;N5;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P19,P23;N7;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P18,P23;N9;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P17,P23;N11;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P16,P23;N13;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P15,P23;N15;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P14,P23;N17;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P13,P23;N19;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P4,P1;N6;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P5,P1;N8;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P6,P1;N10;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P7,P1;N12;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P8,P1;N14;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P9,P1;N16;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P10,P1;N18;11,11,25,5,19,19,11,11,25,5,19,19); DQFF(P11,P1;N20;11,11,25,5,19,19,11,11,25,5,19,19); OR(L1,L2;N21;24,24,34,34); OR(L3,L4;N22;24,24,34,34); OR(L5,L6;N23;24,24,34,34); OR(L7,L8;N24;24,24,34,34); OR(L9,L10;N25;24,24,34,34); OR(L11,L12;N26;24,24,34,34); OR(L13,L14;N27;24,24,34,34); OR(L15,L16;N28;24,24,34,34); OR(L17,L18;N29;24,24,34,34); OR(L19,L20;N30;24,24,34,34); OR(L21,L22;N31;24,24,34,34); OR(L23,L24;N32;24,24,34,34); OR(L25,L26;N33;24,24,34,34); OR(L27,L28;N34;24,24,34,34); OR(L29,L30;N35;24,24,34,34); OR(L31,L32;N36;24,24,34,34); TSB(N21,L33;P4;61,61,61,61,61,61,61,61); TSB(N22,L33;P5;61,61,61,61,61,61,61,61); TSB(N23,L33;P6;61,61,61,61,61,61,61,61); TSB(N24,L33;P7;61,61,61,61,61,61,61,61); TSB(N25,L33;P8;61,61,61,61,61,61,61,61); TSB(N26,L33;P9;61,61,61,61,61,61,61,61); TSB(N27,L33;P10;61,61,61,61,61,61,61,61); TSB(N28,L33;P11;61,61,61,61,61,61,61,61); TSB(N29,P3;P20;61,61,61,61,61,61,61,61); TSB(N30,P3;P19;61,61,61,61,61,61,61,61); TSB(N31,P3;P18;61,61,61,61,61,61,61,61); TSB(N32,P3;P17;61,61,61,61,61,61,61,61); TSB(N33,P3;P16;61,61,61,61,61,61,61,61); TSB(N34,P3;P15;61,61,61,61,61,61,61,61); TSB(N35,P3;P14;61,61,61,61,61,61,61,61); TSB(N36,P3;P13;61,61,61,61,61,61,61,61); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. ;Delays for G~ to Y were not modeled precisely. :74HC677 TTL 24 INV(P18;N1;119,119,119,119); INV(P19;N2;119,119,119,119); INV(P20;N3;119,119,119,119); INV(P21;N4;119,119,119,119); BUF(P21;N5;119,119,119,119); LINV(P23;L42); LNAND(N1,N2,N3,N4;L1); LNAND(N2,N3,N4;L2); LAND(N1,N3,N4;L3); LINV(L2;L4); LNAND(N3,N4;L5); LAND(N1,N2,N4;L6); LINV(L5;L7); LAND(N2,N4;L8); LAND(N1,N4;L9); LAND(N1,N2,N3;L10); LAND(N2,N3;L11); LAND(N1,N3;L12); LAND(N1,N2;L13); LNOR(L3,L4;L14); LNOR(L6,L7;L15); LNOR(L7,L8;L16); LNOR(L8,L7,L9;L17); LNOR(N4,L10;L18); LNOR(N4,L11;L19); LNOR(L11,N4,L12;L20); LNOR(N3,N4;L21); LNOR(N4,N3,L13;L22); LNOR(N2,N3,N4;L23); LNOR(N1,N2,N3,N4;L24); LXOR(L1,P1;L25); LXOR(L2,P2;L26); LXOR(L14,P3;L27); LXOR(L5,P4;L28); LXOR(L15,P5;L29); LXOR(L16,P6;L30); LXOR(L17,P7;L31); LXOR(N5,P8;L32); LXOR(L18,P9;L33); LXOR(L19,P10;L34); LXOR(L20,P11;L35); LXOR(L21,P13;L36); LXOR(L22,P14;L37); LXOR(L23,P15;L38); LXOR(L24,P16;L39); LAND(L25,L26,L27,L28,L29,L30,L31,L32;L40); LAND(L33,L34,L35,L36,L37,L38,L39,P17;L41); NAND(L40,L41,L42;P22;27,27,37,37); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated ;Setup Time for P0 thru P3 before C was not modeled precisely. :74HC678 TTL 24 INV(P18;N1;112,112,112,112); INV(P19;N2;112,112,112,112); INV(P20;N3;112,112,112,112); INV(P21;N4;112,112,112,112); BUF(P21;N5;112,112,112,112); LNAND(N1,N2,N3,N4;L1); LNAND(N2,N3,N4;L2); LAND(N1,N3,N4;L3); LINV(L2;L4); LNAND(N3,N4;L5); LAND(N1,N2,N4;L6); LINV(L5;L7); LAND(N2,N4;L8); LAND(N1,N4;L9); LAND(N1,N2,N3;L10); LAND(N2,N3;L11); LAND(N1,N3;L12); LAND(N1,N2;L13); LNOR(L3,L4;L14); LNOR(L6,L7;L15); LNOR(L7,L8;L16); LNOR(L8,L7,L9;L17); LNOR(N4,L10;L18); LNOR(N4,L11;L19); LNOR(L11,N4,L12;L20); LNOR(N3,N4;L21); LNOR(N4,N3,L13;L22); LNOR(N2,N3,N4;L23); LNOR(N1,N2,N3,N4;L24); LXOR(L1,P1;L25); LXOR(L2,P2;L26); LXOR(L14,P3;L27); LXOR(L5,P4;L28); LXOR(L15,P5;L29); LXOR(L16,P6;L30); LXOR(L17,P7;L31); LXOR(N5,P8;L32); LXOR(L18,P9;L33); LXOR(L19,P10;L34); LXOR(L20,P11;L35); LXOR(L21,P13;L36); LXOR(L22,P14;L37); LXOR(L23,P15;L38); LXOR(L24,P16;L39); LAND(L25,L26,L27,L28,L29,L30,L31,L32;L40); LAND(L33,L34,L35,L36,L37,L38,L39,P17;L41); LNAND(L40,L41;L42); DLATCH(L42,P23;P22;34,34,27,27,25,5,19,44,44,37,37,25,5,19); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC679 TTL 20 INV(P14;N1;35,35,35,35); INV(P15;N2;35,35,35,35); INV(P16;N3;35,35,35,35); INV(P17;N4;35,35,35,35); BUF(P17;N5;35,35,35,35); LINV(P19;L19); LNAND(N1,N2,N3,N4;L1); LNAND(N2,N3,N4;L2); LAND(N1,N3,N4;L3); LINV(L2;L4); LNAND(N3,N4;L5); LAND(N1,N2,N4;L6); LINV(L5;L7); LAND(N2,N4;L8); LAND(N1,N4;L9); LAND(N1,N2;L10); LNOR(L3,L4;L11); LNOR(L6,L7;L12); LNOR(L7,L8;L13); LNOR(L8,L7,L9;L14); LNOR(N4,L10;L15); LNOR(N4,N2;L16); LNOR(N1,N2,N4;L17); LNOR(N3,N4;L18); XOR(L1,P1;N7;9,9,9,9); XOR(L2,P2;N8;9,9,9,9); XOR(L11,P3;N9;9,9,9,9); XOR(L5,P4;N10;9,9,9,9); XOR(L12,P5;N11;9,9,9,9); XOR(L13,P6;N12;9,9,9,9); XOR(L14,P7;N13;9,9,9,9); XOR(N5,P8;N14;9,9,9,9); XOR(L15,P9;N15;9,9,9,9); XOR(L16,P11;N16;9,9,9,9); XOR(L17,P12;N17;9,9,9,9); XOR(L18,P13;N18;9,9,9,9); LAND(N7,N8,N9,N10,N11,N12;L20); LAND(N13,N14,N15,N16,N17,N18;L21); NAND(L20,L21,L19;P18;21,21,31,31); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated ;Setup time of P before C was not modeled precisely. :74HC680 TTL 20 INV(P14;N1;35,35,35,35); INV(P15;N2;35,35,35,35); INV(P16;N3;35,35,35,35); INV(P17;N4;35,35,35,35); BUF(P17;N5;35,35,35,35); LNAND(N1,N2,N3,N4;L1); LNAND(N2,N3,N4;L2); LAND(N1,N3,N4;L3); LINV(L2;L4); LNAND(N3,N4;L5); LAND(N1,N2,N4;L6); LINV(L5;L7); LAND(N2,N4;L8); LAND(N1,N4;L9); LAND(N1,N2;L10); LNOR(L3,L4;L11); LNOR(L6,L7;L12); LNOR(L7,L8;L13); LNOR(L8,L7,L9;L14); LNOR(N4,L10;L15); LNOR(N4,N2;L16); LNOR(N1,N2,N4;L17); LNOR(N3,N4;L18); LXOR(L1,P1;L19); LXOR(L2,P2;L20); LXOR(L11,P3;L21); LXOR(L5,P4;L22); LXOR(L12,P5;L23); LXOR(L13,P6;L24); LXOR(L14,P7;L25); LXOR(N5,P8;L26); LXOR(L15,P9;L27); LXOR(L16,P11;L28); LXOR(L17,P12;L29); LXOR(L18,P13;L30); LAND(L19,L20,L21,L22,L23,L24;L31); LAND(L25,L26,L27,L28,L29,L30;L32); LNAND(L31,L32;L33); DLATCH(L33,P19;P18;30,30,21,21,25,5,19,40,40,31,31,25,5,19); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC682 TTL 20 LXNOR(P17,P18;L1); LXNOR(P15,P16;L2); LXNOR(P13,P14;L3); LXNOR(P11,P12;L4); LXNOR(P8,P9;L5); LXNOR(P6,P7;L6); LXNOR(P4,P5;L7); LXNOR(P2,P3;L8); LINV(P3;L9); LINV(P5;L10); LINV(P7;L11); LINV(P9;L12); LINV(P12;L13); LINV(P14;L14); LINV(P16;L15); LINV(P18;L16); LAND(L7,L6,L5,L4,L3,L2,L1,P2,L9;L17); LAND(L6,L5,L4,L3,L2,L1,P4,L10;L18); LAND(L5,L4,L3,L2,L1,P6,L11;L19); LAND(L4,L3,L2,L1,P8,L12;L20); LAND(L3,L2,L1,P11,L13;L21) LAND(L2,L1,P13,L14;L22); LAND(L1,P15,L15;L23); LAND(P17,L16;L24); NAND(L1,L2,L3,L4,L5,L6,L7,L8;P19;59,59,69,69); NOR(L17,L18,L19,L20,L21,L22,L23,L24;P1;59,59,69,69); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated. :74HC684 TTL 20 LXNOR(P17,P18;L1); LXNOR(P15,P16;L2); LXNOR(P13,P14;L3); LXNOR(P11,P12;L4); LXNOR(P8,P9;L5); LXNOR(P6,P7;L6); LXNOR(P4,P5;L7); LXNOR(P2,P3;L8); LINV(P3;L9); LINV(P5;L10); LINV(P7;L11); LINV(P9;L12); LINV(P12;L13); LINV(P14;L14); LINV(P16;L15); LINV(P18;L16); LAND(L7,L6,L5,L4,L3,L2,L1,P2,L9;L17); LAND(L6,L5,L4,L3,L2,L1,P4,L10;L18); LAND(L5,L4,L3,L2,L1,P6,L11;L19); LAND(L4,L3,L2,L1,P8,L12;L20); LAND(L3,L2,L1,P11,L13;L21) LAND(L2,L1,P13,L14;L22); LAND(L1,P15,L15;L23); LAND(P17,L16;L24); NAND(L1,L2,L3,L4,L5,L6,L7,L8;P19;59,59,69,69); NOR(L17,L18,L19,L20,L21,L22,L23,L24;P1;59,59,69,69); % :74HC688 TTL 20 XNOR(P18,P17;N1;10,10,14,14); XNOR(P16,P15;N2;10,10,14,14); XNOR(P14,P13;N3;10,10,14,14); XNOR(P12,P11;N4;10,10,14,14); XNOR(P9,P8;N5;10,10,14,14); XNOR(P7,P6;N6;10,10,14,14); XNOR(P5,P4;N7;10,10,14,14); XNOR(P3,P2;N8;10,10,14,14); LINV(P1;L1); NAND(N1,N2,N3,N4,N5,N6,N7,N8,L1;P19;20,20,30,30); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50 pF and 150pF :74HC804 TTL 20 NAND(P1,P2;P3;25,25,46,46); NAND(P4,P5;P6;25,25,46,46); NAND(P7,P8;P9;25,25,46,46); NAND(P13,P12;P11;25,25,46,46); NAND(P16,P15;P14;25,25,46,46); NAND(P19,P18;P17;25,25,46,46); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50pF and 150pF :74HC805 TTL 20 NOR(P1,P2;P3;24,24,45,45); NOR(P4,P5;P6;24,24,45,45); NOR(P7,P8;P9;24,24,45,45); NOR(P13,P12;P11;24,24,45,45); NOR(P16,P15;P14;24,24,45,45); NOR(P19,P18;P17;24,24,45,45); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays are given for 50pF and 150pF ;Delays for 150pF were estimated. :74HC808 TTL 20 AND(P1,P2;P3;25,25,46,46); AND(P4,P5;P6;25,25,46,46); AND(P7,P8;P9;25,25,46,46); AND(P13,P12;P11;25,25,46,46); AND(P16,P15;P14;25,25,46,46); AND(P19,P18;P17;25,25,46,46); % ;taken from 1988 TI High-Speed CMOS Logic data book. ;Delays for 15pF were extrapolated :74HC832 TTL 20 OR(P1,P2;P3;15,15,25,25); OR(P4,P5;P6;15,15,25,25); OR(P7,P8;P9;15,15,25,25); OR(P13,P12;P11;15,15,25,25); OR(P16,P15;P14;15,15,25,25); OR(P19,P18;P17;15,15,25,25); % ;taken form 1989 TI High-Speed CMOS Logic data book ;Delays for 15pF were extrapolated :74HC4078A TTL 14 LOR(P2,P3,P4,P5,P9,P10,P11,P12;L1); BUF(L1;P1;23,23,33,33); INV(L1;P13;23,23,33,33); %