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Text File | 1991-01-31 | 51.3 KB | 1,461 lines

* Sample standard device library * * Copyright 1991 by MicroSim Corporation * This is a reduced version of MicroSim's standard parts libraries. Some * components from several types of component libraries have been included * here. You are welcome to make as many copies of it as you find convenient. * * The Microsim library included with the production version of PSpice * includes over 3,500 analog devices, and over 1,500 digital devices. * * Release date: January 1991 * * It takes time for PSpice to scan a library file. To speed this up, PSpice * creates an index file, called <filename>.IND. The index file is re-created * whenever PSpice senses that the library file has changed. * The following is a summary of parts in this library: * * Part name Part type * --------- --------- * Q2N2222A NPN bipolar transistor * Q2N2907A PNP bipolar transistor * Q2N3904 NPN bipolar transistor * Q2N3906 PNP bipolar transistor * * D1N750 zener diode * MV2201 voltage variable capacitance diode * D1N4148 switching diode * MBD101 switching diode * * J2N3819 N-channel Junction field effect transistor * J2N4393 N-channel Junction field effect transistor * * LM324 linear operational amplifier * UA741 linear operational amplifier * LM111 voltage comparator * * K3019PL_3C8 ferroxcube pot magnetic core * KRM8PL_3C8 ferroxcube pot magnetic core * K502T300_3C8 ferroxcube pot magnetic core * * IRF150 N-type power MOS field effect transistor * IRF9140 P-type power MOS field effect transistor * * 7402 TTL digital 2-input NOR gate * 7404 TTL digital inverter * 7405 TTL digital inverter, open collector * 7414 TTL digital inverter, schmidt trigger * 7474 TTL digital D-type flip-flop * 74107 TTL digital JK-type flip-flop * 74393 TTL digital 4-bit binary counter * * A4N25 optocoupler * * 2N1595 silicon controlled rectifier * 2N5444 Triac * *------------------------------------------------------------------------------- * Library of bipolar transistor model parameters * * This is a reduced version of MicroSim's bipolar transistor model library. * You are welcome to make as many copies of it as you find convenient. * * The parameters in this model library were derived from the data sheets for * each part. Each part was characterize using the Parts option. * Devices can also be characterized without Parts as follows: * * NE, NC Normally set to 4 * BF, ISE, IKF These are adjusted to give the nominal beta vs. * collector current curve. BF controls the mid- * range beta. ISE/IS controls the low-current * roll-off. IKF controls the high-current rolloff. * ISC Set to ISE. * IS, RB, RE, RC These are adjusted to give the nominal VBE vs. * IC and VCE vs. IC curves in saturation. IS * controls the low-current value of VBE. RB+RE * controls the rise of VBE with IC. RE+RC controls * the rise of VCE with IC. RC is normally set to 0. * VAF Using the voltages specified on the data sheet * VAF is set to give the nominal output impedance * (RO on the .OP printout) on the data sheet. * CJC, CJE Using the voltages specified on the data sheet * CJC and CJE are set to give the nominal input * and output capacitances (CPI and CMU on the .OP * printout; Cibo and Cobo on the data sheet). * TF Using the voltages and currents specified on the * data sheet for FT, TF is adjusted to produce the * nominal value of FT on the .OP printout. * TR Using the rise and fall time circuits on the * data sheet, TR (and if necessary TF) are adjusted * to give a transient analysis which shows the * nominal values of the turn-on delay, rise time, * storage time, and fall time. * KF, AF These parameters are only set if the data sheet has * a spec for noise. Then, AF is set to 1 and KF * is set to produce a total noise at the collector * which is greater than the generator noise at the * collector by the rated number of decibels. * * .model Q2N2222A NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 + Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 + Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 + Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10) * National pid=19 case=TO18 * 88-09-07 bam creation .model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 + Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 + Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 + Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) * National pid=63 case=TO18 * 88-09-09 bam creation .model Q2N3904 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 + Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 + Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 + Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10) * National pid=23 case=TO92 * 88-09-08 bam creation .model Q2N3906 PNP(Is=1.41f Xti=3 Eg=1.11 Vaf=18.7 Bf=180.7 Ne=1.5 Ise=0 + Ikf=80m Xtb=1.5 Br=4.977 Nc=2 Isc=0 Ikr=0 Rc=2.5 Cjc=9.728p + Mjc=.5776 Vjc=.75 Fc=.5 Cje=8.063p Mje=.3677 Vje=.75 Tr=33.42n + Tf=179.3p Itf=.4 Vtf=4 Xtf=6 Rb=10) * National pid=66 case=TO92 * 88-09-09 bam creation *------------------------------------------------------------------------------- * Library of diode model parameters * * Copyright 1991 by MicroSim Corporation * This is a reduced version of MicroSim's diode model library. * You are welcome to make as many copies of it as you find convenient. * * The parameters in this model library were derived from the data sheets for * each part. Most parts were characterize using the Parts option. * Devices can also be characterized without Parts as follows: * IS nominal leakage current * RS for zener diodes: nominal small-signal impedance * at specified operating current * IB for zener diodes: set to nominal leakage current * IBV for zener diodes: at specified operating current * IBV is adjusted to give the rated zener voltage * * *** Zener Diodes *** * * "A" suffix zeners have the same parameters (e.g., 1N750A has the same * parameters as 1N750) * .model D1N750 D(Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 + Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=4.7 Ibv=20.245m Nbv=1.6989 + Ibvl=1.9556m Nbvl=14.976 Tbv1=-21.277u) * Motorola pid=1N750 case=DO-35 * 89-9-18 gjg * Vz = 4.7 @ 20mA, Zz = 300 @ 1mA, Zz = 12.5 @ 5mA, Zz =2.6 @ 20mA *** Voltage-variable capacitance diodes * The parameters in this model library were derived from the data sheets for * each part. Each part was characterize using the Parts option. * .model MV2201 D(Is=1.365p Rs=1 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=14.93p M=.4261 + Vj=.75 Fc=.5 Isr=16.02p Nr=2 Bv=25 Ibv=10u) * Motorola pid=MV2201 case=182-03 * 88-09-22 bam creation *** Switching Diodes *** .model D1N4148 D(Is=0.1p Rs=16 CJO=2p Tt=12n Bv=100 Ibv=0.1p) * 85-??-?? Original library .model MBD101 D(Is=192.1p Rs=.1 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=893.8f M=98.29m + Vj=.75 Fc=.5 Isr=16.91n Nr=2 Bv=5 Ibv=10u) * Motorola pid=MBD101 case=182-03 * 88-09-22 bam creation *------------------------------------------------------------------------------- * Library of junction field-effect transistor (JFET) model parameters * This is a reduced version of MicroSim's JFET model library. * You are welcome to make as many copies of it as you find convenient. * The parameters in this model library were derived from the data sheets for * each part. Each part was characterize using the Parts option. .model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 + Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7 + Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 + Af=1) * National pid=50 case=TO92 * 88-08-01 rmn BVmin=25 .model J2N4393 NJF(Beta=9.109m Betatce=-.5 Rd=1 Rs=1 Lambda=6m Vto=-1.422 + Vtotc=-2.5m Is=205.2f Isr=1.988p N=1 Nr=2 Xti=3 Alpha=20.98u + Vk=123.7 Cgd=4.57p M=.4069 Pb=1 Fc=.5 Cgs=4.06p Kf=123E-18 + Af=1) * National pid=51 case=TO18 * 88-07-13 bam BVmin=40 *------------------------------------------------------------------------------- * Library of linear IC definitions * This is a reduced version of MicroSim's linear subcircuit library. * You are welcome to make as many copies of it as you find convenient. * * The parameters in the opamp library were derived from the data sheets for * each part. The macromodel used is similar to the one described in: * * Macromodeling of Integrated Circuit Operational Amplifiers * by Graeme Boyle, Barry Cohn, Donald Pederson, and James Solomon * IEEE Journal of SoliE-State Circuits, Vol. SC-9, no. 6, Dec. 1974 * * Differences from the reference (above) occur in the output limiting stage * which was modified to reduce internally generated currents associated with * output voltage limiting, as well as short-circuit current limiting. * * The opamps are modelled at room temperature and do not track changes with * temperature. This library file contains models for nominal, not worst case, * devices. * *----------------------------------------------------------------------------- * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt LM324 1 2 3 4 5 * c1 11 12 2.887E-12 c2 6 7 30.00E-12 dc 5 53 dx de 54 5 dx dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 21.22E6 -20E6 20E6 20E6 -20E6 ga 6 0 11 12 188.5E-6 gcm 0 6 10 99 59.61E-9 iee 3 10 dc 15.09E-6 hlim 90 0 vlim 1K q1 11 2 13 qx q2 12 1 14 qx r2 6 9 100.0E3 rc1 4 11 5.305E3 rc2 4 12 5.305E3 re1 13 10 1.845E3 re2 14 10 1.845E3 ree 10 99 13.25E6 ro1 8 5 50 ro2 7 99 25 rp 3 4 9.082E3 vb 9 0 dc 0 vc 3 53 dc 1.500 ve 54 4 dc 0 vlim 7 8 dc 0 vlp 91 0 dc 40 vln 0 92 dc 40 .model dx D(Is=800.0E-18 Rs=1) .model qx PNP(Is=800.0E-18 Bf=166.7) .ends *----------------------------------------------------------------------------- * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt uA741 1 2 3 4 5 * c1 11 12 8.661E-12 c2 6 7 30.00E-12 dc 5 53 dx de 54 5 dx dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -10E6 10E6 10E6 -10E6 ga 6 0 11 12 188.5E-6 gcm 0 6 10 99 5.961E-9 iee 10 4 dc 15.16E-6 hlim 90 0 vlim 1K q1 11 2 13 qx q2 12 1 14 qx r2 6 9 100.0E3 rc1 3 11 5.305E3 rc2 3 12 5.305E3 re1 13 10 1.836E3 re2 14 10 1.836E3 ree 10 99 13.19E6 ro1 8 5 50 ro2 7 99 100 rp 3 4 18.16E3 vb 9 0 dc 0 vc 3 53 dc 1 ve 54 4 dc 1 vlim 7 8 dc 0 vlp 91 0 dc 40 vln 0 92 dc 40 .model dx D(Is=800.0E-18 Rs=1) .model qx NPN(Is=800.0E-18 Bf=93.75) .ends *----------------------------------------------------------------------------- *** Voltage comparators * The parameters in this comparator library were derived from data sheets for * each parts. The macromodel used was developed by MicroSim Corporation, and * is produced by the "Parts" option to PSpice. * * Although we do not use it, another comparator macro model is described in: * * An Integrated-Circuit Comparator Macromodel * by Ian Getreu, Andreas Hadiwidjaja, and Johan Brinch * IEEE Journal of Solid-State Circuits, Vol. SC-11, no. 6, Dec. 1976 * * This reference covers the considerations that go into duplicating the * behavior of voltage comparators. * * The comparators are modelled at room temperature. The macro model does not * track changes with temperature. This library file contains models for * nominal, not worst case, devices. * *----------------------------------------------------------------------------- * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | open collector output * | | | | | output ground * | | | | | | .subckt LM111 1 2 3 4 5 6 * f1 9 3 v1 1 iee 3 7 dc 100.0E-6 vi1 21 1 dc .45 vi2 22 2 dc .45 q1 9 21 7 qin q2 8 22 7 qin q3 9 8 4 qmo q4 8 8 4 qmi .model qin PNP(Is=800.0E-18 Bf=833.3) .model qmi NPN(Is=800.0E-18 Bf=1002) .model qmo NPN(Is=800.0E-18 Bf=1000 Cjc=1E-15 Tr=118.8E-9) e1 10 6 9 4 1 v1 10 11 dc 0 q5 5 11 6 qoc .model qoc NPN(Is=800.0E-18 Bf=34.49E3 Cjc=1E-15 Tf=364.6E-12 Tr=79.34E-9) dp 4 3 dx rp 3 4 6.122E3 .model dx D(Is=800.0E-18 Rs=1) * .ends *------------------------------------------------------------------------------- * Library of magnetic core model parameters * This is a reduced version of MicroSim's magnetic core library. * You are welcome to make as many copies of it as you find convenient. * The parameters in this model library were derived from the data sheets for * each core. The Jiles-Atherton magnetics model is described in: * * Theory of Ferromagnetic Hysteresis, by D C Jiles and D L Atherton, * Journal of Magnetism and Magnetic Materials, vol 61 (1986) pp 48-60 * * Model parameters for ferrite material (Ferroxcube 3C8) were obtained by * trial simulations, using the B-H curves from the manufacturer's catalog. * Then, the library was compiled from the data sheets for each core geometry. * Notice that only the geometric values change once a material is * characterized. * Example use: K2 L2 .99 K1409PL_3C8 * Notes: * 1) Using a K device (formerly only for mutual coupling) with a model * reference changes the meaning of the L device: the inductance value * becomes the number of turns for the winding. * 2) K devices can "get away" with specifying only one inductor, as in the * example above, to simulate power inductors. * Example circuit file: *+----------------------------------------------------------------------------- *|Demonstration of power inductor B-H curve *| *|* To view results with Probe (B-H curve): *|* 1) Add Trace for B(K1) *|* 2) set X-axis variable to H(K1) *|* *|* Probe x-axis unit is Oersted *|* Probe y-axis unit is Gauss *|* *|.tran .1 4 *|igen0 0 1 sin(0 .1amp 1Hz 0) ; Generator: starts with 0.1 amp sinewave, then *|igen1 0 1 sin(0 .1amp 1Hz 1) ; +0.1 amps, starting at 1 second *|igen2 0 1 sin(0 .2amp 1Hz 2) ; +0.2 amps, starting at 2 seconds *|igen3 0 1 sin(0 .8amp 1Hz 3) ; +0.4 amps, starting at 3 seconds *|RL 1 0 1ohm ; generator source resistance *|L1 1 0 20 ; inductor with 20 turns *|K1 L1 .9999 K528T500_3C8 ; Ferroxcube torroid core *|.model K528T500_3C8 Core(MS=420E3 ALPHA=2E-5 A=26 K=18 C=1.05 *|+ AREA=1.17 PATH=8.49) *|.options itl5=0 *|.probe *|.end *+----------------------------------------------------------------------------- *** Ferroxcube pot cores: 3C8 material .model K3019PL_3C8 Core(Ms=420E3 Alpha=2E-5 A=26 K=18 C=1.05 + Area=1.38 Path=4.52) *** Ferroxcube square cores: 3C8 material .model KRM8PL_3C8 Core(Ms=420E3 Alpha=2E-5 A=26 K=18 C=1.05 + Area=.630 Path=3.84) *** Ferroxcube toroid cores: 3C8 material .model K502T300_3C8 Core(Ms=420E3 Alpha=2E-5 A=26 K=18 C=1.05 + Area=.371 Path=7.32) *------------------------------------------------------------------------------- * Library of MOSFET model parameters (for "power" MOSFET devices) * * This is a reduced version of MicroSim's power MOSFET model library. * You are welcome to make as many copies of it as you find convenient. * * The parameters in this model library were derived from the data sheets for * each part. Each part was characterize using the Parts option. * Device can also be characterized without Parts as follows: * LEVEL Set to 3 (short-channel device). * TOX Determined from gate ratings. * L, LD, W, WD Assume L=2u. Calculate from input capacitance. * XJ, NSUB Assume usual technology. * IS, RD, RB Determined from "source-drain diode forward voltage" * specification or curve (Idr vs. Vsd). * RS Determine from Rds(on) specification. * RDS Calculated from Idss specification or curves. * VTO, UO, THETA Determined from "output characteristics" curve family * (Ids vs. Vds, stepped Vgs). * ETA, VMAX, CBS Set for null effect. * CBD, PB, MJ Determined from "capacitance vs. Vds" curves. * RG Calculate from rise/fall time specification or curves. * CGSO, CGDO Determined from gate-charge, turn-on/off delay and * rise time specifications. * * NOTE: when specifying the instance of a device in your circuit file: * * BE SURE to have the source and bulk nodes connected together, as this * is the way the real device is constructed. * * DO NOT include values for L, W, AD, AS, PD, PS, NRD, or NDS. * The PSpice default values for these parameters are taken into account * in the library model statements. Of course, you should NOT reset * the default values using the .OPTIONS statement, either. * * Example use: M17 15 23 7 7 IRF150 * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * The "power" MOSFET device models benefit from relatively complete specifi- * cation of static and dynamic characteristics by their manufacturers. The * following effects are modeled: * - DC transfer curves in forward operation, * - gate drive characteristics and switching delay, * - "on" resistance, * - reverse-mode "body-diode" operation. * * The factors not modeled include: * - maximum ratings (eg. high-voltage breakdown), * - safe operating area (eg. power dissipation), * - latch-up, * - noise. * * For high-current switching applications, we advise that you include * series inductance elements, for the source and drain, in your circuit file. * In doing so, voltage spikes due to di/dt will be modeled. According to the * 1985 International Rectifier databook, the following case styles have lead * inductance values of: * TO-204 (modified TO-3) source = 12.5nH drain = 5.0nH * TO-220 source = 7.5nH drain = 3.5-4.5nH * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * .model IRF150 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0 Vmax=0 Xj=0 + Tox=100n Uo=600 Phi=.6 Rs=1.624m Kp=20.53u W=.3 L=2u Vto=2.831 + Rd=1.031m Rds=444.4K Cbd=3.229n Pb=.8 Mj=.5 Fc=.5 Cgso=9.027n + Cgdo=1.679n Rg=13.89 Is=194E-18 N=1 Tt=288n) * Int'l Rectifier pid=IRFC150 case=TO3 * 88-08-25 bam creation .model IRF9140 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0 Vmax=0 Xj=0 + Tox=100n Uo=300 Phi=.6 Rs=70.6m Kp=10.15u W=1.9 L=2u Vto=-3.67 + Rd=60.66m Rds=444.4K Cbd=2.141n Pb=.8 Mj=.5 Fc=.5 Cgso=877.2p + Cgdo=369.3p Rg=.811 Is=52.23E-18 N=2 Tt=140n) * Int'l Rectifier pid=IRFC9140 case=TO3 * 88-08-25 bam creation *------------------------------------------------------------------------------- * Library of digital logic * Copyright 1991 by MicroSim Corporation * This is a reduced version of MicroSim's Digital components library. * You are welcome to make as many copies of it as you find convenient. * * The parameters in this model library were derived from: * * The TTL Data Book, Texas Instruments, 1985 * vol. 2 * * Each device is modeled by a subcircuit. The interface pins of the * subcircuit have the same name as the pin labels in the data book. The * general order is inputs followed by outputs, but on the more complex * devices you will have to look at the subcircuit definition. * The word "BAR" is appended to inverted inputs or outputs. * * There are two optional power supply pins for each digital subcircuit. * You do not need to specify these if you are using a 5v supply with * analog and digital ground connected. If you use another power supply * configuration, then the pins should be connected to that supply. * * The timing charactistics from the data book are included in the models, * with all data sheet effects modeled, unless noted in this file. * * If a device contains multiple, independant, identical functions, only * one is contained in the subcircuit. (e.g. the 7400 contains four two- * input NAND gates, but there is only one in the 7400 subckt.) * * The subcircuit name is the part name. Only the 74 series (not the 54 * series) is included in the library, except for a few parts which * are only made in the 54 series. (e.g. 54L00) *-------------------------------------------------------------------- * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7402 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_02 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_02 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *------------------------------------------------------------------------- * 7404 Hex Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7404 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_04 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_04 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *------------------------------------------------------------------------- * 7405 Hex Inverters with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7405 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_05 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_05 ugate ( + tplhty=40ns tplhmx=55ns + tphlty=8ns tphlmx=15ns + ) *------------------------------------------------------------------------- * 7414 Hex Schmitt-Trigger Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7414 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface U1 inv DPWR DGND + A Y + D_14 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_14 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=15ns tphlmx=22ns + ) *------------------------------------------------------------------------- * 7474 Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7474 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_74 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_74 ueff ( + twpclmn=30ns twclklmn=37ns + twclkhmn=30ns tsudclkmn=20ns + thdclkmn=5ns tppcqlhmx=25ns + tppcqhlmx=40ns tpclkqlhty=14ns + tpclkqlhmx=25ns tpclkqhlty=20ns + tpclkqhlmx=40ns + ) *------------------------------------------------------------------------- * 74107 Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 74107 CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + CLRBAR J K CLRBAR_BUF J_BUF K_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2BUF buf DPWR DGND + CLK CLK_BUF + D_107_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLK_BUF W1 W2 Y YB + D_107_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLKBAR Y YB QBUF QBAR_BUF + D_107_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + CLK_BUF J_BUF K_BUF CLKBAR JB KB + D0_GATE IO_STD U4 ao(3,2) DPWR DGND + J_BUF K_BUF QBAR_BUFD J_BUF KB $D_HI W1 + D_107_3 IO_STD MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J_BUF K_BUF QBUFD JB K_BUF $D_HI W2 + D_107_3 IO_STD MNTYMXDLY={MNTYMXDLY} UBUF bufa(4) DPWR DGND + QBUF QBAR_BUF QBUF QBAR_BUF Q QBAR QBUFD QBAR_BUFD + D_107_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_107_1 ugff ( + twghmx=19ns twghty=19ns + twpclmx=47ns twpclty=47ns + ) .model D_107_2 ugff ( + tppcqlhty=10ns tppcqlhmx=19ns + tppcqhlty=19ns tppcqhlmx=34ns + tpgqlhty=10ns tpgqlhmx=19ns + tpgqhlty=19ns tpgqhlmx=34ns + twghmx=20ns twghty=20ns + twpclmx=47ns twpclty=47ns + ) .model D_107_3 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) .model D_107_4 ugate ( + tplhmn=6ns tplhmx=6ns + ) *------------------------------------------------------------------------- * 74393 Dual 4-bit Binary Counter with Individual Clocks * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names .subckt 74393 A CLR QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inv DPWR DGND + CLR CLRBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + $D_HI CLRBAR A $D_HI $D_HI QA_BUF $D_NC + D_393_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + $D_HI CLRBAR QA_BUF $D_HI $D_HI QB_BUF $D_NC + D_393_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 jkff(1) DPWR DGND + $D_HI CLRBAR QB_BUF $D_HI $D_HI QC_BUF $D_NC + D_393_2 IO_STD MNTYMXDLY={MNTYMXDLY} U4 jkff(1) DPWR DGND + $D_HI CLRBAR QC_BUF $D_HI $D_HI QD_BUF $D_NC + D_393_3 IO_STD MNTYMXDLY={MNTYMXDLY} UBUFF bufa(4) DPWR DGND + QA_BUF QB_BUF QC_BUF QD_BUF QA QB QC QD + D_393_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_393_1 ueff ( + tppcqhlty=18ns tppcqhlmx=33ns + tpclkqlhty=6ns tpclkqlhmx=14ns + tpclkqhlty=7ns tpclkqhlmx=14ns + twclkhmn=20ns twclklmn=20ns + twpclmn=20ns tsudclkmn=25ns + ) .model D_393_2 ueff () .model D_393_3 ueff ( + tpclkqlhty=27ns tpclkqlhmx=40ns + tpclkqhlty=27ns tpclkqhlmx=40ns + ) .model D_393_4 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) * * AtoD and DtoA Subcircuits * ------------------------- * The subcircuits in this library are used to convert analog signals * into digital signals (AtoD) and digital signals into analog signals * (DtoA). The PSpice Digital Simulation Option creates "X" devices which * reference these subcircuits whenever it needs to convert a digital or * analog signal. The user usually will not need to use these subcircuits * directly. However, if you need to add new AtoD or DtoA subcircuits, the * interface nodes must be in the following order, and have the following * parameters: * * AtoD: .subckt <name> <analog-node> <dig-node> <dig-pwr> <dig-gnd> * + params: CAPACITANCE=0 * * DtoA: .subckt <name> <dig-node> <analog-node> <dig-pwr> <dig-gnd> * + params: DRVL=0 DRVH=0 CAPACITANCE=0 * * I/O Models * ---------- * I/O models specify the names of the AtoD and DtoA subcircuits PSpice must * use to convert analog signals to digital signals or vice versa. (I/O models * also describe driving and loading characteristics.) Up to four of each * AtoD and DtoA subcircuit names may be specified in an I/O model, using * parameters AtoD1 through AtoD4, and DtoA1 through DtoA4. The subcircuit * which PSpice actually uses depends on the value of the IO_LEVEL parameter * in a subcircuit reference. * * As implemented in this library, the levels have the following definitions: * * IO_LEVEL Definition * -------- -------------------------------------------------------------- * 1 Basic (simple) model with X, R, and F between VIL max and VIH min (AtoD) * 2 Basic (simple) model without intermediate X value * 3 Elaborate model with X between VIL max and VIH min (AtoD) * 4 Elaborate model without intermediate X, R, and F value * * The Elaborate model has a more accurate I-V curve, including clamping * diodes, but since it has more devices, it can take longer to simulate * when it is used. * * For example, to specify the basic interface without an intermediate * X value, you would use: * * X1 in out 74LS04 PARAMS: IO_LEVEL=2 * * If the IO_LEVEL is not specified for a device, the default IO_LEVEL is used. * The default level is controled by the .OPTION parameter DIGIOLVL, which * defaults to 1. * *----------------------------------------------------------------------------- * Digital Power Supply *----------------------------------------------------------------------------- * PSpice automatically creates one instance of this subcircuit if any * AtoD or DtoA interfaces are created. PSpice always uses node 0 as the * required analog reference node "GND". The digital power and ground * nodes default to global nodes named $G_DPWR and $G_DGND, which are * used throughout the digital libraries. The default output is 5.0v. * * To create your own power supply, simply create an instance of this * subcircuit, using your own digital power and ground node names, and * the desired voltage. For example: * * XMYPOWER 0 MY_PWR MY_GND DIGIFPWR params: VOLTAGE=3.5V * .subckt DIGIFPWR AGND + optional: DPWR=$G_DPWR DGND=$G_DGND + params: VOLTAGE=5.0v REFERENCE=0v * VDPWR DPWR DGND {VOLTAGE} R1 DPWR AGND 1MEG VDGND DGND REF {REFERENCE} R2 REF AGND 1E-6 R3 DGND AGND 1MEG .ends *----------------------------------------------------------------------------- * Stimulus Device Models and Subcircuits *----------------------------------------------------------------------------- *------------------------------------------------- * Stimulus I/O Models .model IO_STM uio ( + drvh=0 drvl=0 + DtoA1="DtoA_STM" DtoA2="DtoA_STM" + DtoA3="DtoA_STM" DtoA4="DtoA_STM" + ) .model IO_STM_OC uio ( + drvh=1MEG drvl=0 + DtoA1="DtoA_STM_OC" DtoA2="DtoA_STM_OC" + DtoA3="DtoA_STM_OC" DtoA4="DtoA_STM_OC" + ) *------------------------------------------------- * Stimulus DtoA Subcircuit .subckt DtoA_STM D A DPWR DGND + params: DRVL=0 DRVH=0 CAPACITANCE=0 * N1 A DGND DPWR DINSTM DGTLNET=D IO_STM C1 A 0 {CAPACITANCE+0.1pF} .ends *------------------------------------------------- * Stimulus Open Collector DtoA Subcircuit .subckt DtoA_STM_OC D A DPWR DGND + params: DRVL=0 DRVH=0 CAPACITANCE=0 * N1 A DGND DPWR DINSTM_OC DGTLNET=D IO_STM_OC C1 A 0 {CAPACITANCE+0.1pF} .ends *------------------------------------------------- * Stimulus Digital Input/Output Models * * We use 1/2 ohm and a 500ps transition time, on the assumption that * this will be a "strong" signal source with a "fast" switching time * in most systems which use this library. Change the tsw's and/or the * rlow and rhi values if these don't work for your system. * .model DINSTM dinput ( + s0name="0" s0tsw=0.5ns s0rlo=.5 s0rhi=1k + s1name="1" s1tsw=0.5ns s1rlo=1k s1rhi=.5 + s2name="X" s2tsw=0.5ns s2rlo=0.429 s2rhi=1.16 ; .313ohm, 1.35v + s3name="R" s3tsw=0.5ns s3rlo=0.429 s3rhi=1.16 ; .313ohm, 1.35v + s4name="F" s4tsw=0.5ns s4rlo=0.429 s4rhi=1.16 ; .313ohm, 1.35v + s5name="Z" s5tsw=0.5ns s5rlo=1MEG s5rhi=1MEG + ) .model DINSTM_OC dinput ( + s0name="0" s0tsw=0.5ns s0rlo=.5 s0rhi=1k + s1name="1" s1tsw=0.5ns s1rlo=1MEG s1rhi=1MEG + s2name="X" s2tsw=0.5ns s2rlo=0.429 s2rhi=1.16 ; .313ohm, 1.35v + s3name="R" s3tsw=0.5ns s3rlo=0.429 s3rhi=1.16 ; .313ohm, 1.35v + s4name="F" s4tsw=0.5ns s4rlo=0.429 s4rhi=1.16 ; .313ohm, 1.35v + s5name="Z" s5tsw=0.5ns s5rlo=1MEG s5rhi=1MEG + ) *----------------------------------------------------------------------------- * Zero-Delay Models *----------------------------------------------------------------------------- *------------------------------------------------- * Zero-Delay Gate Model .model D0_GATE ugate () *------------------------------------------------- * Zero-Delay Tristate Gate Model .model D0_TGATE utgate () *------------------------------------------------- * Zero-Delay Edge-Triggered Flip-Flop Model .model D0_EFF ueff () *------------------------------------------------- * Zero-Delay Gated Flip-Flop Model .model D0_GFF ugff () ****************************************************************************** * 74/54 Family (standard TTL) ****************************************************************************** *------------------------------------------------- * 7400 I/O Models .model IO_STD uio ( + drvh=96.4 drvl=104 + AtoD1="AtoD_STD" AtoD2="AtoD_STD_NX" + AtoD3="AtoD_STD_E" AtoD4="AtoD_STD_NXE" + DtoA1="DtoA_STD" DtoA2="DtoA_STD" + DtoA3="DtoA_STD" DtoA4="DtoA_STD" + ) .model IO_STD_ST uio ( + drvh=96.4 drvl=104 + AtoD1="AtoD_STD_ST" AtoD2="AtoD_STD_ST" + AtoD3="AtoD_STD_ST_E" AtoD4="AtoD_STD_ST_E" + DtoA1="DtoA_STD" DtoA2="DtoA_STD" + DtoA3="DtoA_STD" DtoA4="DtoA_STD" + ) .model IO_STD_OC uio ( + drvh=1MEG drvl=104 + AtoD1="AtoD_STD" AtoD2="AtoD_STD_NX" + AtoD3="AtoD_STD_E" AtoD4="AtoD_STD_NXE" + DtoA1="DtoA_STD_OC" DtoA2="DtoA_STD_OC" + DtoA3="DtoA_STD_OC" DtoA4="DtoA_STD_OC" + ) *------------------------------------------------- * 7400 Standard AtoD Subcircuits * Simple Models: .subckt AtoD_STD A D DPWR DGND + params: CAPACITANCE=0 * O0 A DGND DO74 DGTLNET=D IO_STD C1 A 0 {CAPACITANCE+0.1pF} .ends .subckt AtoD_STD_NX A D DPWR DGND + params: CAPACITANCE=0 * O0 A DGND DO74_NX DGTLNET=D IO_STD C1 A 0 {CAPACITANCE+0.1pF} .ends * Elaborate Models: .subckt AtoD_STD_E A D DPWR DGND + params: CAPACITANCE=0 * O0 A DGND DO74 DGTLNET=D IO_STD C1 A 0 {CAPACITANCE+0.1pF} D0 DGND a D74CLMP D1 1 2 D74 D2 2 DGND D74 R1 DPWR 3 4k Q1 1 3 A 0 Q74 ; substrait should be DGND .ends .subckt AtoD_STD_NXE A D DPWR DGND + params: CAPACITANCE=0 * O0 A DGND DO74_NX DGTLNET=D IO_STD C1 A 0 {CAPACITANCE+0.1pF} D0 DGND a D74CLMP D1 1 2 D74 D2 2 DGND D74 R1 DPWR 3 4k Q1 1 3 A 0 Q74 ; substrait should be DGND .ends *------------------------------------------------- * 7400 Schmidt trigger AtoD Subcircuits * Simple Model: .subckt AtoD_STD_ST A D DPWR DGND + params: CAPACITANCE=0 * O0 A DGND DO74_ST DGTLNET=D IO_STD C1 A 0 {CAPACITANCE+0.1pF} .ends * Elaborate Model: .subckt AtoD_STD_ST_E A D DPWR DGND + params: CAPACITANCE=0 * O0 A DGND DO74_ST DGTLNET=D IO_STD C1 A 0 {CAPACITANCE+0.1pF} D0 DGND a D74CLMP D1 1 2 D74 D2 2 DGND D74 R1 DPWR 3 4k Q1 1 3 A 0 Q74 .ends *------------------------------------------------- * 7400 standard DtoA Subcircuit .subckt DtoA_STD D A DPWR DGND + params: DRVL=0 DRVH=0 CAPACITANCE=0 * N1 A DGND DPWR DIN74 DGTLNET=D IO_STD C1 A 0 {CAPACITANCE+0.1pF} .ends *------------------------------------------------- * 7400 open collector DtoA Subcircuit .subckt DtoA_STD_OC D A DPWR DGND + params: DRVL=0 DRVH=0 CAPACITANCE=0 * N1 A DGND DPWR DIN74_OC DGTLNET=D IO_STD_OC C1 A 0 {CAPACITANCE+0.1pF} .ends *------------------------------------------------- * 7400 Digital Input/Output Models .model DIN74 dinput ( + s0name="0" s0tsw=3.5ns s0rlo=7.13 s0rhi=389 ; 7ohm, 0.09v + s1name="1" s1tsw=5.5ns s1rlo=467 s1rhi=200 ; 140ohm, 3.5v + s2name="X" s2tsw=3.5ns s2rlo=42.9 s2rhi=116 ; 31.3ohm, 1.35v + s3name="R" s3tsw=3.5ns s3rlo=42.9 s3rhi=116 ; 31.3ohm, 1.35v + s4name="F" s4tsw=3.5ns s4rlo=42.9 s4rhi=116 ; 31.3ohm, 1.35v + s5name="Z" s5tsw=3.5ns s5rlo=200K s5rhi=200K + ) .model DIN74_OC dinput ( + s0name="0" s0tsw=3.5ns s0rlo=7.13 s0rhi=389 ; 7ohm, 0.09v + s1name="1" s1tsw=5.5ns s1rlo=200K s1rhi=200K + s2name="X" s2tsw=3.5ns s2rlo=42.9 s2rhi=116 ; 31.3ohm, 1.35v + s3name="R" s3tsw=3.5ns s3rlo=42.9 s3rhi=116 ; 31.3ohm, 1.35v + s4name="F" s4tsw=3.5ns s4rlo=42.9 s4rhi=116 ; 31.3ohm, 1.35v + s5name="Z" s5tsw=5.5ns s5rlo=200K s5rhi=200K + ) .model DO74 doutput ( + s0name="X" s0vlo=0.8 s0vhi=2.0 + s1name="0" s1vlo=-1.5 s1vhi=0.8 + s2name="R" s2vlo=0.8 s2vhi=1.4 + s3name="R" s3vlo=1.3 s3vhi=2.0 + s4name="X" s4vlo=0.8 s4vhi=2.0 + s5name="1" s5vlo=2.0 s5vhi=7.0 + s6name="F" s6vlo=1.3 s6vhi=2.0 + s7name="F" s7vlo=0.8 s7vhi=1.4 + ) .model DO74_NX doutput ( + s0name="0" s0vlo=-1.5 s0vhi=1.35 + s2name="1" s2vlo=1.35 s2vhi=7.0 + ) .model DO74_ST doutput ( + s0name="0" s0vlo=-1.5 s0vhi=1.7 + s1name="1" s1vlo=0.9 s1vhi=7.0 + ) .model D74 d ( + is=1e-16 rs=25 cjo=2pf + ) .model D74CLMP d ( + is=1e-15 rs=2 cjo=2pf + ) .model Q74 npn ( + ise=1e-16 isc=4e-16 + bf=49 br=.03 + cje=1pf cjc=.5pf + cjs=3pf vje=0.9v + vjc=0.8v vjs=0.7v + mje=0.5 mjc=0.33 + mjs=0.33 tf=0.2ns + tr=10ns rb=50 + rc=20 + ) *------------------------------------------------------------------------------- * Library of optocoupler models * Copyright 1991 by MicroSim Corporation * This is a reduced version of MicroSim's Opto-coupler components library. * You are welcome to make as many copies of it as you find convenient. * The parameters in this model library were derived from the data sheets for * each part. *.model 4N25 * 6-pin DIP: pin #1 #2 #4 #5 #6 * | | | | | .subckt A4N25 pin1 pin2 pin4 pin5 pin6 params: rel_CTR=1 * Motorola pid=4N25 * 88-01-04 pwt * 88-01-18 pwt rework Cje approximation * The data sheet used for this model is from Motorola: it was the most * complete for DC and switching parameters, and is was easy to find the * component IR-LED and phototransistor as separate devices for further * specifications. d_MainLED pin1 pin2 MainLED d_PhotoLED pin1 1 PhotoLED .001 v_PhotoLED 1 pin2 0 f_TempComp 0 2 v_PhotoLED 1 r_TempComp 2 0 TempComp {rel_CTR} g_BaseSrc 5 6 2 0 .9 q_PhotoBJT 5 6 4 PhotoBJT r_C 5 pin5 .1 r_B 6 pin6 .1 r_E 4 pin4 .1 * Since active devices dominate pin-to-pin capacitance on each "side" of the * optocoupler, isolation is modeled by identical capacitances and resistances * linked to a common point; this gives isolation of .5pF and 1E+11 ohms c_1 pin1 7 .4p r_1 pin1 7 .12T c_2 pin2 7 .4p r_2 pin2 7 .12T c_4 pin4 7 .4p r_4 pin4 7 .12T c_5 pin5 7 .4p r_5 pin5 7 .12T c_6 pin6 7 .4p r_6 pin6 7 .12T * Similar to Motorola MLED15. .model MainLED D(Is=1.1p Rs=.66 Ikf=30m N=1.9 Xti=3 Cjo=40p M=.34 Vj=.75 + Isr=30n Nr=3.8 Bv=6 Ibv=100u Tt=.5u) * Models photon generation: same as MainLED except no AC effects, no breakdown. .model PhotoLED D(Is=1.1p Rs=.66 Ikf=30m N=1.9 Xti=3 Cjo=0 M=.34 Vj=.75 + Isr=30n Nr=3.8 Bv=0 Tt=0) * Temperature compensation for system: 1.38x @ -55'C, .54x @ +100'C, all @ 10mA * Note: the photo BJT has its own temperature corrections, which must be kept * as the transistor is electrically available. .model TempComp RES(R=1 Tc1=-11.27m Tc2=43.46u) * Similar to Motorola MDR3050; Hfe=325 @ Ic=500uA, Vce=5V * Use beta variation (w/Parts) to model change in current-transfer ratio (CTR). * Hand adjust reverse beta (Br) to match saturation characteristics. * Set Isc to model dark current. * Hand adjust Cjc to match fall time @ Ic=10mA (which yields rise time, too). * Hand adjust reverse transit-time (Tr) to match storage time @ Ic=10mA. * Delay time set by LED I-V and C-V characteristics; set Cje to 25% of Cjc, * inspection of phototransistor chip layouts show the emitter area is 20%-25% * that of the collector area. The same layouts show that base resistance is * made negligible by design; also, the operating currents are small. * Hand adjust forward transit-time (Tf) to match MDR3050 pulse data. Check * against 4N25 frequency response (Fig 11, 12). .model PhotoBJT NPN(Is=10f Xti=3 Vaf=60 + Bf=400 Ne=3.75 Ise=580p Ikf=.26 Xtb=1.5 + Br=.04 Nc=2 Isc=3.5n + Cjc=10p Mjc=.3333 Vjc=.75 Tr=88u + Cje=2.5p Mje=.3333 Vje=.75 Tf=1.5n) .ends *.model 4N25A * 6-pin DIP: pin #1 #2 #4 #5 #6 * | | | | | .subckt A4N25A pin1 pin2 pin4 pin5 pin6 * 88-01-05 pwt * Same as 4N25 (UL recognized). x1 pin1 pin2 pin4 pin5 pin6 A4N25 .ends *------------------------------------------------------------------------------- * Library of Thyristor (SCR and Triac) models * Copyright 1991 by MicroSim Corporation * This is a reduced version of MicroSim's Thyristor components library. * You are welcome to make as many copies of it as you find convenient. * Library of SCR models * NOTE: This library requires the "Analog Behavioral Modeling" * option available with PSpice. A model developed without * Behavioral Modeling was found to be very slow and not * very robust. * This macromodel uses a controlled switch as the basic SCR * structure. In all cases, the designer should use * the manufacturer's data book for actual part selection. * The required parameters were derived from data sheet (Motorola) * information on each part. When available, only "typical" * parameters are used (except for Idrm which is always * a "max" value). If a "typical" parameter is not available, * a "min" or "max" value may be used in which case a comment is * made in the library. * The SCRs are modeled at room temperature and do not track * changes with temperature. Note that Vdrm is specified by the * manufacturer as valid over a temperature range. Also, in * nearly all cases, dVdt and Toff are specified by the * manufacturer at approximately 100 degrees C. This results in a * model which is somewhat "conservative" for a room temperature * model. * The parameter dVdt (when available from the date sheet) is used * to model the Critical Rate of Rise of Off-State Voltage. If * not specified, dVdt is defaulted to 1000 V/microsecond. * A side effect of this model is that the turn-on current, Ion, * is determined by Vtm/(Ih*Vdrm). Vtm is also used as the * holding voltage. .SUBCKT Scr anode gate cathode PARAMS: + Vdrm=400v Vrrm=400v Idrm=10u + Ih=6ma dVdt=5e7 + Igt=5ma Vgt=0.7v + Vtm=1.7v Itm=24 + Ton=1u Toff=15u * Where: * Vdrm => Forward breakover voltage * Vrrm => Reverse breakdown voltage * Idrm => Peak blocking current * Ih => Holding current * dVdt => Critical value for dV/dt triggering * Igt => Gate trigger current * Vgt => Gate trigger voltage * Vtm => On-state voltage * Itm => On-state current * Ton => Turn-on time * Toff => Turn-off time * Main conduction path Scr anode anode0 control 0 Vswitch ; controlled switch Dak1 anode0 anode2 Dakfwd OFF ; SCR is initially off Dka cathode anode0 Dkarev OFF VIak anode2 cathode ; current sensor * dVdt Turn-on Emon dvdt0 0 TABLE {v(anode,cathode)} (0 0) (2000 2000) CdVdt dvdt0 dvdt1 100pfd ; displacement current Rdlay dvdt1 dvdt2 1k VdVdt dvdt2 cathode DC 0.0 EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10) RdVdt condvdt 0 1meg * Gate Rseries gate gate1 {(Vgt-0.65)/Igt} Rshunt gate1 gate2 {0.65/Igt} Dgkf gate1 gate2 Dgk VIgf gate2 cathode ; current sensor * Gate Turn-on Egate1 gate4 0 TABLE {i(Vigf)-0.95*Igt} (0 0) (1m 10) Rgate1 gate4 0 1meg Egon1 congate 0 TABLE {v(gate4)*v(anode,cathode)} (0 0) (10 10) Rgon1 congate 0 1meg * Main Turn-on EItot Itot 0 TABLE {i(VIak)+5E-5*i(VIgf)/Igt} (0 0) (2000 2000) RItot Itot 0 1meg Eprod prod 0 TABLE {v(anode,cathode)*v(Itot)} (0 0) (1 1) Rprod prod 0 1meg Elin conmain 0 TABLE + {10*(v(prod) - (Vtm*Ih))/(Vtm*Ih)} (0 0) (2 10) Rlin conmain 0 1meg * Turn-on/Turn-off control Eonoff contot 0 TABLE + {v(congate)+v(conmain)+v(condvdt)} (0 0) (10 10) * Turn-on/Turn-off delays Rton contot dlay1 825 Dton dlay1 control Delay Rtoff contot dlay2 {290*Toff/Ton} Dtoff control dlay2 Delay Cton control 0 {Ton/454} * Reverse breakdown Dbreak anode break1 Dbreak Dbreak2 cathode break1 Dseries * Controlled switch model .MODEL Vswitch vswitch + (Ron = {(Vtm-0.7)/Itm}, Roff = {Vdrm*Vdrm/(Vtm*Ih)}, + Von = 5.0, Voff = 1.5) * Diodes .MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5) .MODEL Dseries D (Is=1E-14) .MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01) .MODEL Dkarev D (Is=1E-10 Cjo=5pf Rs=0.01) .MODEL Dakfwd D (Is=4E-11 Cjo=5pf) .MODEL Dbreak D (Ibv=1E-7 Bv={1.1*Vrrm} Cjo=5pf Rs=0.5) * Allow the gate to float if required Rfloat gate cathode 1e10 .ENDS * .SUBCKT 2N1595 anode gate cathode * "Typical" parameters X1 anode gate cathode Scr PARAMS: + Vdrm=50v Vrrm=50v Ih=5ma Vtm=1.1v Itm=1 + dVdt=1e9 Igt=2ma Vgt=.7v Ton=0.8u Toff=10u + Idrm=10u * 90-5-18 Morotola DL137, Rev 2, 3/89 .ENDS * Library of Triac models * NOTE: This library requires the "Analog Behavioral Modeling" * option available with PSpice. * This macromodel uses two controlled switches as the basic triac * structure. The model was developed to provide firing in all * four quadrants. It should be noted, however, that the library * contains parts which the manufacturer has guaranteed will fire * in 4 quadrants, 3 quadrants or 2 quadrants. Therefore, the * designer should always use the manufacturer's data book for * part selection. * The required parameters were derived from data sheet (Motorola) * information on each part. When available, only "typical" * parameters are used (except for Idrm which is always * a "max" value). If a "typical" parameter is not available, * a "min" or "max" value may be used in which case a comment is * made in the library. * The triacs are modeled at room temperature and do not track * changes with temperature. Note that Vdrm is specified by the * manufacturer as valid over a temperature range. Also, in * nearly all cases, dVdt is specified by the manufacturer at * approximately 100 degrees C. This results in a model which * is somewhat "conservative" for a room temperature model. * The parameter dVdt (when available from the date sheet) is used * to model the Critical Rate of Rise of Off-State Voltage. If * not specified, dVdt is defaulted to 1000 V/microsecond. The * Critical Rate of Rise of Commutation Voltage is not modeled. * It is generally good practice to use an RC snubber network * across the triac to limit the commutating dvdt to a value below * the maximum allowable rating (see manufacturer's data sheet and * application notes). Also, note that the turn-off time is * assumed to be zero. .SUBCKT Triac MT2 gate MT1 PARAMS: + Vdrm=400v Idrm=10u + Ih=6ma dVdt=50e6 + Igt=20ma Vgt=0.9v + Vtm=1.3v Itm=17 + Ton=1.5u * Where: * Vdrm => Forward breakover voltage * Idrm => Peak blocking current * Ih => Holding current [MT2(+)] * dVdt => Critical value for dV/dt triggering * Igt => Gate trigger current [MT2(+),G(-)] * Vgt => Gate trigger voltage [MT2(+),G(-)] * Vtm => On-state voltage * Itm => On-state current * Ton => Turn-on time * Main conduction path Striac MT2 MT20 cntrol 0 Vswitch ; controlled switch Dak1 MT20 MT22 Dak OFF ; triac is initially off VIak MT22 MT1 ; current sensor Striacr MT2 MT23 cntrolr 0 Vswitch ; controlled switch Dka1 MT21 MT23 Dak OFF ; triac is initially off VIka MT1 MT21 ; reverse current sense * dVdt Turn-on Emon dvdt0 0 TABLE {ABS(V(MT2,MT1))} (0 0) (2000 2000) CdVdt dvdt0 dvdt1 100pfd ; displacement current Rdlay dvdt1 dvdt2 1k VdVdt dvdt2 MT1 DC 0.0 EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10) RdVdt condvdt 0 1meg * Gate Rseries gate gate1 {(Vgt-0.65)/Igt} Rshunt gate1 gate2 {0.65/Igt} Dgkf gate1 gate2 Dgk Dgkr gate2 gate1 Dgk VIgf gate2 MT1 DC 0.0 ; current sensor * Gate Turn-on Egate congate 0 TABLE {(ABS(i(VIgf))-0.95*Igt)} (0 0) (1m 10) Rgate congate 0 1meg * Holding current, holding voltage (Quadrant I) Emain1 main1 0 TABLE {i(VIak)-Ih+5e-3*i(VIgf)/Igt} (0 0) (.1m 1) Rmain1 main1 0 1meg Emain2 main2 0 TABLE {v(MT2,MT1)-(Ih*Vtm/Itm)} (0 0) (.1m 1) Rmain2 main2 0 1meg Emain3 cnhold 0 TABLE {v(main1,0)*v(main2,0)} (0 0 (1 10) Rmain3 cnhold 0 1meg * Holding current, holding voltage (Quadrant III) Emain1r main1r 0 TABLE {i(VIka)-Ih-5e-3*i(VIgf)/Igt} (0 0) (.1m 1) Rmain1r main1r 0 1meg Emain2r main2r 0 TABLE {v(MT1,MT2)-(Ih*Vtm/Itm)} (0 0) (.1m 1) Rmain2r main2r 0 1meg Emain3r cnholdr 0 TABLE {v(main1r,0)*v(main2r,0)} (0 0 (1 10) Rmain3r cnholdr 0 1meg * Main Emain4 main4 0 table {(1.0-ABS(i(VIgf))/Igt)} (0 0) (1 1) Rmain4 main4 0 1meg Emain5 cnmain 0 table {v(mt2,mt1)-1.05*Vdrm*v(main4)} (0 0) (1 10) Rmain5 cnmain 0 1meg Emain5r cnmainr 0 table {v(mt1,mt2)-1.05*Vdrm*v(main4)} (0 0) (1 10) Rmain5r cnmainr 0 1meg * Turn-on/Turn-off control (Quadrant I ) Eonoff contot 0 TABLE + {v(cnmain)+v(congate)+v(cnhold)+v(condvdt)} (0 0) (10 10) * Turn-on/Turn-off delays (Quadrant I) Rton contot dlay1 825 Dton dlay1 cntrol Delay Rtoff contot dlay2 {2.9E-3/Ton} Dtoff cntrol dlay2 Delay Cton cntrol 0 {Ton/454} * Turn-on/Turn-off control (Quadrant III) Eonoffr contotr 0 TABLE + {v(cnmainr)+v(congate)+v(cnholdr)+v(condvdt)} (0 0) (10 10) * Turn-on/Turn-off delays (Quadrant III) Rtonr contotr dlayr1 825 Dtonr dlayr1 cntrolr Delay Rtoffr contotr dlayr2 {2.9E-3/Ton} Dtoffr cntrolr dlayr2 Delay Ctonr cntrolr 0 {Ton/454} * Controlled switch model .MODEL Vswitch vswitch + (Ron = {(Vtm-0.7)/Itm}, Roff = {1.75E-3*Vdrm/Idrm}, + Von = 5.0, Voff = 1.5) * Diodes .MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5) .MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01) .MODEL Dak D (Is=4E-11 Cjo=5pf) * Allow the gate to float if required Rfloat gate MT1 1e10 .ENDS * .SUBCKT 2N5444 MT2 gate MT1 * Min and Max parameters X1 MT2 gate MT1 Triac PARAMS: + Vdrm=200v Idrm=10u Ih=70ma dVdt=50e6 Ton=1u + Igt=70ma Vgt=2.0v Vtm=1.65v Itm=56 * 90-5-18 Morotola DL137, Rev 2, 3/89 .ENDS * End of library file