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- ************************************************************************
- * *
- * Program : PC-DRC V6.00B2.1 *
- * Date : Jul 02 1992 *
- * Time : 10:47AM *
- * Database : layout2.pcb *
- * Output : 3_layer.drc *
- * *
- ************************************************************************
-
-
- Disjoint Subnets
-
- NET COMP PIN COORDINATES COMP PIN COORDINATES
-
-
-
- Total Number of Disjoint Subnets: 0
-
- ***********************************************************************
- * *
- * Program : PC-DRC V6.00B2.1 *
- * Date : Jul 02 1992 10:47:40 AM *
- * Database : layout2.pcb *
- * Pass : pass_1 *
- * *
- ***********************************************************************
-
-
- LAYERS GROUPED:
- ---------------
- COMP
- PADCOM
-
-
- DESIGN RULES SET:
- -----------------
- Pad size....................................60.00
- Nonround pad size...........................60.00
- Via size....................................50.00
- Trace width.................................12.00
- Pad to pad spacing..........................10.00
- Pad to trace spacing........................10.00
- Trace to trace spacing......................10.00
- Pad to board edge spacing...................75.00
- Trace to board edge spacing.................75.00
-
-
-
- Inner Plane Connectivity:
- -------------------------
- Aperture Values Nets
- --------------- ----
- 22
-
-
-
-
- No DRC errors were found on this pass.
-
-
-
- STATISTICS:
- -----------
- Number of pads processed 67
- Number of vias processed 6
- Number of traces processed 80
- Number of other shapes processed 8
-
- Number of pad size errors 0
- Number of via size errors 0
- Number of trace width errors 0
-
- Number of pad to pad errors 0
- Number of pad to trace or shape errors 0
- Number of trace to trace or shape errors 0
- Number of pad to board edge errors 0
- Number of trace or shape to board edge errors 0
-
-
- Total number of entities processed 161
- Total number of size violations 0
- Total number of spacing violations 0
- Total number of violations 0
-
- Time finished: 10:47:42 AM
-
- ***********************************************************************
- * *
- * Program : PC-DRC V6.00B2.1 *
- * Date : Jul 02 1992 10:47:42 AM *
- * Database : layout2.pcb *
- * Pass : pass_2 *
- * *
- ***********************************************************************
-
-
- LAYERS GROUPED:
- ---------------
- SOLDER
- PADSLD
-
-
- DESIGN RULES SET:
- -----------------
- Pad size....................................60.00
- Nonround pad size...........................60.00
- Via size....................................50.00
- Trace width.................................12.00
- Pad to pad spacing..........................10.00
- Pad to trace spacing........................10.00
- Trace to trace spacing......................10.00
- Pad to board edge spacing...................75.00
- Trace to board edge spacing.................75.00
-
-
-
- Inner Plane Connectivity:
- -------------------------
- Aperture Values Nets
- --------------- ----
- 22
-
-
-
-
- No DRC errors were found on this pass.
-
-
-
- STATISTICS:
- -----------
- Number of pads processed 67
- Number of vias processed 6
- Number of traces processed 9
- Number of other shapes processed 8
-
- Number of pad size errors 0
- Number of via size errors 0
- Number of trace width errors 0
-
- Number of pad to pad errors 0
- Number of pad to trace or shape errors 0
- Number of trace to trace or shape errors 0
- Number of pad to board edge errors 0
- Number of trace or shape to board edge errors 0
-
-
- Total number of entities processed 90
- Total number of size violations 0
- Total number of spacing violations 0
- Total number of violations 0
-
- Time finished: 10:47:44 AM
-