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- ( { OrCAD PCB NetList Format
- Demonstration Design (2 Bit Adder) Revised: July 13, 1989
- 890713-0001 Revision: 2
- OrCAD L.P.
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- Time Stamp - 13-JUL-1989 15:44:39 }
- ( 3E0DB148 14DIP300 U2 74LS04
- ( 1 CIN )
- ( 2 N00006 )
- ( 3 N00007 )
- ( 4 N00002 )
- ( 5 X0 )
- ( 6 N00009 )
- ( 7 GND )
- ( 8 N00004 )
- ( 9 Y0 )
- ( 10 N00018 )
- ( 11 N00011 )
- ( 12 N00014 )
- ( 13 N00019 )
- ( 14 VCC )
- )
- ( 3E0DB15A 14DIP300 U7 74LS04
- ( 1 X1 )
- ( 2 N00021 )
- ( 3 Y1 )
- ( 4 N00016 )
- ( 7 GND )
- ( 14 VCC )
- )
- ( 3E0DB14A 14DIP300 U3 74LS08
- ( 1 CIN )
- ( 2 N00002 )
- ( 3 N00001 )
- ( 4 N00007 )
- ( 5 N00006 )
- ( 6 N00005 )
- ( 7 GND )
- ( 8 N00010 )
- ( 9 N00007 )
- ( 10 CIN )
- ( 11 N00003 )
- ( 12 X0 )
- ( 13 N00004 )
- ( 14 VCC )
- )
- ( 3E0DB150 14DIP300 U4 74LS08
- ( 1 Y0 )
- ( 2 N00009 )
- ( 3 N00008 )
- ( 4 Y0 )
- ( 5 X0 )
- ( 6 N00012 )
- ( 7 GND )
- ( 8 N00013 )
- ( 9 N00011 )
- ( 10 N00014 )
- ( 11 N00017 )
- ( 12 N00019 )
- ( 13 N00018 )
- ( 14 VCC )
- )
- ( 3E0DB159 14DIP300 U5 74LS08
- ( 1 N00019 )
- ( 2 N00011 )
- ( 3 N00022 )
- ( 4 X1 )
- ( 5 N00016 )
- ( 6 N00015 )
- ( 7 GND )
- ( 8 N00020 )
- ( 9 Y1 )
- ( 10 N00021 )
- ( 11 N00023 )
- ( 12 Y1 )
- ( 13 X1 )
- ( 14 VCC )
- )
- ( 3E0DB14D 14DIP300 U1 74LS32
- ( 1 N00010 )
- ( 2 N00012 )
- ( 3 N00011 )
- ( 4 N00001 )
- ( 5 N00005 )
- ( 6 S0 )
- ( 7 GND )
- ( 8 N00007 )
- ( 9 N00003 )
- ( 10 N00008 )
- ( 11 COUT )
- ( 12 N00022 )
- ( 13 N00023 )
- ( 14 VCC )
- )
- ( 3E0DB158 14DIP300 U6 74LS32
- ( 1 N00013 )
- ( 2 N00017 )
- ( 3 S1 )
- ( 4 N00015 )
- ( 5 N00020 )
- ( 6 N00019 )
- ( 7 GND )
- ( 14 VCC )
- )
- ( 3E0DB169 10HH100 JP1 HEADER10
- ( 1 X0 )
- ( 2 X1 )
- ( 3 Y0 )
- ( 4 Y1 )
- ( 5 S0 )
- ( 6 S1 )
- ( 7 CIN )
- ( 8 COUT )
- ( 9 GND )
- ( 10 VCC )
- )
- )
-