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/ Amiga ISO Collection / AmigaUtilCD2.iso / Programming / Assembler / dse-src3.dms / in.adf / Source / Include / custom.i
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Text File  |  1992-11-10  |  10.0 KB  |  260 lines
  1. * Custom chip register addresses *
  2. Custom        equ    $dff000    ; Custom chips base address
  3.  
  4. bltddat        equ    $0000    ; Blitter Destination Data (DMA only)
  5. dmaconr        equ    $0002    ; DMA Enable Read
  6. vposr        equ    $0004    ; Vertical Beam Position Read
  7. vhposr        equ    $0006    ; Vert/Horiz Beam Position Read
  8. dskdatr        equ    $0008    ; Disk Data Read (DMA only)
  9. joy0dat        equ    $000a    ; Joystick/Mouse Port 0 Data (read)
  10. joy1dat        equ    $000c    ; Joystick/Mouse Port 1 Data (read)
  11. clxdat        equ    $000e    ; Collision Data (read)
  12. adkconr        equ    $0010    ; Audio/Disk Control Read
  13. pot0dat        equ    $0012    ; Pot Port 0 Data Read
  14. pot1dat        equ    $0012    ; Pot Port 1 Data Read
  15. potgor        equ    $0016    ; Pot Port Data Read
  16. serdatr        equ    $0018    ; Serial Data Input and Status Read
  17. dskbytr        equ    $001a    ; Disk Data Byte and Disk Status Read
  18. intenar        equ    $001c    ; Interrupt Enable (read)
  19. intreqr        equ    $001e    ; Interrupt Request (read)
  20. dskpt        equ    $0020    ; Disk Pointer (write)
  21. dskpth        equ    dskpt
  22. dskptl        equ    dskpt+2
  23. dsklen        equ    $0024    ; Disk Data Length
  24. dskdat        equ    $0026    ; Disk DMA Write
  25. refptr        equ    $0028    ; Refresh Pointer (write) DON'T USE!
  26. vposw        equ    $002a    ; Vert Beam Position Write DON'T USE!
  27. vhposw        equ    $002c    ; Vert/Horiz Beam Pos Write DON'T USE!
  28. copcon        equ    $002e    ; Coprocessor Control
  29. serdat        equ    $0030    ; Serial Data Output (write)
  30. serper        equ    $0032    ; Serial Period & Data Bit Control (write)
  31. potgo        equ    $0034    ; Pot Port Data (write)
  32. joytest        equ    $0036    ; JOY0DAT and JOY1DAT Write
  33. strequ        equ    $0038    ; Short Frame Vertical Strobe
  34. strvbl        equ    $003a    ; Normal Vertical Blank Stobe
  35. strhor        equ    $003c    ; Horizontal Sync Strobe
  36. strlong        equ    $003e    ; Long Raster Strobe
  37. bltcon0        equ    $0040    ; Blitter Control Register 0 (write)
  38. bltcon1        equ    $0042    ; Blitter Control Register 1 (write)
  39. bltafwm        equ    $0044    ; Source A First Word Mask (write)
  40. bltalwm        equ    $0046    ; Source A Last Word Mask (write)
  41. bltcpt        equ    $0048    ; Blitter Source C Pointer (write)
  42. bltcpth        equ    bltcpt
  43. bltcptl        equ    bltcpt+2
  44. bltbpt        equ    $004c    ; Blitter Source B Pointer (write)
  45. bltbpth        equ    bltbpt
  46. bltbptl        equ    bltbpt+2
  47. bltapt        equ    $0050    ; Blitter Source A Pointer (write)
  48. bltapth        equ    bltapt
  49. bltaptl        equ    bltapt+2
  50. bltdpt        equ    $0054    ; Blitter Destination Pointer (write)
  51. bltdpth        equ    bltdpt
  52. bltdptl        equ    bltdpt+2
  53. bltsize        equ    $0058    ; Blitter Start and Size (write)
  54.  
  55. bltcmod        equ    $0060    ; Blitter Source C Modulo (write)
  56. bltbmod        equ    $0062    ; Blitter Source B Modulo (write)
  57. bltamod        equ    $0064    ; Blitter Source A Modulo (write)
  58. bltdmod        equ    $0066    ; Blitter Destination Modulo (write)
  59.  
  60. bltcdat        equ    $0070    ; Blitter Source C Data (write)
  61. bltbdat        equ    $0072    ; Blitter Source B Data (write)
  62. bltadat        equ    $0074    ; Blitter Source A Data (write)
  63.  
  64. dsksync        equ    $007e    ; Disk Sync Pattern (write)
  65. cop1lc        equ    $0080    ; Copper Program Counter 1 (write)
  66. cop1lch        equ    cop1lc
  67. cop1lcl        equ    cop1lc+2
  68. cop2lc        equ    $0080    ; Copper Program Counter 2 (write)
  69. cop2lch        equ    cop2lc
  70. cop2lcl        equ    cop2lc+2
  71. copjmp1        equ    $0088    ; Copper Jump Strobe 1
  72. copjmp2        equ    $0088    ; Copper Jump Strobe 2
  73. copins        equ    $008c    ; Copper Instruction Identity (write)
  74. diwstrt        equ    $008e    ; Display Window Start (write)
  75. diwstop        equ    $0090    ; Display Window Stop (write)
  76. ddfstrt        equ    $0092    ; Display Data Fetch Start (write)
  77. ddfstop        equ    $0094    ; Display Data Fetch Stop (write)
  78. dmacon        equ    $0096    ; DMA Control (write)
  79. clxcon        equ    $0098    ; Collision Control (write)
  80. intena        equ    $009a    ; Interrupt Enable (write)
  81. intreq        equ    $009c    ; Interrupt Request (write)
  82. adkcon        equ    $009e    ; Audio/Disk Control (write)
  83. aud0lc        equ    $00a0    ; Channel 0 Waveform Address (write)
  84. aud0lch        equ    aud0lc
  85. aud0lcl        equ    aud0lc+2
  86. aud0len        equ    $00a4    ; Channel 0 Waveform Length (write)
  87. aud0per        equ    $00a6    ; Channel 0 Period (write)
  88. aud0vol        equ    $00a8    ; Channel 0 Volume (write)
  89. aud0dat        equ    $00aa    ; Channel 0 Data (write)
  90.  
  91. aud1lc        equ    $00b0    ; Channel 1 Waveform Address (write)
  92. aud1lch        equ    aud1lc
  93. aud1lcl        equ    aud1lc+2
  94. aud1len        equ    $00b4    ; Channel 1 Waveform Length (write)
  95. aud1per        equ    $00b6    ; Channel 1 Period (write)
  96. aud1vol        equ    $00b8    ; Channel 1 Volume (write)
  97. aud1dat        equ    $00ba    ; Channel 1 Data (write)
  98.  
  99. aud2lc        equ    $00c0    ; Channel 2 Waveform Address (write)
  100. aud2lch        equ    aud2lc
  101. aud2lcl        equ    aud2lc+2
  102. aud2len        equ    $00c4    ; Channel 2 Waveform Length (write)
  103. aud2per        equ    $00c6    ; Channel 2 Period (write)
  104. aud2vol        equ    $00c8    ; Channel 2 Volume (write)
  105. aud2dat        equ    $00ca    ; Channel 2 Data (write)
  106.  
  107. aud3lc        equ    $00d0    ; Channel 3 Waveform Address (write)
  108. aud3lch        equ    aud3lc
  109. aud3lcl        equ    aud3lc+2
  110. aud3len        equ    $00d4    ; Channel 3 Waveform Length (write)
  111. aud3per        equ    $00d6    ; Channel 3 Period (write)
  112. aud3vol        equ    $00d8    ; Channel 3 Volume (write)
  113. aud3dat        equ    $00da    ; Channel 3 Data (write)
  114.  
  115. bpl1pt        equ    $00e0    ; Bitplane 1 Pointer (write)
  116. bpl1pth        equ    bpl1pt
  117. bpl1ptl        equ    bpl1pt+2
  118. bpl2pt        equ    $00e4    ; Bitplane 2 Pointer (write)
  119. bpl2pth        equ    bpl2pt
  120. bpl2ptl        equ    bpl2pt+2
  121. bpl3pt        equ    $00e8    ; Bitplane 3 Pointer (write)
  122. bpl3pth        equ    bpl3pt
  123. bpl3ptl        equ    bpl3pt+2
  124. bpl4pt        equ    $00ec    ; Bitplane 4 Pointer (write)
  125. bpl4pth        equ    bpl4pt
  126. bpl4ptl        equ    bpl4pt+2
  127. bpl5pt        equ    $00f0    ; Bitplane 5 Pointer (write)
  128. bpl5pth        equ    bpl5pt
  129. bpl5ptl        equ    bpl5pt+2
  130. bpl6pt        equ    $00f4    ; Bitplane 6 Pointer (write)
  131. bpl6pth        equ    bpl6pt
  132. bpl6ptl        equ    bpl6pt+2
  133.  
  134. bplcon0        equ    $0100    ; Bitplane Control Register 0 (write)
  135. bplcon1        equ    $0102    ; Bitplane Control Register 1 (write)
  136. bplcon2        equ    $0104    ; Bitplane Control Register 2 (write)
  137.  
  138. bpl1mod        equ    $0108    ; Bitplane Modulo 1 (write)
  139. bpl2mod        equ    $010a    ; Bitplane Modulo 2 (write)
  140.  
  141. bpl1dat        equ    $0110    ; Bitplane Data Register 1 (write)
  142. bpl2dat        equ    $0112    ; Bitplane Data Register 2 (write)
  143. bpl3dat        equ    $0114    ; Bitplane Data Register 3 (write)
  144. bpl4dat        equ    $0116    ; Bitplane Data Register 4 (write)
  145. bpl5dat        equ    $0118    ; Bitplane Data Register 5 (write)
  146. bpl6dat        equ    $011a    ; Bitplane Data Register 6 (write)
  147.  
  148. spr0pt        equ    $0120    ; Sprite Pointer 0 (write)
  149. spr0pth        equ    spr0pt
  150. spr0ptl        equ    spr0pt+2
  151. spr1pt        equ    $0124    ; Sprite Pointer 1 (write)
  152. spr1pth        equ    spr1pt
  153. spr1ptl        equ    spr1pt+2
  154. spr2pt        equ    $0128    ; Sprite Pointer 2 (write)
  155. spr2pth        equ    spr2pt
  156. spr2ptl        equ    spr2pt+2
  157. spr3pt        equ    $012c    ; Sprite Pointer 3 (write)
  158. spr3pth        equ    spr3pt
  159. spr3ptl        equ    spr3pt+2
  160. spr4pt        equ    $0130    ; Sprite Pointer 4 (write)
  161. spr4pth        equ    spr4pt
  162. spr4ptl        equ    spr4pt+2
  163. spr5pt        equ    $0134    ; Sprite Pointer 5 (write)
  164. spr5pth        equ    spr5pt
  165. spr5ptl        equ    spr5pt+2
  166. spr6pt        equ    $0138    ; Sprite Pointer 6 (write)
  167. spr6pth        equ    spr6pt
  168. spr6ptl        equ    spr6pt+2
  169. spr7pt        equ    $013c    ; Sprite Pointer 7 (write)
  170. spr7pth        equ    spr7pt
  171. spr7ptl        equ    spr7pt+2
  172.  
  173. spr0pos        equ    $0140    ; Sprite Position 0 (write)
  174. spr0ctl        equ    $0142    ; Sprite Control 0 (write)
  175. spr0data    equ    $0144    ; Sprite Data A Register 0 (write)
  176. spr0datb    equ    $0146    ; Sprite Data B Register 0 (write)
  177. spr1pos        equ    $0148    ; Sprite Position 1 (write)
  178. spr1ctl        equ    $014a    ; Sprite Control 1 (write)
  179. spr1data    equ    $014c    ; Sprite Data A Register 1 (write)
  180. spr1datb    equ    $014e    ; Sprite Data B Register 1 (write)
  181. spr2pos        equ    $0150    ; Sprite Position 2 (write)
  182. spr2ctl        equ    $0152    ; Sprite Control 2 (write)
  183. spr2data    equ    $0154    ; Sprite Data A Register 2 (write)
  184. spr2datb    equ    $0156    ; Sprite Data B Register 2 (write)
  185. spr3pos        equ    $0158    ; Sprite Position 3 (write)
  186. spr3ctl        equ    $015a    ; Sprite Control 3 (write)
  187. spr3data    equ    $015c    ; Sprite Data A Register 3 (write)
  188. spr3datb    equ    $015e    ; Sprite Data B Register 3 (write)
  189. spr4pos        equ    $0160    ; Sprite Position 4 (write)
  190. spr4ctl        equ    $0162    ; Sprite Control 4 (write)
  191. spr4data    equ    $0164    ; Sprite Data A Register 4 (write)
  192. spr4datb    equ    $0166    ; Sprite Data B Register 4 (write)
  193. spr5pos        equ    $0168    ; Sprite Position 5 (write)
  194. spr5ctl        equ    $016a    ; Sprite Control 5 (write)
  195. spr5data    equ    $016c    ; Sprite Data A Register 5 (write)
  196. spr5datb    equ    $016e    ; Sprite Data B Register 5 (write)
  197. spr6pos        equ    $0170    ; Sprite Position 6 (write)
  198. spr6ctl        equ    $0172    ; Sprite Control 6 (write)
  199. spr6data    equ    $0174    ; Sprite Data A Register 6 (write)
  200. spr6datb    equ    $0176    ; Sprite Data B Register 6 (write)
  201. spr7pos        equ    $0178    ; Sprite Position 7 (write)
  202. spr7ctl        equ    $017a    ; Sprite Control 7 (write)
  203. spr7data    equ    $017c    ; Sprite Data A Register 7 (write)
  204. spr7datb    equ    $017e    ; Sprite Data B Register 7 (write)
  205.  
  206. color00        equ    $0180    ; Color Register 0 (write)
  207. color01        equ    $0182    ; Color Register 1 (write)
  208. color02        equ    $0184    ; Color Register 2 (write)
  209. color03        equ    $0186    ; Color Register 3 (write)
  210. color04        equ    $0188    ; Color Register 4 (write)
  211. color05        equ    $018a    ; Color Register 5 (write)
  212. color06        equ    $018c    ; Color Register 6 (write)
  213. color07        equ    $018e    ; Color Register 7 (write)
  214. color08        equ    $0190    ; Color Register 8 (write)
  215. color09        equ    $0192    ; Color Register 9 (write)
  216. color10        equ    $0194    ; Color Register 10 (write)
  217. color11        equ    $0196    ; Color Register 11 (write)
  218. color12        equ    $0198    ; Color Register 12 (write)
  219. color13        equ    $019a    ; Color Register 13 (write)
  220. color14        equ    $019c    ; Color Register 14 (write)
  221. color15        equ    $019e    ; Color Register 15 (write)
  222. color16        equ    $01a0    ; Color Register 16 (write)
  223. color17        equ    $01a2    ; Color Register 17 (write)
  224. color18        equ    $01a4    ; Color Register 18 (write)
  225. color19        equ    $01a6    ; Color Register 19 (write)
  226. color20        equ    $01a8    ; Color Register 20 (write)
  227. color21        equ    $01aa    ; Color Register 21 (write)
  228. color22        equ    $01ac    ; Color Register 22 (write)
  229. color23        equ    $01ae    ; Color Register 23 (write)
  230. color24        equ    $01b0    ; Color Register 24 (write)
  231. color25        equ    $01b2    ; Color Register 25 (write)
  232. color26        equ    $01b4    ; Color Register 26 (write)
  233. color27        equ    $01b6    ; Color Register 27 (write)
  234. color28        equ    $01b8    ; Color Register 28 (write)
  235. color29        equ    $01ba    ; Color Register 29 (write)
  236. color30        equ    $01bc    ; Color Register 30 (write)
  237. color31        equ    $01be    ; Color Register 31 (write)
  238. beamcon0    equ    $01dc    ; Video Beam Control 0 (write)
  239.  
  240. * CIA addresses *
  241. CIAA        equ    $bfe001    ; CIAA base address
  242. CIAB        equ    $bfd000    ; CIAB base address
  243. PRA        equ    $000    ; Peripheral Data Register for port A
  244. PRB        equ    $100    ; Peripheral Data Register for port B
  245. DDRA        equ    $200    ; Data Direction Register A
  246. DDRB        equ    $300    ; Data Direction Register B
  247. TALO        equ    $400    ; Timer A Low Byte
  248. TAHI        equ    $500    ; Timer A High Byte
  249. TBLO        equ    $600    ; Timer B Low Byte
  250. TBHI        equ    $700    ; Timer B High Byte
  251. TODLO        equ    $800    ; TOD Counter Low Byte
  252. TODMID        equ    $900    ; TOD Counter Mid Byte
  253. TODHI        equ    $a00    ; TOD Counter High Byte
  254. TODHR        equ    $b00    ; Unused
  255. SDR        equ    $c00    ; Serial Data Register
  256. ICR        equ    $d00    ; Interrupt Control Register
  257. CRA        equ    $e00    ; Control Register A
  258. CRB        equ    $f00    ; Control Register B
  259.  
  260.