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The F-PC Assembler The F-PC Assembler Section 9: The F-PC Assembler Section 9: The F-PC Assembler ______________________________ Updated 01 Oct 89 Updated 01 Oct 89 _________________ PASM, The F-PC Assembler ____________________________ 2 PREFIX or POSTFIX ? _____________________________ 2 The 80386 and 80386SX ___________________________ 3 PASM386.SEQ _____________________________________ 3 Disassembler ____________________________________ 3 PASM Glossary _______________________________________ 4 Addressing Modes ____________________________________ 5 Register Mode ___________________________________ 5 386 Registers _______________________________ 6 X87 Registers _______________________________ 6 Immediate Mode __________________________________ 6 Direct Mode _____________________________________ 7 Index Mode ______________________________________ 7 Implied Mode and Segment Override _______________ 8 x87 Operand Types _______________________________ 9 Macros ______________________________________________ 9 INLINE Code ________________________________________ 10 Local Labels _______________________________________ 10 Example ________________________________________ 11 Long Jump ______________________________________ 11 Supported Instructions _____________________________ 11 Hawkins Mnemonic Jumps _________________________ 11 Some Structure Constructs ______________________ 12 x86 and x87 Instructions _______________________ 12 Register Usage _____________________________________ 19 Assembler Internals ________________________________ 20 PostFix ________________________________________ 21 PreFix _________________________________________ 21 PASM Syntax Comparison _____________________________ 22 CODE Structure _____________________________________ 24 Regular Next ___________________________________ 24 Inline NEXT ___________________________________ 24 9-1 9-1 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ The assembler supports prefix syntax in an attempt to provide PASM, The F-PC Assembler PASM, The F-PC Assembler ________________________ a syntax which is more readable to programmers of other PASM.SEQ is an assembler which languages. The use of sequential is based on an 8086 assembler text file for source code published in Dr. Dobb's Journal, encourages the programmer to February 1982, by Ray Duncan. write programs in the vertical This assembler was subsequently code style with one statement modified by Robert L. Smith to per line. This style is what repair bugs, and support the traditional assembler requires. prefix assembler notation. Bob F-PC works well in this style, discovered a very simple method if you choose to do so. However, to let a postfix assembler to F-PC does not prevent you to assemble prefix code, by write in the horizontal code deferring assembly until the style, by which you can squeeze next assembler command or the many statements into one line end of line, when all the and make you own life miserable. arguments for the previous It supports postfix syntax to assembler command are piled on prevent alienating the the top of the data stack. Tom established base of F83 users. Zimmer has made additional modifications to allow syntax The prefix notation is close to switching, and to increase the original Intel assembly compatibility in postfix mode syntax, and certainly will be with the F83 Assembler. more familiar to programmers of other languages. All the code words defined in F-PC are coded PREFIX or POSTFIX ? PREFIX or POSTFIX ? ___________________ in the prefix notation. Please consider writing any new PASM supports dual syntaxes. assembly code you need in the The words PREFIX and POSTFIX prefix mode for distribution and switch between the two supported assimilation. modes. The postfix mode is very similar to F83's CPU8086 Assembler. Prefix mode, which is the default mode, allows a syntax which is much closer to MASM used by Intel and MicroSoft. 9-2 9-2 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ The assembly of a machine - 286/386 unique instruction is generally instructions. deferred to the following three - Extended (32 bit) size events: when the next assembly registers and memory. mnemonic is encountered, at the - Extra segment registers. end of a line, or when the command END-CODE or A; is Not Supported: executed. Therefore, a good style in writing code words in - ENTER, LEAVE. F-PC is to put one assembly - Long (2 byte) offset instruction in one line, conditional jumps. followed by the parameter - Extended (32 bit) specification or the arguments. addressing. Multiple assembly instructions - MOV with CRx or DRx are allowed in the same line, registers. except the assembly directives - Protected mode which build control structures instructions in general. in a code word, such as IF, ELSE, THEN, BEGIN, WHILE, AGAIN, etc. These directives must be Disassembler Disassembler ____________ the first or the only instruction in a line because In order to facilitate writing they act immediately, not assembler language (CODE) waiting for the next assembly definitions, DASM386.SEQ is a definitions, DASM386.SEQ is a ___________ instruction. It is a good ideal full disassembler for the 80386 to put these structure words in and the 80387 (numeric separate lines with proper processor). Beheading is used indentation so that the nested to minimize clutter but some structures in a code definition extra defitions are placed into can be perceived more readily. the DASM386 vocabulary. In the DASM386 vocabulary. In addition, the following words are defined in the FORTH are defined in the FORTH The 80386 and 80386SX The 80386 and 80386SX _____________________ vocabulary: The Intel 80286 offers little DM ( addr -- ) DM ( addr -- ) extra capability which is useful Display memory starting at in a Forth system. The address addr in DUMP ____ 386/386SX (and 486 when it is format. available) is a big step and does add capabilities which DIS ( addr -- ) DIS ( addr -- ) could be useful in FORTH - the Disassembler instructions least of which is 32 bit starting at address addr. ____ registers and operations which can be used to extend F-PC (F- IDIS ( n -- ) IDIS ( n -- ) TZ, etc.) into a 32 bit world. Disassemble the interrupt procedure whose interrupt number is n. _ PASM386.SEQ PASM386.SEQ ___________ SEEN ( addr -- ) SEEN ( addr -- ) This documentation reflects Disassembler F-PC CODE Version 1.0 of the 80386 Version 1.0 of the 80386 definitions starting at instruction implementation - address addr. If addr does ____ PASM386.SEQ. not point to a CODE definition, then control is Supported passed to the regular routine (SEE). _____ 9-3 9-3 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ SEE ( | name ) SEE ( | name ) CODE CODE This replaces the regular Define "name" as a new code SEE. It invokes SEEN to ___ ____ definition. Assembly perform disassembly. language follows, terminated by END-CODE. ________ The display and be paused by ______ entering a space or stopped by END-CODE END-CODE entering an escape. Terminates CODE ____ definitions, checks error conditions, and makes the code definition available PASM Glossary PASM Glossary _____________ for searching and execution. Here we will only give a small list of PASM words in this A; A; glossary. All assembly Completes the assembly of mnemonics are identical to those the previous instruction. defined in F83 8086 Assembler. All the structure directives and LOCAL_REF LOCAL_REF test conditions are also This functions sets the identical to those in F83. Only mode so that local labels the most important FORTH words will NOT cross CODE word will NOT cross CODE word controlling the assembler are boundaries. The local listed here. label mechanism is cleared each time a new CODE word PREFIX PREFIX is started. This is the Assert prefix mode for the default mode. following code definitions. GLOBAL_REF GLOBAL_REF POSTFIX POSTFIX This function sets the mode Assert postfix mode for the so that local labels can following code definitions. cross CODE definition boundaries. All local ASM.8086 ASM.8086 label definitions will be Assert 8086 mode for the available and the mechanism following code definitions is NOT reset at the is NOT reset at the - this is the default. beginning of a CODE This mode limits the definition. The local assembler to the (original) label mechanism must be 8086 limits, registers, reset with the CLEAR_LABELS ____________ etc. function before using global referencing mode. ASM.386 ASM.386 Assert 386 mode for the CLEAR_LABELS CLEAR_LABELS following code definitions. Clear the local label This mode permits 386 32bit mechanism to a clean or registers, 386 extra unused state in preparation segment registers, unique for using local labels. 386 instructions, and 386 This word need only be used extensions to existing if in the GLOBAL_REFS mode. ___________ instructions to be used. In the LOCAL_REFS mode, __________ CLEAR_LABELS is performed ____________ automatically. 9-4 9-4 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ BYTE BYTE # # Assemble current and indicates an immediate subsequent code using byte number. arguments, if register size is not explicitly #) #) specified. indicates swapping source and destination registers WORD WORD and/or memory addresses. Assemble current and subsequent code using 16 bit arguments, if register size is not explicitly Addressing Modes Addressing Modes ________________ specified. The most difficult problem in LABEL LABEL using 8086 assembler is to Start an assembly figure out the correct subroutine or mark the addressing mode and code it into current code address to be an instruction. You can get a referenced later. good ideal and probably figure out most of the addressing mode >PRE >PRE syntax from the above table. save the current prefix / However, there are cases the postfix setting and set table fells short. Here we will prefix. try to summarize the addressing syntax more systematically to PRE> PRE> show you how F-PC handles restore the previous prefix addresses in the prefix mode. / postfix setting. INLINE INLINE Register Mode Register Mode _____________ begin assembly code inside of a colon definition. Source or destination is a register in the CPU. The source END-INLINE END-INLINE registers specifications are: terminate assembly code inside of a colon definition and revert to AL BL CL DL AL BL CL DL normal colon compilation. AH BH CH DH AH BH CH DH AX BX CX DX AX BX CX DX INLINEON INLINEON SP BP SI DI SP BP SI DI turns generation of inline IP RP IP RP NEXT on. ____ CS DS SS ES CS DS SS ES INLINEOFF INLINEOFF Destination register turns generation of inline specifications are: NEXT off. ____ FAR FAR AL, BL, CL, DL, AL, BL, CL, DL, is used to designate an AH, BH, CH, DH, AH, BH, CH, DH, external segment jump. AX, BX, CX, DX, AX, BX, CX, DX, SP, BP, SI, DI, SP, BP, SI, DI, [] [] IP, RP, IP, RP, is used with FAR for long ___ CS, DS, SS, ES, CS, DS, SS, ES, labels. 9-5 9-5 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ Note that IP is the same as the Note that IP is the same as the __ The destination register SI register and that RP is the __ __ specifications are: same as the BP register. This __ additional register names are provided for compatibility with ST(0), ST(1), ST(0), ST(1), most Forth systems. ST(2), ST(3), ST(2), ST(3), ST(4), ST(5), ST(4), ST(5), ST(6), ST(7), ST(6), ST(7), 386 Registers 386 Registers _____________ In addition, the register The 32bit source registers specifications ST and ST, are specifications ST and ST, are specifications are: used in some instructions to specify an implied ST(0). specify an implied ST(0). _______ EAX EBX ECX EDX EAX EBX ECX EDX ESP EBP ESI EDI ESP EBP ESI EDI Immediate Mode Immediate Mode ______________ The 16bit source segment The argument is assembled as a registers specifications are: literal in the instruction. The immediate value must be preceded by the symbol #, which is a word _ CS DS SS ES CS DS SS ES and must be delimited by spaces: FS GS FS GS The 32bit destination registers MOV AX, # 1234 MOV AX, # 1234 specifications are: ADD CL, # 32 ADD CL, # 32 ROL AX, # 3 ROL AX, # 3 EAX, EBX, ECX, EDX, EAX, EBX, ECX, EDX, For some 386 instructions, 32- ESP, EBP, ESI, EDI, ESP, EBP, ESI, EDI, bit immediate data is expected and must be specified. This can The 16bit destination segment be specified and two successive registers specifications are: 16-bit values or a single double-value. For example: CS, DS, SS, ES, CS, DS, SS, ES, FS, GS, FS, GS, MOV EAX, # $1234 $5678 MOV EAX, # $1234 $5678 MOV EAX, # $5678.1234 MOV EAX, # $5678.1234 X87 Registers X87 Registers _____________ If a double value is specified, The support for the (floating note that it is stored in point) numeric processor such as reverse order on the stack. the 8087 and the 80387 add a number of register definitions to the assembler. The source register specifications are: ST(0) ST(1) ST(0) ST(1) ST(2) ST(3) ST(2) ST(3) ST(4) ST(5) ST(4) ST(5) ST(6) ST(7) ST(6) ST(7) 9-6 9-6 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ Direct Mode Direct Mode ___________ Examples are: An address is assembled into the instruction. This is used to CMP 2 [BP], SI CMP 2 [BP], SI specify an address to be jumped DEC 3 [SI] DEC 3 [SI] to or a memory location for data MOV BP, 0 [BX] MOV BP, 0 [BX] reference. The address is used directly as a 16 bit number. The following register index Depending on the instruction, specifications are allowed in F- the address may be assembled PC for source register unmodified or assembled as an designations: eight bit offset in the branch instructions. To jump or call beyond a 64K byte segment, the [SI] [IP] [SI] [IP] address must be preceded by [BP] [RP] [BP] [RP] FAR []. ______ [DI] [DI] [BX] [BX] Examples are: [BX+SI] [SI+BX] [BX+SI] [SI+BX] [BX+IP] [IP+BX] [BX+IP] [IP+BX] CALL FAR [] <label> CALL FAR [] <label> JMP <dest> JMP <dest> [BX+DI] [DI+BX] [BX+DI] [DI+BX] MOV BX, <source> MOV BX, <source> INC <dest> WORD INC <dest> WORD [BP+SI] [SI+BP] [BP+SI] [SI+BP] JZ <label> JZ <label> [BP+IP] [IP+BP] [BP+IP] [IP+BP] [RP+IP] [IP+RP] [RP+IP] [IP+RP] The destination address may be taken from the data stack [BP+DI] [DI+BP] [BP+DI] [DI+BP] directly: [RP+DI] [DI+RP] [RP+DI] [DI+RP] Destination registers are MOV CX, # 16 MOV CX, # 16 specified in a similar manner HERE ( save current code HERE ( save current code by: address on stack) address on stack) ... ... ... ... [SI], [IP], [SI], [IP], LOOPZ ( loop back to HERE if LOOPZ ( loop back to HERE if [BP], [RP], [BP], [RP], condition fails) condition fails) [DI], [DI], [BX], [BX], Index Mode Index Mode __________ [BX+SI], [SI+BX], [BX+SI], [SI+BX], [BX+IP], [IP+BX], [BX+IP], [IP+BX], One or two registers can be used as index registers to scan [BX+DI], [DI+BX], [BX+DI], [DI+BX], through data arrays. The contents of the index register [BP+SI], [SI+BP], [BP+SI], [SI+BP], or the sum of the contents of [BP+IP], [IP+BP], [BP+IP], [IP+BP], two index registers are added to form a base address, an offset [BP+DI], [DI+BP], [BP+DI], [DI+BP], is added to the base address to form the true address for data Note that the available reference. specifications are NOT symmetric. 9-7 9-7 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ There must be an offset number If you need to specify an preceding the index register address with a segment register specification, even if the other than the default implied offset is 0. This offset must offset is 0. This offset must ________________ register, use a segment override be specified even if the be specified even if the ________________________ instruction before the address instruction does not use it instruction does not use it ___________________________ specification: (e.g., the push and pop ____ ___ instructions can push/pop values indirectly or indexed but do not indirectly or indexed but do not CS: DS: ES: SS: CS: DS: ES: SS: use the offset). The 386 adds two more segment The 386 adds two more segment When the index register is used registers. These are similar to as destination, a comma must be the ES register and can be used the ES register and can be used __ appended immediately: in similar ways. The extra 386 segment over-rides are: MOV 0 [BX+IP], AX MOV 0 [BX+IP], AX FS: GS: FS: GS: 32-bit index registers require support of 32-bit addressing. Examples are: This is not currently supported. MOV ES: BP, SI MOV ES: BP, SI Implied Mode and Segment Implied Mode and Segment ________________________ CMP CS: 2 [BP], AX CMP CS: 2 [BP], AX Override Override ________ ADD AX, ES: 10 [BX+DI] ADD AX, ES: 10 [BX+DI] The implied mode is where The 8086 addressing modes are so mistakes are most likely to confusing that even experienced occur because you will have to programmer needs a good Intel be keenly aware of which segment 8086 manual to find the right register is used by the addressing mode and the F-PC instruction at any instance. assembler syntax table to Since the segment register is determine the correct argument implied and not stated list. explicitly, the bug generally can hide very securely The best way to write assembly underneath laughing at you. The code is still keeping the code code works when you test it but short and simple. It is very fails when the segment register easy in F-PC to break a long is modified. CODE definition into many small ____ fragments which are initially -- Branch and jump instructions defined as separate CODE ____ use CS segment register. definitions. After verifying that each fragment works, you -- Data movement instructions can edit out the CODE, NEXT, and ____ ____ use DS segment register. END-CODE lines to combine the ________ fragments into a single CODE ____ -- Stack instructions use SS definition. segment. -- String instructions use DS:SI as source and ES:DI as destination. 9-8 9-8 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ Charles Curley kindly Macros Macros ______ contributes an 8086 disassembler with a single step debugger. It Another area of interest is the is helpful to disassemble the macros. Here is the definition CODE word you defined and see ____ of the NEXT macro: what the computer thinks of what you mean. There is always this 'Do what I mean, not what I say' : NEXT >PRE JMP >NEXT A; : NEXT >PRE JMP >NEXT A; syndrome. Stepping through a PRE> ; PRE> ; piece of code one instruction at a time is the last thing you The macro itself is simply the have to do if everything else sequence JMP >NEXT. The _________ failed. surrounding words are used for support. Since PASM supports both postfix as well as prefix x87 Operand Types x87 Operand Types _________________ notation, it is not known on entry to a macro what mode is Many x87 instructions require selected. The words >PRE and ____ specifying a operand type PRE> select prefix, and restore ____ designation. The valid one are: the previous mode so macros will always be in prefix notation. The A; after >NEXT, forces the __ _____ REAL*4 REAL*4 assembly of the JMP instruction ___ REAL*8 REAL*8 before the mode switch. INTEGER*2 INTEGER*2 INTEGER*4 INTEGER*4 The standard predefined macros INTEGER*8 INTEGER*8 in PASM include NEXT (a JMP or ____ BCD BCD inline next function), 1PUSH _____ REAL_TEMP REAL_TEMP (pushes AX on the stack and then (pushes AX on the stack and then does NEXT), and 2PUSH (pushes ____ _____ If one is not specified but it DX, AX and then does NEXT). DX, AX and then does NEXT). ____ is needed, REAL*4 is assumed. is needed, REAL*4 is assumed. Normally, these are needed for instructions referencing memory - those with a floating point stack register specification do not need this (it is ignored). 9-9 9-9 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ INLINE Code INLINE Code ___________ Local Labels Local Labels ____________ INLINE allows us to include ______ To support large code machine code inside a high level definitions, Bob Smith colon definition. This is introduced 'local labels' to F- easily done in F-PC because it PC. The local labels are place is built on direct threaded markers $: preceded by a number. code. Every word is compiled as They are used to mark locations a code address in the colon in a large code definition for definition. The code in the forward and backward jumps and code field pointed to by the branches. They can be used code address is executed quite freely in a range of code directly because it is genuine words and reused to save head 8086 machine code. Whether the space by replacing LABELs which _____ code belongs to a colon have global names and cannot be definition or a code definition reused. does not make any difference. INLINE only has to compile the The use of local labels is best address pointing to the top of demonstrated by an example taken the dictionary in the code from the software floating point segment. The assembler can then package SFLOAT.SEQ by Bob Smith. be invoked to compile machine Up to 32 local labels can be code. If the code is terminated used to mark addresses of by NEXT or one of its ____ assembly code. They can be derivatives, the next word referred to before or after compiled in the colon definition their placements. They can be will be executed after the referenced across code word assembly code is done. END- ____ boundaries. The command LLAB- _____ INLINE only has to clean up the ______ INIT defines the boundary where ____ assembly environment and return the local label referencing the control back to the colon cannot cross. Between two compiler. consecutive LLAB-INIT, local _________ labels can be freely placed and Here is an example on how to use referenced. The LLAB-INIT _________ INLINE and END-INLINE to add function is from George Hawkins assembly code in the middle of a enhancement to PASM. It is colon definition: similar to the CLEAR-LABELS ____________ function in the original PASM. : TEST ( -- ) : TEST ( -- ) This technique is especially 5 0 DO 5 0 DO useful where the one-entry-one- I \ Get I \ Get exit dogma is very awkward when loop index loop index a piece of code has multiple INLINE INLINE entry points and can be shared pop ax \ pop I pop ax \ pop I among many code word add ax, # 23 \ add add ax, # 23 \ add definitions. It allows us to 23 23 construct structured spaghetti 1push \ push 1push \ push code, if there were such thing. sum sum END-INLINE END-INLINE . \ print . \ print results results LOOP LOOP ; ; 9-10 9-10 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ The implementation of local Supported Instructions Supported Instructions ______________________ labels in PASM has been enhanced by George Hawkins to correct some bugs as well as to add some features. For example, it is no Hawkins Mnemonic Jumps Hawkins Mnemonic Jumps ______________________ longer necessary to use LLAB- _____ INIT (or CLEAR-LABELS) to ____ ____________ George Hawkins has added a initialize since this will be number of mnemonic functions for done automatically by CODE. ____ jumping in assembler CODE ____ definitions. These additional definitions are: Example Example _______ J JMP J JMP Short jump labels: J0<> JNE J0<> JNE J0= JZ J0= JZ SUB AX, AX SUB AX, AX J0>= JNS J0>= JNS JNE 2 $ JNE 2 $ J0< JS J0< JS .... up to 127 bytes of .... up to 127 bytes of code code J<> JNE J<> JNE 2 $: MOV AX, BX 2 $: MOV AX, BX J= JZ J= JZ \ destination of short \ destination of short J>= JNL J>= JNL jump jump J< JNGE J< JNGE J> JNLE J> JNLE J<= JNG J<= JNG Long Jump Long Jump _________ JU>= JNC JU>= JNC A single long label (more than JU< JNAE JU< JNAE 127 bytes of code) is supported JU> JNBE JU> JNBE in each CODE definition. This ____ JU<= JNA JU<= JNA long jump label can only be used for forward addressing! An ___________________ These mnemonic jumps are very example is: useful with local labels. JMP L$ JMP L$ ..... any length ..... any length L$: MOV x, x L$: MOV x, x \ destination of long \ destination of long jump jump 9-11 9-11 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ Some Structure Constructs Some Structure Constructs _________________________ DS: 8086 Segment (prefix) DS: 8086 Segment (prefix) Override - points to the PASM supports a number of standard (default) data constructs for structured segment - normally the programming. These constructs same as CS: in F-PC and are similar to those available points to the beginning for colon definitions and of the CODE space. include the following: FS: 386 FS: 386 IF Segment (prefix) THEN Override ELSE GS: 386 GS: 386 BEGIN Segment (prefix) UNTIL Override AGAIN WHILE AAA ASCII Adjust after AAA ASCII Adjust after REPEAT Addition There is also some shorthand for AAD ASCII Adjust after AAD ASCII Adjust after comparison: Division AAM ASCII Adjust after AAM ASCII Adjust after 0= 0<> 0< 0>= 0= 0<> 0< 0>= Multiplication < >= <= > < >= <= > U< U>= U<= U> U< U>= U<= U> AAS ASCII Adjust after AAS ASCII Adjust after OV OV Subtraction CX<>0 CX<>0 ADC Arithmetic (integer) Add ADC Arithmetic (integer) Add with Carry x86 and x87 Instructions x86 and x87 Instructions ________________________ ADD Arithmetic (integer) ADD Arithmetic (integer) Addition The following gives a list of the 8086, 80286, 80386, 8087, AND (logical) and AND (logical) and 80287, and 80387 instructions supported by the F-PC assembler. BSF 386 BSF 386 Scan Bit Forward ES: 8086 Segment (prefix) ES: 8086 Segment (prefix) Override BSR 386 BSR 386 Scan Bit Reverse CS: 8086 Segment (prefix) CS: 8086 Segment (prefix) Override - Code Segment BT 386 BT 386 - points to F-PC's CODE Bit Test space. BTC 386 BTC 386 SS: 8086 Segment (prefix) SS: 8086 Segment (prefix) Bit Test and Complement Override - points to the Stack segment BTR 386 BTR 386 Bit Test and Reset BTS 386 BTS 386 Bit Test and Set CALL Call Procedure CALL Call Procedure 9-12 9-12 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ CBW Convert Byte to Word CBW Convert Byte to Word FCOMP x87 Compare FCOMP x87 Compare (real/integer and pop CLC Clear Carry Flag CLC Clear Carry Flag FCOMPP x87 Compare Real and Pop FCOMPP x87 Compare Real and Pop CLD Clear Direction Flag CLD Clear Direction Flag twice (increasing) FCOS 387 FCOS 387 CLI Clear Interrupt Flag CLI Clear Interrupt Flag Cosine of ST(0) (Disable) FDECSTP x87 Decrement stack FDECSTP x87 Decrement stack CLTS 386 CLTS 386 pointer Clear Task Switched Flag FDISI 8087 FDISI 8087 CMC Complement Carry Flag CMC Complement Carry Flag DISABLE interrupts CMP Compare Register/Memory CMP Compare Register/Memory FDIV x87 Divide FDIV x87 Divide with memory or (real/integer) Immediate. FDIVP x87 Divide Real and Pop FDIVP x87 Divide Real and Pop CMPS Compare String CMPS Compare String FDIVR x87 Divide FDIVR x87 Divide CMPSB Compare (byte) String CMPSB Compare (byte) String (real/integer) REVERSE CMPSD Compare (Dword) String CMPSD Compare (Dword) String FDIVRP x87 Divide Real Reverse FDIVRP x87 Divide Real Reverse and Pop CMPSW Compare (word) String CMPSW Compare (word) String FENI 8087 FENI 8087 CWD Convert Word to Dword CWD Convert Word to Dword ENABLE interrupts DAA Decimal Adjust after DAA Decimal Adjust after FFREE x87 Free Register FFREE x87 Free Register Addition FINCSTP x87 Increment Stack FINCSTP x87 Increment Stack DAS Decimal Adjust after DAS Decimal Adjust after pointer Subtraction FINIT x87 Initialize Processor FINIT x87 Initialize Processor DEC Decrement DEC Decrement FLD x87 Load FLD x87 Load DIV Unsigned divide DIV Unsigned divide (real/integer/bcd/temp_r eal) F2XM1 x87 (2**x)-1 F2XM1 x87 (2**x)-1 FLD1 x87 Load +1.0 FLD1 x87 Load +1.0 FABS x87 absolute value FABS x87 absolute value FLDCW x87 Load control word FLDCW x87 Load control word FABS, x87 - for compatability FABS, x87 - for compatability FLDENV x87 Load environment FLDENV x87 Load environment FADD x87 Add (real/integer) FADD x87 Add (real/integer) FLDL2E x87 Load LOG2(e) FLDL2E x87 Load LOG2(e) FADDP x87 Add Real and Pop FADDP x87 Add Real and Pop FLDL2T x87 Load LOG2(10) FLDL2T x87 Load LOG2(10) FCHS x87 Change Sign FCHS x87 Change Sign FLDLG2 x87 Load LOG10(2) FLDLG2 x87 Load LOG10(2) FCLEX x87 Clear Exceptions FCLEX x87 Clear Exceptions FLDLN2 x87 Load LOGe(2) FLDLN2 x87 Load LOGe(2) FCOM x87 Compare FCOM x87 Compare (real/integer) FLDPI x87 Load pi FLDPI x87 Load pi 9-13 9-13 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ FLDZ x87 Load +0.0 FLDZ x87 Load +0.0 FSUBR x87 Subtract FSUBR x87 Subtract (real/integer) REVERSE FMUL x87 Multiply FMUL x87 Multiply (real/integer) FSUBRP x87 Subtract real FSUBRP x87 Subtract real reverse and Pop FMULP x87 Multiply Real and FMULP x87 Multiply Real and Pop FTST x87 Test stack top FTST x87 Test stack top against +0.0 FNOP x87 no-operation FNOP x87 no-operation FUCOM 387 FUCOM 387 FPATAN x87 Partial Arctangent FPATAN x87 Partial Arctangent unordered compare FPREM x87 Partial Remainder FPREM x87 Partial Remainder FUCOMP 387 FUCOMP 387 unordered compare and FPREM1 387 FPREM1 387 pop Partial Remainder FUCOMPP 387 FUCOMPP 387 FPTAN x87 Partial Tangent FPTAN x87 Partial Tangent unordered Compare and Pop Twice FRNDINT x87 Round to Integer FRNDINT x87 Round to Integer FXAM x87 Examine stack top FXAM x87 Examine stack top FRSTOR x87 Restore saved state FRSTOR x87 Restore saved state FXCH x87 Exchange registers FXCH x87 Exchange registers FSAVE x87 Save state FSAVE x87 Save state FXTRACT x87 Extract exponent and FXTRACT x87 Extract exponent and FSCALE x87 Scale FSCALE x87 Scale significant FSIN 387 FSIN 387 FYL2X x87 Y*(LOG2(X)) FYL2X x87 Y*(LOG2(X)) Sine of ST(0) FYL2XP1 x87 Y*(LOG2(X+1)) FYL2XP1 x87 Y*(LOG2(X+1)) FSINCOS 387 FSINCOS 387 Sine and Cosine of ST(0) HLT Halt Processor ! HLT Halt Processor ! FSQRT x87 Square root FSQRT x87 Square root IDIV (integer) Signed Divide IDIV (integer) Signed Divide FSQRT, x87 -- for compat. FSQRT, x87 -- for compat. IMUL (integer) Signed IMUL (integer) Signed Multiply FST x87 Store (real/integer) FST x87 Store (real/integer) IN Input from an I/O Port IN Input from an I/O Port FSTCW x87 Store control word FSTCW x87 Store control word INC Increment INC Increment FSTENV x87 Store environment FSTENV x87 Store environment INS 386 INS 386 FSTP x87 Store FSTP x87 Store Input String - DX port (real/integer/BCD/temp_r eal) and Pop INSB 386 INSB 386 Input (byte) String - DX FSTSW x87 Store status word FSTSW x87 Store status word port FSUB x87 Subtract FSUB x87 Subtract INSD 386 INSD 386 (real/integer) Input (Dword) String - DX port FSUBP x87 Subtract real and FSUBP x87 Subtract real and pop INSW 386 INSW 386 Input (word) String - DX port 9-14 9-14 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ INT Call to Software- INT Call to Software- JNB Jump if Not Below JNB Jump if Not Below Interrupt Procedure (CF=0) INTO On Overflow, call INTO On Overflow, call JNBE Jump if Not Below or JNBE Jump if Not Below or interrupt procedure Equal (CF=0 and ZF=0) IRET Interrupt Return - IRET Interrupt Return - restore 16 bit regs JNC Jump if Not Carry JNC Jump if Not Carry (CF=0) IRETD 386 IRETD 386 Interrupt Return - JNE Jump if Not Equal JNE Jump if Not Equal restore 32 bit regs (ZF=0) (protected mode) JNG Jump if Not Greater JNG Jump if Not Greater JA Jump if Above JA Jump if Above (ZF=1 or SF<>OF) (CF=0 and ZF=0) JNGE Jump if Not Greater or JNGE Jump if Not Greater or JAE Jump if Above or Equal JAE Jump if Above or Equal Equal (CF=0) (SF<>OF) JB Jump if Below JB Jump if Below JNL Jump if Not Less JNL Jump if Not Less (CF=1) (SF=OF) JBE Jump if Below or Equal JBE Jump if Below or Equal JNLE Jump if Not Less or JNLE Jump if Not Less or (CF=1 or ZF=1) Equal (ZF=0 and SF=OF) JC Jump if Carry JC Jump if Carry (CF=1) JNO Jump if Not Overflow JNO Jump if Not Overflow (OF=0) JCXZ Jump if CX Register is JCXZ Jump if CX Register is Zero JNP Jump if Not Parity JNP Jump if Not Parity (PF=0) JE Jump if Equal JE Jump if Equal (ZF=1) JNS Jump if Not Sign JNS Jump if Not Sign (SF=0) JG Jump if Greater JG Jump if Greater (ZF=0 and SF=OF) JNZ Jump if Not Zero JNZ Jump if Not Zero (ZF=0) JGE Jump if Greater of Equal JGE Jump if Greater of Equal (SF=OF) JO Jump if Overflow JO Jump if Overflow (OF=1) JL Jump if Less JL Jump if Less (SF<>OF) JP Jump if Parity JP Jump if Parity (PF=1) JLE Jump if Less or Equal JLE Jump if Less or Equal (ZF=1 or SF<>OF) JPE Jump if Parity Even JPE Jump if Parity Even (PF=1) JMP Unconditional JUMP JMP Unconditional JUMP JPO Jump if Parity Odd JPO Jump if Parity Odd JNA Jump if Not Above JNA Jump if Not Above (PF=0) (CF=1 and ZF=1) JS Jump if Sign JS Jump if Sign JNAE Jump if Not Above or JNAE Jump if Not Above or (SF=1) Equal (CF=1) JZ Jump if Zero JZ Jump if Zero (ZF=1) 9-15 9-15 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ LAHF Load Flags into AH LAHF Load Flags into AH MOVSX 386 MOVSX 386 register move to reg with Sign Extension LDS Load pointer into DS LDS Load pointer into DS register MOVZX 386 MOVZX 386 move to reg with Zero LEA Load Effective Address LEA Load Effective Address Extension LES Load pointer into ES LES Load pointer into ES MUL Unsigned Multiply MUL Unsigned Multiply register NEG Negate NEG Negate LFS 386 LFS 386 Segment Register Load NOP No Operation NOP No Operation LGS 386 LGS 386 NOT (Logical) Not NOT (Logical) Not Segment Register Load OR (logical) Or OR (logical) Or LOCK Bus Lock LOCK Bus Lock OUT Write to I/O Port OUT Write to I/O Port LODS Load String LODS Load String OUTS 386 OUTS 386 LODSB Load (byte) String LODSB Load (byte) String Output String - DX port LODSD Load (Dword) String LODSD Load (Dword) String OUTSB 386 OUTSB 386 Output (byte) String - LODSW Load (word) String LODSW Load (word) String DX port LOOP Loop with CX as counter LOOP Loop with CX as counter OUTSD 386 OUTSD 386 Output (Dword) String - LOOPE Loop with CX as counter LOOPE Loop with CX as counter DX port and Equal OUTSW 386 OUTSW 386 LOOPNE Loop with CX as Counter LOOPNE Loop with CX as Counter Output (word) String - and NOT Equal DX port LOOPNZ Loop with CX as Counter LOOPNZ Loop with CX as Counter POP Pop off Stack POP Pop off Stack and NOT Zero POPA 386 POPA 386 LOOPZ Loop with CX as Counter LOOPZ Loop with CX as Counter Pop All 16 bit Registers and Zero POPAD 386 POPAD 386 LSS 386 LSS 386 Pop All 32 bit Registers Segment Register Load POPF Pop Flags off Stack POPF Pop Flags off Stack MOV Move MOV Move POPFD 386 POPFD 386 MOVS Move String MOVS Move String Pop 32 bit Flags off Stack MOVSB Move (byte) String MOVSB Move (byte) String PUSH Push onto Stack PUSH Push onto Stack MOVSD Move (Dword) String MOVSD Move (Dword) String PUSHA 386 PUSHA 386 MOVSW Move (word) String MOVSW Move (word) String Push All 16 bit Registers 9-16 9-16 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ PUSHAD 386 PUSHAD 386 SETAE 386 SETAE 386 Push All 16 bit SET if Above or Equal Registers (CF=0) PUSHF Push Flags onto Stack PUSHF Push Flags onto Stack SETB 386 SETB 386 SET if Below PUSHFD 386 PUSHFD 386 (CF=1) Push 32 bit Flags onto Stack SETBE 386 SETBE 386 SET if Below or Equal RCL Rotate through Carry RCL Rotate through Carry (CF=1 or ZF=1) Left SETC 386 SETC 386 RCR Rotate through Carry RCR Rotate through Carry SET if Carry Right (CF=1) REP Repeat REP Repeat SETE 386 SETE 386 SET if Equal REPE Repeat while Equal REPE Repeat while Equal (ZF=1) REPNE Repeat while Not Equal REPNE Repeat while Not Equal SETG 386 SETG 386 SET if Greater REPNZ Repeat while Not Zero REPNZ Repeat while Not Zero (ZF=0 and SF=OF) REPZ Repeat while Zero REPZ Repeat while Zero SETGE 386 SETGE 386 SET if Greater of Equal RET Return from Procedure RET Return from Procedure (SF=OF) RETF Return from Inter- RETF Return from Inter- SETL 386 SETL 386 Segment Procedure SET if Less (SF<>OF) ROL Rotate Left ROL Rotate Left SETLE 386 SETLE 386 ROR Rotate Right ROR Rotate Right SET if Less or Equal (ZF=1 or SF<>OF) SAHF Store AH into Flags SAHF Store AH into Flags SETNA 386 SETNA 386 SAL Shift Arithmetic Left SAL Shift Arithmetic Left SET if Not Above (CF=1 and ZF=1) SAR Shift Arithmetic Right SAR Shift Arithmetic Right SETNAE 386 SETNAE 386 SBB Subtract with Borrow SBB Subtract with Borrow SET if Not Above or Equal SCAS Scan String SCAS Scan String (CF=1) SCASB Scan (byte) String SCASB Scan (byte) String SETNB 386 SETNB 386 SET if Not Below SCASD Scan (Dword) String SCASD Scan (Dword) String (CF=0) SCASW Scan (word) String SCASW Scan (word) String SETNBE 386 SETNBE 386 SET if Not Below or SETA 386 SETA 386 Equal SET if Above (CF=0 and ZF=0) (CF=0 and ZF=0) 9-17 9-17 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ SETNC 386 SETNC 386 SETS 386 SETS 386 SET if Not Carry SET if Sign (CF=0) (SF=1) SETNE 386 SETNE 386 SETZ 386 SETZ 386 SET if Not Equal SET if Zero (ZF=0) (ZF=1) SETNG 386 SETNG 386 SHL Shift (logical) Left SHL Shift (logical) Left SET if Not Greater (ZF=1 or SF<>OF) SHLD 386 SHLD 386 Shift Left Double SETNGE 386 SETNGE 386 SET if Not Greater or SHR Shift (logical) Right SHR Shift (logical) Right Equal (SF<>OF) SHRD 386 SHRD 386 Shift Right Double SETNL 386 SETNL 386 SET if Not Less STC Set Carry Flag STC Set Carry Flag (SF=OF) STD Set Direction Flag STD Set Direction Flag SETNLE 386 SETNLE 386 (decreasing) SET if Not Less or Equal (ZF=0 and SF=OF) STI Set Interrupt Flag STI Set Interrupt Flag (enable) SETNO 386 SETNO 386 SET if Not Overflow STOS Store String STOS Store String (OF=0) STOSB Store (byte) String STOSB Store (byte) String SETNP 386 SETNP 386 SET if Not Parity STOSD Store (Dword) String STOSD Store (Dword) String (PF=0) STOSW Store (word) String STOSW Store (word) String SETNS 386 SETNS 386 SET if Not Sign SUB Subtract SUB Subtract (SF=0) TEST Logical Compare TEST Logical Compare SETNZ 386 SETNZ 386 SET if Not Zero WAIT Wait for Coprocessor WAIT Wait for Coprocessor (ZF=0) XCHG Exchange register with XCHG Exchange register with SETO 386 SETO 386 register/memory. SET if Overflow (OF=1) XLAT Table Lookup Translation XLAT Table Lookup Translation SETP 386 SETP 386 XOR (logical) Exclusive Or. XOR (logical) Exclusive Or. SET if Parity (PF=1) SETPE 386 SETPE 386 SET if Parity Even (PF=1) SETPO 386 SETPO 386 SET if Parity Odd (PF=0) 9-18 9-18 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ Register Usage Register Usage ______________ ES The extra segment ES The extra segment register - this is used in F-PC implements a virtual conjunction with the SI conjunction with the SI machine which uses the more or register to define the less standard set of current instruction. "registers": Therefore, it points somewhere within the LIST SP data stack pointer SP data stack pointer or X segment. This must be or X segment. This must be ____________ preserved by any code _____________________ RP return stack pointer RP return stack pointer words. ______ IP next word pointer IP next word pointer FS Another extra segment FS Another extra segment register valid only on the register valid only on the W current word pointer W current word pointer 80386. 80386. UP user area pointer - UP user area pointer - GS Another extra segment GS Another extra segment implemented as a VARIABLE. register valid only on the register valid only on the 80386. 80386. The following 80x8x register usage is made in F-PC: SP the SP or data stack SP the SP or data stack pointer -- used as SS:SP. pointer -- used as SS:SP. CS The code segment CS The code segment register used for any code BP the RP or return stack BP the RP or return stack definitions. This must be definitions. This must be ____________ pointer -- used as SS:BP. pointer -- used as SS:BP. preserved by any code _____________________ words. F-PC primitives and ______ ES:SI the IP or ES:SI the IP or basic operation depends on instruction pointer - both CS and DS having the both CS and DS having the points within the LIST or X same value. segment. Both the ES and segment. Both the ES and _______________ SI registers must be SI registers must be ____________________ DS The data segment DS The data segment preserved by a code ___________________ register used for any data definition. ___________ other than ." or "" other than ." or "" strings. This must be strings. This must be ____________ BX CX DX DI BX CX DX DI preserved by any code _____________________ scratch registers - can be words. F-PC primitives and ______ used without preserving in basic operation depends on a code definition - not both CS and DS having the both CS and DS having the assumptions are made about same value. their contents. SS The stack segment SS The stack segment EBX ECX EDX EDI EBX ECX EDX EDI register used with SP and register used with SP and 32-bit forms of the above BP to define the location BP to define the location scratch registers. of the F-PC stacks. This ____ must be preserved by any must be preserved by any ________________________ AX W or current word AX W or current word code words. Currently, F- ___________ pointer -- CS:AX points to pointer -- CS:AX points to PC sets this to the same the current machine code value as DS. value as DS. word on entry -- can be used as a scratch register since no assumptions are made about its contents. EAX the 32-bit form of the EAX the 32-bit form of the above register. 9-19 9-19 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ DF The Direction Flag DF The Direction Flag Although this was originally (used by string related based on Duncan's 8086 functions) -- assumed to be _____________ assembler, Robert L. Smith and 0 or increment. If the 0 or increment. If the _______________ Tom Zimmer have modified this direction flag is changed assembler to handle PREFIX in a code definition notation. This version is (through the use of the STD highly dependent in Zimmer's instruction), then it must Forth (F-PC, F-TZ, etc.). It is be reset (by the CLD interesting to note how much of instruction) before the end Duncan's original assembler (e.g., NEXT) of the code still exists in this package. definition. Since NEXT In fact, this assembler seems to uses the string instruction be closer to Duncan's original LODSW, disaster will result than assembler in Laxon&Perry's if the direction flag is F83. not set to 0. This assembler depends on the In general, CX is used for In general, CX is used for Kernel functions: counts, AX and DX are used for counts, AX and DX are used for data, and BX is used for data, and BX is used for RUN, addresses. For string DEFER, operations, DS:SI is used for operations, DS:SI is used for CREATE, the source and ES:DI is used for the source and ES:DI is used for and the destination. While DOES> following such conventions, be sure to restore such registers for its functioning. DEFER is _____ as are needed to preserve the used (among other things) to virtual FORTH machine provide the hooks for the meta- implemented by F-PC. compilation process. CREATE and ______ DOES> provide the capability to _____ Caution should be used when _______ create the defining words which using the extended (32 bit) define the instructions as well forms of register or the 386 as the register notations. RUN ___ extra segment registers. DOS and DEFER are used to create the _____ does not support these extended capability to handle the PREFIX capability to handle the PREFIX forms although everything should notation. work properly. The register operand functions F-PC currently uses a single define a set of words which use code segment of 64k bytes. The the register names as the CS, DS, and SS registers all CS, DS, and SS registers all definition names. At run-time, point to this single segment these definitions store values with the stacks being located at into a set of variables to the top (high addresses) of the indicate what registers have segment. been specified and what their order was. These information is used to complete the instruction at "instruction build" time. Assembler Internals Assembler Internals ___________________ The bulk of the assembler in F- PC is contained in the file PASM.SEQ -- there are some primitives to support the assembler in the Kernel. 9-20 9-20 The F-PC Assembler The F-PC Assembler !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ !"#$%&'()*+,-./0123456789:;<=>?@A...Z[\]^_`{|}~ The basic process of the PreFix PreFix ______ assembler uses the CREATE DOES> construct to create the code to The new PREFIX format modifies The new PREFIX format modifies handle both the register the process slightly - the definitions and the instruction instruction-word now occurs definitions. Each set of BEFORE the operand information. registers or instructions are To accommodate this format, the grouped into categories and a instruction-word saves the defining word is created for address of passed data and the each category. These defining address of a subroutine to build words create the definitions the instruction into a special (one for each register (internal) variable: APRIOR. (internal) variable: APRIOR. ______ specification or instruction) Execution of the save which (at run-time) creates the information is executed at a code which is the equivalent deferred time - this time can be instruction. My, how powerful when the next assembly this is in that the whole instruction mnemonic occurs, assembler is created using only when the END-CODE function is ________ FORTH (no CODE definitions). FORTH (no CODE definitions). executed or at the end of a physical line. At the "deferred time", the instruction has all PostFix PostFix _______ of the information necessary to build the correct code. The original POSTFIX format The original POSTFIX format process is fairly easy to understand. A defining word is created for each instruction category. This word contains the fixed (e.g., opcode) portion of the instruction as data in the CREATE part of the defining ______ word (the address of this data is passed to the run-time or DOES> code). Immediate data or _____ the addresses of VARIABLEs are placed on the stack. The register functions set other (internal) variables to values which indicate the register, register size, etc. The register specifications, immediate data, addresses, etc. must be place before the instruction. When the instruction-word is executed, it uses the data from the stack or internal variables together with the pre-compiled "opcode" data to assemble the instruction into memory. 9-21 9-21 The F-PC Assembler The F-PC Assembler PASM Syntax Comparison PASM Syntax Comparison ______________________ The differences among the F-PC prefix mode, the F83 postfix mode, and the Intel MASM notation are best illustrated by the following table. Although the table is not exhaustive, it covers most of the cases useful in doing PASM programming. 9-22 9-22 The F-PC Assembler The F-PC Assembler PREFIX POSTFIX MASM PREFIX POSTFIX MASM AAA AAA AAA ADC AX, SI SI AX ADC ADC AX,SI ADC DX, 0 [SI] 0 [SI] DX ADC ADC DX,0[SI] ADC 2 [BX+SI], DI DI 2 [BX+SI] ADC ADC 2[BX][SI],DI ADC MEM BX BX MEM #) ADC ADC MEM,BX ADC AL, # 5 5 # AL ADC ADC AL,5 AND AX, BX BX AX AND AND AX,BX AND CX, MEM CX MEM #) AND AND CX,MEM AND DL, # 3 3 # DL AND AND DL,3 CALL NAME NAME #) CALL CALL NAME CALL FAR [] NAME FAR [] NAME #) CALL ????? CMP DX, BX BX DX CMP CMP DX,BX CMP 2 [BP], SI SI 2 [BP] CMP CMP [BP+2],SI DEC BP BP DEC DEC BP DEC MEM MEM DEC DEC MEM DEC 3 [SI] 3 [SI] DEC DEC 3[SI] DIV CL CL DIV DIV CL DIV MEM MEM DIV DIV MEM IN PORT# WORD WORD PORT# IN IN AX,PORT# IN PORT# PORT# IN IN AL,PORT# IN AX, DX DX AX IN IN AX,DX INC MEM BYTE MEM INC INC MEM BYTE INC MEM WORD MEM #) INC INC MEM WORD INT 16 16 INT INT 16 JA NAME NAME JA JA NAME JNBE NAME NAME #) JNBE JNBE NAME JMP NAME NAME #) JMP JMP JMP FAR [] NAME NAME [] FAR JMP JMP [NAME] JMP FAR $F000 $E987 JMP F000:E987 LODSW AX LODS LODS WORD LODSB AL LODS LODS BYTE LOOP NAME NAME #) LOOP LOOP NAME MOV DX, NAME NAME #) DX MOV MOV DX,[NAME] MOV AX, BX BX AX MOV MOV AX,BX MOV AH, AL AL AH MOV MOV AH,AL MOV BP, 0 [BX] 0 [BX] BP MOV MOV BP,0[BX] MOV ES: BP, SI ES: BP SI MOV MOV ES:BP,SI MOVSW AX MOVS MOVS WORD POP DX DX POP POP DX POPF POPF POPF PUSH SI SI PUSH PUSH SI REP REP REP RET RET RET ROL AX, # 1 AX ROL ROL AX,1 ROL AX, CL AX CL ROL ROL AX,CL SHL AX, # 1 AX SHL SHL AX,1 XCHG AX, BP BP AX XCHG XCHG AX,BP XOR CX, DX DX, CX XOR XOR CX,DX 9-23 9-23 The F-PC Assembler The F-PC Assembler CODE Structure CODE Structure ______________ This structure is used for CODE definitions. The beginning ____ of the name field contains the length (n) of the name. of the name field contains the length (n) of the name. Regular Next Regular Next ____________ +--------------+ HEAD SPACE [ VIEW offset ] VIEW HEAD SPACE [ VIEW offset ] VIEW [ LINK pointer ] LINK [ 8n ] NAME [ . ] [ . ] n bytes long [ . + 80 hex ] Points to CODE space [ CFA pointer ] >-------+ +--------------+ | | +--------------+ | CODE SPACE [ . ] CFA <---+ CODE SPACE [ . ] CFA <---+ [ . ] [ . ] machine [ . ] code [ . ] [ . ] [ JMP ] end of CODE Points to LIST space [ NEXT ] definition +--------------+ Inline NEXT Inline NEXT ____________ +--------------+ HEAD SPACE [ VIEW offset ] VIEW HEAD SPACE [ VIEW offset ] VIEW [ LINK pointer ] LINK [ 8n ] NAME [ . ] [ . ] n bytes long [ . + 80 hex ] Points to CODE space [ CFA pointer ] >-------+ +--------------+ | | +--------------+ | CODE SPACE [ . ] CFA <---+ CODE SPACE [ . ] CFA <---+ [ . ] [ . ] machine [ . ] code [ . ] [ . ] [ ES: LODSW ] INLINE NEXT ___________ [ JMP AX ] end of definition +--------------+ 9-24 9-24