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- Tseng Super VGA
-
- ET3000-AX 512k 8/16 bit Main chip
- -BX 512k 8 bit
- -Bp 256k 8 bit Basic chip
- ET4000 1M 8/16 bit
-
-
- Registers:
-
- 102h: Microchannel Setup Control
- bit 0 Disable Card if set
-
- 3C0h index 16h: ATC Miscellaneous
- (Write data to 3C0h, Read from 3C1h (May not be needed))
- bit 4,5 High resoloutionn timings.
-
- 3C3h (R/W): Microchannel Video Subsystem Enable Register:
- bit 0 Enable Microchannel VGA if set
-
- 3C4h index 6 (R/W): Zoom Control (ET3000 Only)
- bit 0-2 Yzoom factor 0=1:1
- 4-6 Xzoom factor 0=1:1
- 7 Hardware zoom enabled if set
-
- 3C4h index 7 (R/W): TS Auxiliary Mode
- bit 0 (ET3000 Only) Switch Normal Window if set (Text/Graph)
- 1 (ET3000 Only) Switch Zoom Window if set (Text/Graph)
- 2 (ET3000 Only) Switch Split Window if set (Text/Graph)
- 4 (ET3000 Only) If set 8 simultaneous fonts are enabled,
- using bit 3,4,6 of each attribute byte
- to select the font.
- 3,5 Rom Bios Enable/Disable:
- 0 0 C000-C3FF Enabled
- 0 1 Rom disabled
- 1 0 C000-C5FF,C680-C7FF Enabled
- 1 1 C000-C7FF Enabled
- 6 MCLK/2 if set
- 7 VGA compatible if set EGA else.
-
- 3CBh (R/W): PEL Address/Data
-
- 3CDh (R/W): Segment Select
- bit 0-2 (ET3000) 64k Write bank nr
- 3-5 (ET3000) 64k Read bank nr
- 6-7 (ET3000) Segment Configuration.
- 0 128K segments
- 1 64K segments
- 2 1M linear memory
- 0-3 (ET4000) 64k Write bank nr (0..15)
- 4-7 (ET4000) 64k Read bank nr (0..15)
-
- 3d4h index 1Bh (R/W): X Zoom Start Address (ET3000 Only)
- bit 0-7 Offset of Zoom window start in character clocks
- (8 pixels) from left edge
-
- 3d4h index 1Ch (R/W): X Zoom End (ET3000 Only)
- bit 0-7 Offset of Zoom window end in char clocks from left edge
-
- 3d4h index 1Dh (R/W): Y Zoom Start Address (ET3000 Only)
- bit 0-7 Start line of zoom window bit 0-7
-
- 3d4h index 1Eh (R/W): Y Zoom End Address (ET3000 Only)
- bit 0-7 (ET3000 Only) End line of zoom window bit 0-7
-
- 3d4h index 1Fh (R/W): Y Zoom Start and End High (ET3000 Only)
- bit 0-2 End line of zoom window bit 8-10
- 3-5 Start line of zoom window bit 8-10
-
- 3d4h index 20h (R/W): Zoom Start Address Low (ET3000 Only)
- bit 0-7 Zoom Start Address bit 0-7
- Adress of Zoom data
-
- 3d4h index 21h (R/W): Zoom Start Address Middle (ET3000 Only)
- bit 0-7 Zoom Start Address bit 8-15
-
- 3d4h index 23h (R/W): Extended start ET3000 (ET3000 Only)
- bit 0 Cursor start adress bit 16
- 1 Display start adress bit 16
- 2 Zoom start adress bit 16
-
- 3d4h index 24h (R/W): Compatability Control
- bit 0 Enable Clock Translate
- 1 Additional Master Clock Select
- 2 Enable tri-state for all output pins
- 3 Enable input A8 of 1MB DRAMs
- 4 Reserved
- 5 Enable external ROM CRTC translation
- 6 Enable Double Scan and Underline Attribute
- 7 CGA/MDA/Hercules
-
- 3d4h index 25h (R/W): Overflow High ET3000 (ET3000 Only)
- bit 0 Vertical Blank Start bit 10
- 1 Vertical Total Start bit 10
- 2 Vertical Display End bit 10
- 3 Vertical Sync Start bit 10
- 4 Line Compare bit 10
- 5-6 Reserved
- 7 Vertical Interlace if set
-
- 3d4h index 32h (R/W): RAS/CAS Video Config
- Ram timing, System clock and Ram type. Sample values:
- 00h VRAM 80nsec
- 09h VRAM 100nsec
- 00h VRAM 28MHz
- 08h VRAM 36MHz
- 70h DRAM 40MHz
-
- 3d4h index 33h (R/W): Extended start ET4000 (ET4000 Only)
- bit 0-1 Display start adress bits 16-17
- 2-3 Cursor start adress bits 16-17
- Can be used to ID ET4000
-
- 3d4h index 34h (R/W): Compatibility Control Register
- bit 3 if set Video Subsystem Enable Register at 46E8h
- else at 3C3h.
-
- 3d4h index 35h (R/W): Overflow High ET4000 (ET4000 Only)
- bit 0 Vertical Blank Start Bit 10
- 1 Vertical Total Bit 10
- 2 Vertical Display End Bit 10
- 3 Vertical Sync Start Bit 10
- 4 Line Compare Bit 10
- 5 Gen-Lock Enabled if set (External sync)
- 6 Read/Modify/Write Enabled if set
- Currently not implemented.
- 7 Vertical interlace if set
-
- 3d4h index 36h (R/W): Video System Configuration 1
- bit 3 16 bit wide fonts if set, else 8 bit wide
- 4 (ET4000 Only) Linear adressing if set
- Video Memory is mapped as a 1 Meg block above 1MB.
- 6 16 bit data path (video memory) if set
- 7 16 bit data (I/O operations) if set
-
- 3d4h index 37h (R/W): Video System Configuration 2
- bit 0-1 Memory size 0,1=256k, 2=512k, 3=1M ???
- 3 Clear if 64kx4 RAMs ???
- if set RAM size = (bit 0-1)*256k
- else RAM size = (bit 0-1)* 64k
-
- 4 16 bit ROM access if set
- 5 Memory bandwidth (0 better than 1) ???
- 7 VRAM installed if set DRAM else.
- bit 6? Block read ahead (BRA) if clear
-
- 46E8h (R): Video Subsystem Enable Register
- bit 3 Enable VGA if set
-
-
- 3C4h index 05 used.
- 3CBh used. PEL Add/Dat. ??
- 3CEh index 0Dh-0Eh used.
-
-
- Bank Switching:
-
- 64k banks are selected by the Segment Select Register at 3CDh.
- Both a Read and a Write segment can be selected.
-
- Hardware Zoom (ET3000 Only).
-
- The ET3000 can zoom a part of display memory in a window.
- The display memory position and window position are selected
- by 3d4h index 1Bh to 21h.
-
-
- Identify Tseng Chipset:
-
- old:=port[$3CD];
- port[$3cd]:=$55;
- new:=port[$3cd];
- port[$3cd]:=old;
-
- if new=$55 then Tseng Chip !!!
-
-
- Identify Tseng 4000:
-
- if odd(port[$3cc]) then base:=$3d4 else base:=$3b4;
-
- port[base]:=$33;old_value:=port[base+1];
- new_value:=old_value xor 15;
- port[base+1]:=new_value;
- value:=port[base+1];
- port[base+1]:=old_value;
-
- if value=new_value then ET4000 chip !!!
-
-
- Video Modes:
- 8 T 132 25 2 (STB only)
- Ah T 132 44 2
-
- 18h T 132 44 4 (8x8) B000
- 19h T 132 25 4 (9x14) B000
- 1Ah T 132 28 4 (9x13) B000
- 22h T 132 44 16 (8x8)
- 23h T 132 25 16 (8x14)
- 24h T 132 28 16 (8x13)
- 25h G 640 480 16 planar
- 26h T 80 60 16 (8x8)
- 27h G 720 512 16 planar (Tseng recomanded, few boards)
- 29h G 800 600 16 planar
- 2Ah T 100 40 16 planar
- 2Dh G 640 350 256 packed
- 2Eh G 640 480 256 packed
- 2Fh G 640 400 256 packed (ET4000 Only)
- 2Fh G 720 512 256 packed (Tseng recomanded, few boards)
- 30h G 800 600 256 packed
- 36h G 960 720 16 planar (STB only)
- 37h G 1024 768 16 planar
- 38h G 1024 768 256 packed (ET4000 Only)
- 3Dh G 1280 1024 16 planar (newer ET4000s)
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- See Hicolor.doc for information about the Sierra HiColor RAMDAC.