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- Newsgroups: comp.unix.questions
- Path: sparky!uunet!sangam!cmie!rs
- From: rs@cmie.ernet.in (Rajappa Iyer)
- Subject: Re: easy make question
- Message-ID: <C1CunH.1MG@cmie.ernet.in>
- Organization: Centre for Monitoring Indian Economy, Bombay
- References: <1993Jan22.132144.165613@dstos3.dsto.gov.au> <JDELL.93Jan23121414@nefertiti.mit.edu>
- Date: Sun, 24 Jan 1993 11:02:04 GMT
- Lines: 38
-
- jdell@nefertiti.mit.edu (John Ellithorpe) writes:
-
- >On 22 Jan 93 13:21:42 CST, sct@crayfish.dsto.gov.au (Sean Troedson) said:
-
- >> has anyone used the wild card "%" in make? According to the man page you
- >> can use it in a target or dependency as in ...
-
- >> all: %.o
-
- >> file1.o:
- >> file2.o:
-
- >> but "make all" spits the dummy with "don't know how to make target `%.o'".
-
- `%' is not really a "wild-card" in the shell sense--it cannot be
- evaluated independently. From the manual: "... matches any string of
- zero or more characters in a target name or dependency in the target
- portion of a conditional macro definition, or within a pattern
- replacement macro reference."
-
- Perhaps the examples below will help clarify the same:
-
- SRCS=filea.c fileb.c
- OBJS=$(SRCS:%.c=%.o)
-
- OBJS will now expand to "filea.o fileb.o"
-
- Take another example:
-
- % : RCS/%,v
- $(CO) $(COFLAGS) $<
-
- Which says the any file, say, "filea.c" depends on "RCS/filea.c,v" and
- the command to extract it is "$(CO) $(COFLAGS) RCS/filea.c,v" (of
- course, with $(CO) and $(COFLAGS) replaced by their definitions.)
- --
- Rajappa Iyer rs@cmie.ernet.in (Preferred)
- riyer@shakti.ncst.ernet.in
-