home *** CD-ROM | disk | FTP | other *** search
- Path: sparky!uunet!enterpoop.mit.edu!eru.mt.luth.se!lunic!my2!glenn
- From: glenn@sm.luth.se (Glenn Jennings)
- Newsgroups: comp.lsi.cad
- Subject: Help with BDNET please
- Message-ID: <1485@my2.sm.luth.se>
- Date: 26 Jan 93 15:18:02 GMT
- Reply-To: Glenn Jennings <glenn@my.sm.luth.se>
- Organization: University of Lulea, Sweden
- Lines: 33
-
- For you OCTTOOLS experts, from a beginner: BDNET questions please !
-
- 1) is there something like BDSYN's "SYNONYM" function in BDNET to create new
- named (and local) bundles by picking and choosing bits from other
- bundles (bit vectors), for example:
-
- NEW_INTERNAL_SIGNAL<4:0> = IN_A<2> & IN_B<2> & IN_B<2> & LOCAL<3:2>;
-
- ...or something like this ? I hope the answer is not:
-
- a) I have to keep track of all individual bits myself in terms of their
- ultimate source or destination names:
- (in that case the problem still occurs if I want to tie a primary
- input directly to a primary output, doesn't it ?)
-
- or
-
- b) actually wire them through a dummy bdsyn module that does the
- bit-gathering for me and passes out my new bit vector...
-
- 2) does more complete BDNET documentation exist (more than the man pages
- distributed with OCTTOOLS) ?
-
- 3) using the scmos standard cells: anything resembling a gated transparent
- latch, or do I have to wire my own together ??
-
- PS I couldn't get BDSYN's "SYNONYM" (sic) function to work either...
-
- Thanks! Glenn J.
- Glenn Jennings Email: glenn@sm.luth.se
- Div. of Computer Engineering Tel: (+46) 920 91763
- Lulea University of Technology Alt: (+46) 920 91000
- S-951 87 Lulea, SWEDEN Fax: (+46) 920 97288
-