NetNews Usenet Archive 1993 #3/NN_1993_3.iso/spool/comp/arch/12411

Internet Message Format | 1993-01-27 | 1.9 KB

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From: [e-mail] (Dennis O'Connor)
Newsgroups: comp.arch
Subject: Re: Machines with cond. assignment instruction?
Message-ID: <[e-mail]>
Date: 26 Jan 93 18:21:51 GMT
References: <[e-mail]> <[e-mail]>
Organization: Intel i960(tm) Architecture
Lines: 40
NNTP-Posting-Host: potato.intel.com
In-reply-to: [e-mail]'s message of 25 Jan 93 08:24:32 GMT


[e-mail] (Shavit Amir) writes:
] Pradeep Dubey ([e-mail]) wrote:
] : Hello Everyone,
] : Are there announced machines (specially micros) with
] : some conditional assignment instruction.  I mean
] : instruction such as the following:
]
] : MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
]
] : where, c1 refers to some result of some previous compare.
]
] The above instruction is a 4 operand instruction, as the condition code is
] another implicit source operand. The best way to perform a conditional move
                       ^^^^
] is to have compares set or clear all the bits in a register.
] Once that is done, conditional moves are simple.
]
] AND R1, R2 -> R4    /* R1 containes the condition code */
] ANDNOT R1,R3 -> R4

? Why is
    TEST<cc>, tsrc1, tsrc2, tdst
    AND       tdst, msrc1, mdst
    ANDNOT    tdst, msrc2, mdst

"best" compared to

    TEST        tsrc1, tsrc2
    SELECT<cc>  msrc1, msrc2, mdst

Yes, the first avoids the CC-bits bottleneck, but multiple CCs could do that
without consuming an entire register (a la RS6000). It uses three intructions
instead of two, so it seems a loss to me.

Yes, the latter uses three inputs and one output, where one input
is the CCs. However, add-with-carry does this too, and most architectures
already have it, so it can't be a big deal.
--
Dennis O'Connor            [e-mail]