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- Newsgroups: comp.unix.bsd
- Path: sparky!uunet!psinntp!sugar!karl
- From: karl@NeoSoft.com (Karl Lehenbauer)
- Subject: Re: WD8003E ethernet card compatibility
- Organization: NeoSoft Communications Services -- (713) 684-5900
- Date: Tue, 22 Dec 1992 08:39:04 GMT
- Message-ID: <BznK14.AB8@NeoSoft.com>
- Keywords: AKCL Common LISP Kyoto Austin 386BSD
- References: <zxmsd01.724542361@studserv> <1gorbsINN8ku@neuro.usc.edu> <1992Dec22.001805.29535@alliant.com>
- Lines: 25
-
- In article <1992Dec22.001805.29535@alliant.com> rdr@cl4.alliant.com (Roger Roles) writes:
- >the buffer showed numerous differences. I "fixed" this (a truly gross hack,
- >probably with significant speed impact, but it works fast enough for my
- >purposes) by comparing every byte and rewriting it until the correct value
- >appeared in the board buffer. I limited the attempts to store the correct
- >value to the board to 10, so as to avoid an infinite loop if the board was
- >truly unable to receive the correct value. So far, the count of 10 limit
- >has never been reached.
-
- Sounds like you might have your bus running at too high of a speed.
-
- On a lot of the modern motherboards, you can select the speed to run the
- bus at. Everyone please read your motherboard manuals closely when
- configuring!
-
- On 50 MHz machines, bus speed is usually CLKI/6. On 33 MHz, CLKI/4.
- If you run a 50 MHz machine at CLK/4, you're clocking the bus at
- 12.5 MHz instead of the standard 8.
-
- And there are many similar variants, like make sure you're not caching
- the board's address space. Also in general that memory wait state and
- cache wait state numbers are correct.
- --
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