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- Newsgroups: comp.sys.mac.programmer
- Path: sparky!uunet!spool.mu.edu!enterpoop.mit.edu!mojo.eng.umd.edu!russotto
- From: russotto@eng.umd.edu (Matthew T. Russotto)
- Subject: Re: Why SUB when you can CLR?
- Message-ID: <1993Jan03.211823.2592@eng.umd.edu>
- Date: Sun, 03 Jan 93 21:18:23 GMT
- Organization: Project GLUE, University of Maryland, College Park
- References: <1993Jan3.205354.6419@hobbes.kzoo.edu>
- Lines: 32
-
- In article <1993Jan3.205354.6419@hobbes.kzoo.edu> k044477@hobbes.kzoo.edu (Jamie R. McCarthy) writes:
- >I've seen a lot of 680x0 code that clears registers by subtracting
- >them from themselves, i.e.
- > SUB.L D3, D3
- >instead of
- > CLR.L D3
- >
- >Even my C compiler produces code like this; there must be a
- >good reason. But I can't figure out what it is. According to
- >my 68000 book, "SUB.L <ea>, Rx" takes six cycles, or "eight, if
- >the effective address mode is register direct," which it is
- >in the example. So eight; that's for either address or data
- >registers. "CLR.L Rx" takes six.
- >
- >And they're both one-word instructions.
- >
- >So why not use CLR? This doesn't have anything to do with
- >incredibly obscure 68020+ pipelining timings, does it?
-
- How about MOVEQ #0, D3? That's FOUR cycles. And 'IL'ing at random, I
- do see a lot of that.
-
- SUB.L D0,D0 sure seems inappropriate, though I do remember certain
- Intel processors liking it (but my 80x86 reference and my plumbing
- didn't get along, and the plumbing won.....
- Anyone want a soggy and mildewed 80x86 reference?)
-
- --
- Matthew T. Russotto russotto@eng.umd.edu russotto@wam.umd.edu
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