NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/comp/sys/intel/2837

Text File | 1992-12-24 | 4.0 KB | 80 lines

Newsgroups: comp.sys.intel
Path: sparky!uunet!van-bc!sl
From: [e-mail] (Stuart Lynne)
Subject: Re: 486/66 .. Into a 486/50 motherboard?
Organization: Wimsey Information Services
Date: Thu, 24 Dec 1992 20:36:00 GMT
Message-ID: <[e-mail]>
References: <[e-mail]> <[e-mail]> <[e-mail]>
Lines: 69

In article <[e-mail]> [e-mail] (Thomas D. Barrett) writes:
>In article <[e-mail]> [e-mail] (Stuart Lynne) writes:

>>Once it does this it makes no difference whether you are running 33 or 50. You
>>are accessing the RAM as fast as you can. The *only* way that there would be
>>a difference would be if your RAM was fast enough to run without wait states
>>with a 50Mhz clock.

>>Since 20 nanosecond SRAM still needs wait states to run with 33 Mhz clock I
>>suspect it will be a while before DRAM gets fast enough to run with no
>>wait states at 50 Mhz :-)
>
>It depends on the design... 20ns SRAM can access data in 20ns.  Since
>the 33MHz cycle time is a minimum of 60ns, this leaves 40ns for the
>address to propogate out of the cpu (~15ns), to be looked-up in the
>tag (~20ns) and enough ready setup time for the 486 (~5ns)... it's tight,
>but it can work.  Some less expensive caches can't handle it and do
>have to use interleaving or adding of one waitstate.
>
>>Does anyone out there know how fast memory would have to be to be used without
>>wait states by a 50Mhz 486?
>
>If you mean SRAM... 20ns is plenty fast for the data for direct mapped
>caches.  But, the tags need to be about 10ns :)

Thanks for the info Tom. I'm the first to admit that I'm no hardware jockey.
My evidence for saying cache access needed wait states was remembering the CMOS
setup page for a 50MHz EISA machine we looked at back in September. It had
wait state setup for both RAM and Cache memory.

I've also seen results for testing the 486 with/without both the internal
and external cache. Internal alone is much faster then external alone. Bela
Lubkin at SCO reports in biz.sco.general:

In article <[e-mail]> [e-mail] <Bela Lubkin> writes:
>No, actually there's a much better one.  Simply disable the external
>cache completely, but *leave the internal cache enabled*.  Now, I
>realize that not all motherboard/BIOS combinations allow this, but if
>yours does, do it.  Remember those performance figures: no cache=1,
>external only=3, internal only=8, both=11.  So with internal only, you
>run about 75% of full speed, which is much better than (sometimes full
>speed) (sometimes 1/11 speed).
>
>(Those performance factors are from one very informal test, don't bother
>trying to hold me to them.  I know they're wrong for most purposes but
>they're right enough for purposes of making this decision).

We can assume two things from this. Either that the internal cache has been
implemented a lot better than external ones. Or that it's a bit better but
run's faster because the external needs wait states for access (perhaps only
for the tags though).

I think we can see that with proper board design there will be little difference
in memory access between 33Mhz and 50Mhz. Possibly a small difference for external
cache access if properly implemented with fast enough tag SRAM.

So the bottom line is if you need the extra CPU cycles that the DX2-66 gives you,
don't worry about loosing performance to to slower memory bus speed, as long
as you have a good quality motherboard which properly implements different wait
state configurations for 33Mhz vs. 50Mhz.

Interesting note. The turbo switch on some 486 boards just disables the cache
to make it look like a slower machine rather than changing the clock.

--
Stuart Lynne <[e-mail]> ......................... UNIX Facsimile Software
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