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Text File  |  1992-12-22  |  694 b   |  20 lines
  1. Newsgroups: comp.sys.intel
  2. Path: sparky!uunet!enterpoop.mit.edu!bloom-picayune.mit.edu!athena.mit.edu!jfc
  3. From: jfc@athena.mit.edu (John F Carr)
  4. Subject: Loading SS
  5. Message-ID: <1992Dec21.205245.13080@athena.mit.edu>
  6. Sender: news@athena.mit.edu (News system)
  7. Nntp-Posting-Host: achates.mit.edu
  8. Organization: Massachusetts Institute of Technology
  9. Date: Mon, 21 Dec 1992 20:52:45 GMT
  10. Lines: 8
  11.  
  12.  
  13. An 80?86 disables interrupts for the instruction following a load of the SS
  14. register, to allow for the stack pointer to be loaded.  What happens if the
  15. following instruction faults?  Even if it doesn't reference memory, there
  16. could be an instruction page fault.
  17.  
  18. --
  19.     John Carr (jfc@athena.mit.edu)
  20.