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- Path: sparky!uunet!spool.mu.edu!agate!darkstar.UCSC.EDU!cats.ucsc.edu!czmax
- From: czmax@cats.ucsc.edu (Max C. Pritikin)
- Newsgroups: comp.os.os2.misc
- Subject: Re: OS/2 Performance tip
- Date: 23 Dec 1992 04:36:18 GMT
- Organization: University of California, Santa Cruz
- Lines: 27
- Message-ID: <1h8qc2INNo3m@darkstar.UCSC.EDU>
- References: <15249.1716.uupcb@factory.com>
- NNTP-Posting-Host: si.ucsc.edu
-
-
- This isn't entirly on the subject, but oh well. :)
-
- I have been having troubles with my 386-40 (AMD) machine.
-
- Parity errors (blech.). I just bought 16 megs of memory and am
- really bummed, BUT. It doesn't seem to be the new memory.
-
- So, i've been trying out different CMOS settings, include disabling
- my cache (64k).
-
- I didn't think it would make much of a difference (as i'm multitasking
- and thought that the context switches would nuke most of the advantages
- of my cache anyway). WRONG ANSWER. I'd *guess* (i didn't try benchmarks
- yet) a factor of two speed difference.
-
- the questions: How is a CPU cache affected by context switches? (about
- how much code is involved in a switch? about how much code can
- run in a particular application before a switch, etc.)
-
- How to better track down the parity errors? (PS, i've reseated all
- my cards and DIPS and i've re-enabled the cache (machine wasn't as usable
- without it) and i've NOT had a parity error lately).
-
- thanks,
-
- -Max
-