NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/comp/lang/vhdl/619

Text File | 1992-12-30 | 3.9 KB | 164 lines

Newsgroups: comp.lang.vhdl
Path: sparky!uunet!mcsun!sun4nl!relay.philips.nl!cc03!ragon
From: [e-mail] (Pierre Ragon Cao/int 7317)
Subject: type conversion and configuration
Message-ID: <[e-mail]>
Originator: [e-mail]
Sender: [e-mail]
Organization: SERI-CEN Network Services, Philips C&P, Eindhoven, The Netherlands
X-Newsreader: Tin 1.1 PL5
Date: Wed, 30 Dec 1992 13:07:12 GMT
Lines: 151


Hi folks

I would be grateful if somebody can help with the following VHDL
examples.
I compiled them on VANTAGE spreadsheet and Model Technology V-System
and got different results.

-EXAMPLE 1
**********

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

PACKAGE bizarre IS

CONSTANT X : std_ulogic:= std_ulogic'(to_x01(bit_vector'("00"))(1));

CONSTANT Y : std_ulogic:= to_x01(bit_vector'("00"))(1);

END bizarre;

One of the tools gives the report below while the other compiles it OK.

Error: LINE 6 * More than one interpretation found for this indexed expression
Error: LINE 8 * More than one interpretation found for this indexed expression

My opinion is that there is no ambiguity.
At worse the indexing operation needs to explicitly know the type and then only
line 6 is OK.

-EXAMPLE 2
**********

-----------------------------------------
ENTITY circuit IS
END circuit;

-----------------------------------------
ENTITY framegen IS
PORT (
      dclreg  : IN bit_vector(7 DOWNTO 0)
     );
END framegen;

-----------------------------------------
ARCHITECTURE cpu68302 OF framegen IS

BEGIN --architecture
END cpu68302;

-----------------------------------------
ENTITY micint IS
PORT (
      dclreg  : OUT bit_vector(7 DOWNTO 0)
     );
END micint;

-----------------------------------------
ARCHITECTURE structural OF circuit IS
COMPONENT micint
PORT (
      dclreg  : OUT bit_vector(7 DOWNTO 0)
     );
END COMPONENT;

FOR c1:micint USE ENTITY WORK.micint(structural);

COMPONENT framegen

PORT (
      dclreg  : IN bit_vector(7 DOWNTO 0)
     );
END COMPONENT;

SIGNAL dclreg  : bit_vector(7 DOWNTO 0);

BEGIN

C1 : micint

PORT MAP(
       dclreg   =>  dclreg
        );

C2 : framegen

PORT MAP(
       dclreg   =>  dclreg
        );

END structural;

-----------------------------------------
ARCHITECTURE structural OF micint IS
BEGIN --architecture
END structural;

-----------------------------------------
CONFIGURATION conf68302_0 OF circuit IS
FOR structural
    FOR c2 : framegen
        USE ENTITY WORK.framegen(cpu68302);
    END FOR;
END FOR;
END conf68302_0;

DESCRIPTION

I have a testbench named circuit made of 2 components
framegen and micint.
The component c1 is bound to the entity micint by a
configuration specification.

The component c2 is bound to the entity framegen by
a configuration declaration.

For one tool i notice that if i reanalyze the architecture
of micint, then the configuration declaration must be reanalyzed,
whereas the other tool does not recompile the configuration.

Now per LRM PARAGRAPH 11.4 a given library unit is potentially
affected by a change in any library unit whose name is referenced
within the given library unit....
If a library unit is changed,then all library units potentially
affected by such changes must be reanalyzed before they can be
used again.

HERE micint is not referenced at all in configuration
called conf68302_0.
To my opinion there is no need to reanalyze the configuration
after a change in a design unit which does not affect it.


----------------------------------------------------------------
TO reach me via the net this line must be included in the file :
(no other sentence beginning with Subject : before the one below)

Subject : <RAGON:FRTRTS1>

and you send the file to : [e-mail]
using your mail program.

From : Pierre RAGON
       Philips Communication Systems
       5,avenue Reaumur
       BP21,BPI50
       92352 Le Plessis Robinson
       Cedex , FRANCE
       tel : [phone]
       fax : [phone]