NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/comp/lang/vhdl/609

Text File | 1992-12-22 | 3.8 KB | 154 lines

Newsgroups: comp.lang.vhdl
Path: sparky!uunet!clsi!kevin
From: [e-mail] (Kevin Cameron)
Subject: Re: wire primitives in VHDL
Message-ID: <[e-mail]>
Originator: kevin@dubhe
Sender: [e-mail]
Reply-To: [e-mail]
Organization: CAD Language Systems Inc.
References:  <[e-mail]>
Date: Wed, 23 Dec 92 01:35:59 GMT
Lines: 140


In article <[e-mail]>, [e-mail] (George Lippincott) writes:
>
> I am trying to figure out a way in VHDL to merge two bidirectional
> signals into one signal.  This is something that most of the major
> logic simulators let you do but which as far as I can tell is
> impossible in VHDL.
>
> This situation comes up when an entity is implemented in such a way
> that two bidirectional ports connect to the same signal.  What I
> would like to do is have some way to "short" these two signals together.
> Ideally the resolution function would see all of the drivers for
> both signals and calculate a value for both nets.
>
> This can be done in Verilog like this:
>         module wire(w,w)
>         inout w;
>         endmodule;
>
> I haven't been able to figure out a way to do the same thing in VHDL.
> If I use the code:
>         a <= b;
>         b <= a;
>
> Then a driver is added to both signals and the value gets stuck at 'U'
> due to the nature of the resolution function in the IEEE 1167 package.
>
> Does anyone have any idea on how to work around this?
>

I ran off the following VHDL for joining two "std_logic" resolved signals (hope
you find it some help - N.B. 'U' is sometimes mapped to 'Z' and intermediate
values appear in some deltas):

-- begin

library ieee;

use ieee.std_logic_1164.all;

architecture a of wire is
begin

    process
        variable res: std_ulogic_vector(1 to 2);
    variable drv: std_logic;
    begin

         w2 <= 'Z';
        w1 <= 'Z';

    wait for 0nS;

    if w1 = 'U' then
        drv    := w2;
        elsif w2 = 'U' then
        drv    := w1;
    else
        res(1) := w1;
        res(2) := w2;
            drv    := resolved(res);
    end if;

    if w1 = drv and w2 /= drv then
        w2 <= drv;
    end if;

        if w2 = drv and w1 /= drv then
        w1 <= drv;
    end if;

    wait until w1 /= w2;

end process;

end;

entity test_wire is
end;

library ieee;

use ieee.std_logic_1164.all;

architecture a of test_wire is
    signal a,b: std_logic;
    component wire port (w1,w2: inout std_logic);
    end component;
begin

    w1: wire port map (a,b);

    a <=    '1' after 1ns,
                 'L' after 2ns,
              'Z' after 3ns,
                       'H' after 14ns,
                          'Z' after 15ns;

    b <= 'Z',              'H' after 4ns,
                               'Z' after 7ns,
                       'U' after 12ns,
                       'H' after 14ns,
                          'Z' after 15ns;

end;

-- end

which gives:

      Time(fs) + Cycle     a    b
----------------------  ---- ----
                  0+ 0:  'U'  'U'
                  0+ 1: *'U' *'Z'
                  0+ 2: *'U'  'Z'
            1000000+ 0: *'1'  'Z'
            1000000+ 1: *'1' *'Z'
            1000000+ 2:  '1' *'1'
            2000000+ 0: *'L'  '1'
            2000000+ 1: *'L' *'Z'
            2000000+ 2:  'L' *'L'
            3000000+ 0: *'Z'  'L'
            3000000+ 1: *'Z' *'Z'
            4000000+ 0:  'Z' *'H'
            4000000+ 1: *'Z' *'H'
            4000000+ 2: *'H'  'H'
            7000000+ 0:  'H' *'Z'
            7000000+ 1: *'Z' *'Z'
           12000000+ 0:  'Z' *'U'
           12000000+ 1: *'Z' *'U'
           12000000+ 2:  'Z' *'U'
           14000000+ 0: *'H' *'H'
           15000000+ 0: *'Z' *'Z'

Kev.
--
Kevin Cameron          CLSI, Suite 100, 5457 Twin Knolls Rd., MD 21045, USA
[e-mail]         Tel: (USA) [phone] (- 5709) x224
uunet!clsi.com!kevin   Fax:       [phone]
-----------------------------------------------------------------------------