NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/comp/lang/verilog/484

Internet Message Format | 1992-12-22 | 1.6 KB

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From: [e-mail] (Michael Lodman)
Newsgroups: comp.lang.verilog
Subject: Re: execution of always blocks
Message-ID: <[e-mail]>
Date: 22 Dec 92 02:11:54 GMT
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In article <[e-mail]> [e-mail] (Steve Ehlers) writes:
>Which is fine if you only care about which ONE is last.  If you have
>three (or more) registers, you'll still have problems.  Using the
>non-blocking assignment operator ( <= ) will give you the behavior you want:
>
> always @(posedge Clk) c <= b;
> always @(posedge Clk) b <= a;

I've always wondered why Verilog, an HDL, had a blocking assignment as
the default to begin with. Early Verilog designs were excessively verbose,
with the creation of non-existant "registers" and wire delay terms to
get around this problem. The recent introduction of the non-blocking
assignemnt seems to me long overdue on the part of the language designers.

With the non-blocking assignemnt, what used to be somewhat tedious is now
a breeze as the model works exactly like I expect the hardware to.

--
Michael Lodman    Department of Computer Science Engineering
    University of California, San Diego
[e-mail]              [phone] x2627