home *** CD-ROM | disk | FTP | other *** search
- Newsgroups: comp.compilers
- Path: sparky!uunet!world!iecc!compilers-sender
- From: tm@netcom.com (Toshiyasu Morita)
- Subject: Difficult CPU architectures
- Reply-To: tm@netcom.com (Toshiyasu Morita)
- Organization: Netcom - Online Communication Services (408 241-9760 guest)
- Date: Wed, 23 Dec 1992 07:41:36 GMT
- Approved: compilers@iecc.cambridge.ma.us
- Message-ID: <92-12-098@comp.compilers>
- Keywords: architecture, question, comment
- Sender: compilers-sender@iecc.cambridge.ma.us
- Lines: 26
-
-
- I've yet to see a good 65816 C compiler and I was kind of wondering why...
-
- Does the fact that it has only a single accumulator and two index
- registers contribute significantly to the difficulty in generating good
- code? Or perhaps the fact that all CPU registers are 16-bit, and the
- address bus is 24-bits wide, and various addressing methods must be used
- to span the entire 16 meg addressing range? Or maybe because of the
- non-orthogonal CPU architecture where most of the addressing modes are
- usable with one or the other index register, but not both? Or maybe
- because the CPU has a "bank register" which controls the upper addressing
- bits in certain addressing modes? Or maybe because certain addressing
- modes only work on the first 64k of memory? Maybe the lack of hardware
- multiply and divide instructions?
-
- Any and all replies appreciated - thanks in advance.
-
-
- Toshi Morita
- tm@netcom.com
- [I'd attribute it more to the relatively small number of customers for a
- 65816 compiler. The Intel '86 line is nearly as difficult to compile for,
- but there are plenty of compilers anyway. -John]
- --
- Send compilers articles to compilers@iecc.cambridge.ma.us or
- {ima | spdcc | world}!iecc!compilers. Meta-mail to compilers-request.
-