NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/alt/sources/2866

Internet Message Format | 1992-12-23 | 111.2 KB

Path: sparky!uunet!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!rutgers!rochester!rit!moscom!pap
From: [e-mail] (Patrick Palmer)
Newsgroups: alt.sources
Subject: YAMPC (part 1/2)
Message-ID: <[e-mail]>
Date: 23 Dec 92 17:26:55 GMT
Organization: Moscom Corp., E. Rochester, NY
Lines: 3148
X-Newsreader: TIN [version 1.3 beta PL7]

Yet Another Microcode Program Compiler.  This is useful for learning
microcode programming.

Patrick
----
Patrick Palmer                                       Multimedia is the answer.
Slo-mo Mail: PO Box 23322, Rochester, NY 14692       What's the question?

--------CUT HERE---------
# This is a shell archive.  cd to an empty directory and feed to sh.
cat << 'Zaphod for prez' | sed 's/X\(.*\)X/\1/' > cmemory
XX
X; YAMPC Microcode Development KitX
X; Patrick PalmerX
XX
X.decimalX
XX
X;X
X;WRITE -  Write MAR into memoryX
X;|  READ - Read MAR address into MBRX
X;|  |  ASOURCE - Source for ABUSX
X;|  |  |  CCCNTRL - CC controlX
X;|  |  |  |  SHFTCTRL - shift controlX
X;|  |  |  |  |   ALUCTRL - Function from ALUX
X;|  |  |  |  |   |  ZDEST - Destination on ZBUSX
X;|  |  |  |  |   |  |  LOADFLAGS - Load FLAGS from ALUX
X;|  |  |  |  |   |  |  |  LOADHOLD - Load HOLD from ABUSX
X;|  |  |  |  |   |  |  |  |  TEST - Select bit from ALU status bitsX
X;|  |  |  |  |   |  |  |  |  |  COND - Type of next addressX
X;|  |  |  |  |   |  |  |  |  |  |    ADDRF - Address for micro jumpX
X;|  |  |  |  |   |  |  |  |  |  |    |    Decimal AddressX
X;|  |  |  |  |   |  |  |  |  |  |    |    |   Hex AddressX
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    CommentX
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    | X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;A  B  C  D  E   F  G  H  I  J  K    L    Dec Hex  RemX
X;******** Initialize PC to 0 ****************************************X
X 0  0  0  0  0  15  2  0  0  0  0    0  ; 0   00 ; PC    <- 0X
X 0  0  0  0  0  15  5  0  0  0  0    0  ; 1   01 ; FLAGS <- 0X
X 0  0  0  0  0  15  1  0  0  0  0    0  ; 2   02 ; AC    <- 0X
X 0  0  0  0  0  14  3  0  0  0  0    0  ; 3   03 ; SP    <- 0xFFX
X 0  0  0  0  0  15  6  0  0  0  0    0  ; 4   04 ; X     <- 0X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 5   05 ; goto fetchX
XX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 6   06 ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 7   07 ; nopX
XX
X;******** Fetch Next Instruction ***********************************X
X 0  1  2  0  0   1 10  0  0  0  0    0  ; 8   08 ; MAR <- PC; READX
X 0  1  2  0  0   9  2  0  0  0  0    0  ; 9   09 ; PC <- PC + 1; READX
X 0  0  9  0  0   1  4  0  0  0  6   12  ; 10  0a ; IR <- MBR;X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 11  0b ; nopX
X;                                                ; start instruction decodeX
X;                                                ; goto 12 + IR7 * 2 + IR6X
X 0  0  0  0  0   0  0  0  0  0  1  115  ; 12  0c ; IR76 00; goto 115X
X 0  0  0  0  0   0  0  0  0  0  1  115  ; 13  0d ; IR76 01; goto 115X
X 0  0  0  0  0   0  0  0  0  0  1   50  ; 14  0e ; IR76 10; goto 50X
X;X
X; OpCodes that have IR7=1 and IR6=1X
X 0  0  0  0  0   0  0  0  0  0  5   16  ; 15  0f ; test IR5, IR4X
X 0  0  0  0  0   0  0  0  0  0  1   20  ; 16  10 ; IR54 00; goto 20 X
X 0  0  0  0  0   0  0  0  0  0  1   32  ; 17  11 ; IR54 01; goto 32X
X 0  0  0  0  0   0  0  0  0  0  1   46  ; 18  12 ; IR54 10; goto 46X
X;X
X; HALT (1111 0000) - halt executionX
X 999 999 999 999 999 999 999 999 999 999 999 999 ; 19  13 ; DIE!!X
X;X
X; pop instructions  X
X 0  1  3  0  0   1 10  0  0  0  0    0  ; 20  14 ; MAR <- SP; READX
X 0  1  3  0  0   9  3  0  0  0  0    0  ; 21  15 ; SP <- SP + 1; READX
X 0  0  0  0  0   0  0  0  0  0  3   24  ; 22  16 ; test IR1, IR0X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 23  17 ; nopX
X 0  0  0  0  0   0  0  0  0  0  1   28  ; 24  18 ; IR10 00; goto 28 X
X 0  0  0  0  0   0  0  0  0  0  1   29  ; 25  19 ; IR10 01; goto 29 X
X 0  0  0  0  0   0  0  0  0  0  1   30  ; 26  1a ; IR10 10; goto 30 X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 27  1b ; IR10 11; goto 8; neverX
X;X
X; POP ACC (1100 0000) - pop accumulator off top of stackX
X 0  0  9  0  0   1  1  1  0  0  1  211  ; 28  1c ; ACC <- MBR; goto 211 X
X;X
X; POP X (1100 0001) - pop index register off top of stackX
X 0  0  9  0  0   1  6  0  0  0  1    8  ; 29  1d ; X <- MBR; goto 8 X
X;X
X; POP FLAGS (1100 0010) - pop flags off top of stackX
X 0  0  9  0  0   1  5  0  0  0  1    8  ; 30  1e ; FLAGS <- MBR; goto 8 X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 31  1f ; nopX
X;X
X; push instructionsX
X 0  0  3  0  0   2  3  0  0  0  0    0  ; 32  20 ; not SP X
X 0  0  3  0  0   9  3  0  0  0  0    0  ; 33  21 ; SP <- SP + 1 X
X 0  0  3  0  0   2  3  0  0  0  0    0  ; 34  22 ; not SP X
X 0  0  3  0  0   1 10  0  0  0  3   36  ; 35  23 ; MAR <- SP; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1   40  ; 36  24 ; IR10 00; goto 40 X
X 0  0  0  0  0   0  0  0  0  0  1   42  ; 37  25 ; IR10 01; goto 42 X
X 0  0  0  0  0   0  0  0  0  0  1   44  ; 38  26 ; IR10 10; goto 44 X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 39  27 ; IR10 11; goto 8; neverX
X;X
X; PUSH ACC (1101 0000) - push accumulator on stackX
X 1  0  1  0  0   1  9  0  0  0  0    0  ; 40  28 ; MBR <- ACC; WRITEX
X 1  0  0  0  0   0  0  0  0  0  1    8  ; 41  29 ; WRITE; goto 8X
X;X
X; PUSH X (1101 0001) - push index register on stackX
X 1  0  6  0  0   1  9  0  0  0  0    0  ; 42  2a ; MBR <- X; WRITEX
X 1  0  0  0  0   0  0  0  0  0  1    8  ; 43  2b ; WRITE; goto 8X
X;X
X; PUSH FLAGS (1101 0010) - push flags on stackX
X 1  0  5  0  0   1  9  0  0  0  0    0  ; 44  2c ; MBR <- FLAGS; WRITEX
X 1  0  0  0  0   0  0  0  0  0  1    8  ; 45  2d ; WRITE; goto 8X
X;X
X; RETN (1110 0000) - return from subroutineX
X 0  1  3  0  0   1 10  0  0  0  0    0  ; 46  2e ; MAR <- SP; READX
X 0  1  3  0  0   9  3  0  0  0  0    0  ; 47  2f ; SP <- SP + 1; READX
X 0  0  9  0  0   1  2  0  0  0  1    8  ; 48  30 ; PC <- MBR; goto 8 X
XX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 49  31 ; nopX
X;X
X; OpCodes that have IR7=1 and IR6=0X
X 0  0  0  0  0   0  0  0  0  0  5   52  ; 50  32 ; test IR5, IR4X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 51  33 ; nopX
X 0  0  0  0  0   0  0  0  0  0  1   59  ; 52  34 ; IR54 00; goto 59 X
X 0  0  0  0  0   0  0  0  0  0  1   71  ; 53  35 ; IR54 01; goto 71X
X 0  0  0  0  0   0  0  0  0  0  1   79  ; 54  36 ; IR54 10; goto 79X
X 0  0  0  0  0   0  0  0  0  0  1   87  ; 55  37 ; IR54 11; goto 87X
XX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 56  38 ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 57  39 ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 58  3a ; nopX
X;X
X; increment/decrement registersX
X 0  0  0  0  0   0  0  0  0  0  3   60  ; 59  3b ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1   70  ; 60  3c ; IR10 00; goto 70 X
X 0  0  0  0  0   0  0  0  0  0  1   69  ; 61  3d ; IR10 01; goto 69 X
X 0  0  0  0  0   0  0  0  0  0  1   66  ; 62  3e ; IR10 10; goto 66 X
X;X
X; DECX (1000 0011) - decrement index registerX
X 0  0  6  0  0   2  6  0  0  0  0    0  ; 63  3f ; not X X
X 0  0  6  0  0   9  6  0  0  0  0    0  ; 64  40 ; X <- X + 1X
X 0  0  6  0  0   2  6  0  0  0  1    8  ; 65  41 ; not X ; goto 8X
X;X
X; DECA (1000 0010) - decrement accumulatorX
X 0  0  1  0  0   2  1  0  0  0  0    0  ; 66  42 ; not ACC X
X 0  0  1  0  0   9  1  0  0  0  0    0  ; 67  43 ; ACC <- ACC + 1 X
X 0  0  1  0  0   2  1  1  0  0  1    8  ; 68  44 ; not ACC; goto 8X
X;X
X; INCX (1000 0001) - increment index registerX
X 0  0  6  0  0   9  6  0  0  0  1    8  ; 69  45 ; X <- X + 1; goto 8X
X;X
X; INCA (1000 0000) - increment accumulatorX
X 0  0  1  0  0   9  1  1  0  0  1    8  ; 70  46 ; ACC <- ACC + 1; goto 8X
X;X
X; clearing registersX
X 0  0  0  0  0   0  0  0  0  0  3   72  ; 71  47 ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1   76  ; 72  48 ; IR10 00; goto 76X
X 0  0  0  0  0   0  0  0  0  0  1   78  ; 73  49 ; IR10 01; goto 78X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 74  4a ; IR10 10; goto 8; never X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 75  4b ; IR10 11; goto 8; never X
X;X
X; CLRA (1001 0000) - clear accumulatorX
X 0  0 10  0  0   1  5  0  0  0  0    4  ; 76  4c ; FLAGS <- 00000100X
X 0  0  1  0  0  15  1  0  0  0  1    8  ; 77  4d ; ACC <- 0; goto 8X
X;X
X; CLRX (1001 0000) - clear index registerX
X 0  0  6  0  0  15  6  0  0  0  1    8  ; 78  4e ; X <- 0; goto 8X
X;X
X; ones/twos complementX
X 0  0  0  0  0   0  0  0  0  0  3   80  ; 79  4f ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1   84  ; 80  50 ; IR10 00; goto 84X
X 0  0  0  0  0   0  0  0  0  0  1   85  ; 81  51 ; IR10 01; goto 85X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 82  52 ; IR10 10; goto 8; never X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 83  53 ; IR10 11; goto 8; never X
X;X
X; NOT (1010 0000) - bitwise complement of accumulatorX
X 0  0  1  0  0   2  1  1  0  0  1  211  ; 84  54 ; not ACC; goto 211X
X;X
X; NEG (1010 0001) - 2's complement negation of the accumulatorX
X 0  0  1  0  0   2  1  0  0  0  0    0  ; 85  55 ; not ACCX
X 0  0  1  0  0   9  1  1  0  0  1  218  ; 86  56 ; ACC <- ACC + 1; goto 218X
X;X
X; shiftingX
X 0  0  0  0  0   0  0  0  0  0  4   88  ; 87  57 ; test IR3,IR2 X
X 0  0  0  0  0   0  0  0  0  0  1   95  ; 88  58 ; IR32 00; goto 95X
X 0  0  0  0  0   0  0  0  0  0  1  104  ; 89  59 ; IR32 01; goto 104X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 90  5a ; IR32 10; goto 8; never X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 91  5b ; IR32 11; goto 8; never X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 92  5c ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 93  5d ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 94  5e ; nopX
X 0  0  0  0  0   0  0  0  0  0  3   96  ; 95  5f ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1  100  ; 96  60 ; IR10 00; goto 100X
X 0  0  0  0  0   0  0  0  0  0  1  108  ; 97  61 ; IR10 01; goto 108X
X 0  0  0  0  0   0  0  0  0  0  1  102  ; 98  62 ; IR10 10; goto 102 X
X 0  0  0  0  0   0  0  0  0  0  1  111  ; 99  63 ; IR10 11; goto 111 X
X;X
X; SLL (1011 0000) - shift logical leftX
X 0  0  0  2  0   0  0  0  0  0  0    0  ; 100 64 ; clear shifterX
X 0  0  1  0  1   1  1  0  0  0  1  114  ; 101 65 ; lshift ACC; goto 114X
X;X
X; SRL (1011 0010) - shift logical rightX
X 0  0  0  2  0   0  0  0  0  0  0    0  ; 102 66 ; clear shifterX
X 0  0  1  0  2   1  1  0  0  0  1  114  ; 103 67 ; rshift ACC; goto 114X
X;X
X; SRA (1011 0100) - shift arithmetically rightX
X 0  0 10  0  0   0  0  0  1  0  0  128  ; 104 68 ; hold <- mask(10000000)X
X 0  0  1  0  1   4  0  0  0  0  0    0  ; 105 69 ; CC <- lshift(0x80&ACC)X
X 0  0  1  0  2   1  1  0  0  0  1  114  ; 106 6a ; rshift ACC; goto 114X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 107 6b ; nopX
X;X
X; SLC (1011 0001) - shift circular leftX
X 0  0 10  0  0   0  0  0  1  0  0  128  ; 108 6c ; hold <- mask(10000000)X
X 0  0  1  0  1   4  0  0  0  0  0    0  ; 109 6d ; CC <- lshift(0x80&ACC)X
X 0  0  1  0  1   1  1  0  0  0  1  114  ; 110 6e ; lshift ACC; goto 114X
X;X
X; SRC (1011 0011) - shift circular rightX
X 0  0 10  0  0   0  0  0  1  0  0    1  ; 111 6f ; hold <- mask(00000001)X
X 0  0  1  0  2   4  0  0  0  0  0    0  ; 112 70 ; CC <- rshift(0x01&ACC)X
X 0  0  1  0  2   1  1  0  0  0  0    0  ; 113 71 ; rshift ACCX
X;X
X; send ACC thru ALU to get proper flags because shifter is after ALUX
X 0  0  1  0  0   1  0  1  0  0  1  213  ; 114 72 ; ACC ; goto 213 X
X;X
X; OpCodes that have IR7=0X
X 0  0  0  0  0   0  0  0  0  0  3  116  ; 115 73 ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1  120  ; 116 74 ; IR10 00; goto 120X
X 0  0  0  0  0   0  0  0  0  0  1  126  ; 117 75 ; IR10 01; goto 126X
X 0  0  0  0  0   0  0  0  0  0  1  133  ; 118 76 ; IR10 10; goto 133 X
X;X
X; Mode is Stack (11) - addr <- (SP) + operandX
X 0  0  3  0  0   0  0  0  1  0  1  134  ; 119 77 ; hold <- SP; goto 134X
X;X
X; Mode is Direct (00) - addr <- operandX
X 0  1  2  0  0   1 10  0  0  0  0    0  ; 120 78 ; MAR <- PC; READX
X 0  1  2  0  0   9  2  0  0  0  0    0  ; 121 79 ; PC <- PC + 1; READX
X 0  0  9  0  0   1  7  0  0  0  0    0  ; 122 7a ; B <- MBRX
X 0  1  7  0  0   1 10  0  0  0  0    0  ; 123 7b ; MAR <- B; READX
X 0  1  0  0  0   0  0  0  0  0  0    0  ; 124 7c ; READX
X 0  0  0  0  0   0  0  0  0  0  1  139  ; 125 7d ; goto 139X
X;X
X; Mode is Indirect (01) - addr <- Memory[operand]X
X 0  1  2  0  0   1 10  0  0  0  0    0  ; 126 7e ; MAR <- PC; READX
X 0  1  2  0  0   9  2  0  0  0  0    0  ; 127 7f ; PC <- PC + 1; READX
X 0  1  9  0  0   1 10  0  0  0  0    0  ; 128 80 ; MAR <- MBR; READX
X 0  1  0  0  0   0  0  0  0  0  0    0  ; 129 81 ; READX
X 0  0  9  0  0   1  7  0  0  0  0    0  ; 130 82 ; B <- MBRX
X 0  1  7  0  0   1 10  0  0  0  0    0  ; 131 83 ; MAR <- B; READX
X 0  1  0  0  0   0  0  0  0  0  1  139  ; 132 84 ; READ; goto 139X
X;X
X; Mode is Indexed (10) - addr <- (X) + operandX
X 0  0  6  0  0   0  0  0  1  0  0    0  ; 133 85 ; hold <- XX
X 0  1  2  0  0   1 10  0  0  0  0    0  ; 134 86 ; MAR <- PC; READX
X 0  1  2  0  0   9  2  0  0  0  0    0  ; 135 87 ; PC <- PC + 1; READX
X 0  0  9  0  0   7  7  0  0  0  0    0  ; 136 88 ; B <- MBR + holdX
X 0  1  7  0  0   1 10  0  0  0  0    0  ; 137 89 ; MAR <- B; READX
X 0  1  0  0  0   0  0  0  0  0  0    0  ; 138 8a ; READX
X;X
X; Mode is loaded into register B, keep on decoding instructionX
X 0  0  0  0  0   0  0  0  0  0  6  140  ; 139 8b ; test IR7, IR6X
X 0  0  0  0  0   0  0  0  0  0  1  170  ; 140 8c ; IR76 00; goto 170X
X;X
X; pc changersX
X 0  0  5  0  0   0  0  0  1  0  0    0  ; 141 8d ; hold <- FLAGSX
X 0  0 10  0  0   4  8  0  0  0  0    4  ; 142 8e ; C <- hold & 00000100X
X 0  0  0  0  0   0  0  0  0  0  5  144  ; 143 8f ; test IR5, IR4X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 144 90 ; goto 8; neverX
X 0  0  0  0  0   0  0  0  0  0  1  162  ; 145 91 ; goto 162X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 146 92 ; goto 8; neverX
X;X
X; branchingX
X 0  0  0  0  0   0  0  0  0  0  4  148  ; 147 93 ; test IR3, IR2X
X;X
X; BR (0111 00aa) - branch alwaysX
X 0  0  7  0  0   1  2  0  0  0  1    8  ; 148 94 ; PC <- B; goto 8 X
X;X
X 0  0  0  0  0   0  0  0  0  0  1  154  ; 149 95 ; IR32 01; goto 154X
X 0  0  0  0  0   0  0  0  0  0  1  158  ; 150 96 ; IR32 10; goto 158X
X;X
X; BNEQ (0111 11aa) - branch if not zero (Z bit = 0)X
X 0  0  8  0  0   1  0  0  0  2  2  152  ; 151 97 ; C; test ZBIT (inverse)X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 152 98 ; 1; goto 8X
X 0  0  7  0  0   1  2  0  0  0  1    8  ; 153 99 ; 0; PC <- B; goto 8 X
X;X
X; BEQ (0111 01aa) - branch if zero (Z bit = 1)X
X 0  0  8  0  0   1  0  0  0  2  2  156  ; 154 9a ; C; test ZBIT (inverse)X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 155 9b ; nopX
X 0  0  7  0  0   1  2  0  0  0  1    8  ; 156 9c ; 1; PC <- B; goto 8 X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 157 9d ; 0; goto 8X
X;X
X; BLSS (0111 10aa) - branch if negative (N bit = 1) X
X 0  0 10  0  0   4  8  0  0  0  0    8  ; 158 9e ; C <- hold & 00001000X
X 0  0  8  0  0   1  0  0  0  2  2  160  ; 159 9f ; C ; test ZBITX
X 0  0  7  0  0   1  2  0  0  0  1    8  ; 160 a0 ; N 1; PC <- B; goto 8 X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 161 a1 ; N 0; goto 8X
X;X
X; CALL (0101 00aa) - jump to subroutineX
X 0  0  3  0  0   2  3  0  0  0  0    0  ; 162 a2 ; not SPX
X 0  0  3  0  0   9  3  0  0  0  0    0  ; 163 a3 ; SP <- SP + 1X
X 0  0  3  0  0   2  3  0  0  0  0    0  ; 164 a4 ; not SPX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 165 a5 ; nopX
X 0  0  3  0  0   1 10  0  0  0  0    0  ; 166 a6 ; MAR <- SPX
X 1  0  2  0  0   1  9  0  0  0  0    0  ; 167 a7 ; MBR <- PC; WRITEX
X 1  0  7  0  0   1  2  0  0  0  0    0  ; 168 a8 ; PC <- B; WRITEX
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 169 a9 ; goto 8X
X;X
X; OpCodes that have IR7=0 and IR6=0X
X 0  0  0  0  0   0  0  0  0  0  5  172  ; 170 aa ; test IR5, IR4X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 171 ab ; nopX
X 0  0  0  0  0   0  0  0  0  0  1  185  ; 172 ac ; IR54 00; goto 185X
X 0  0  0  0  0   0  0  0  0  0  1  195  ; 173 ad ; IR54 01; goto 195X
X 0  0  0  0  0   0  0  0  0  0  1  207  ; 174 ae ; IR54 10; goto 207X
X;X
X; storingX
X 0  0  0  0  0   0  0  0  0  0  4  176  ; 175 af ; test IR3, IR2X
X 0  0  0  0  0   0  0  0  0  0  1  181  ; 176 b0 ; IR32 00; goto 181X
X;X
X; STX (0011 01aa) - store index registerX
X 0  0  7  0  0   1 10  0  0  0  0    0  ; 177 b1 ; MAR <- BX
X 1  0  6  0  0   1  9  0  0  0  0    0  ; 178 b2 ; MBR <- X; WRITEX
X 1  0  0  0  0   0  0  0  0  0  0    0  ; 179 b3 ; WRITEX
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 180 b4 ; goto 8X
X;X
X; STA (0011 00aa) - store accumulatorX
X 0  0  7  0  0   1 10  0  0  0  0    0  ; 181 b5 ; MAR <- BX
X 1  0  1  0  0   1  9  0  0  0  0    0  ; 182 b6 ; MBR <- ACC; WRITEX
X 1  0  0  0  0   0  0  0  0  0  0    0  ; 183 b7 ; WRITEX
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 184 b8 ; goto 8X
X;X
X; math (add/subtract)X
X 0  0  0  0  0   0  0  0  0  0  4  188  ; 185 b9 ; test IR3, IR2X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 186 ba ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 187 bb ; nopX
X 0  0  0  0  0   0  0  0  0  0  1  193  ; 188 bc ; IR32 00; goto 193X
X;X
X; SUB (0000 01aa) - subtract from accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 189 bd ; hold <- MBRX
X 0  0  1  0  0   2  1  0  0  0  0    0  ; 190 be ; not ACCX
X 0  0  1  0  0   7  1  0  0  0  0    0  ; 191 bf ; ACC <- ACC + holdX
X 0  0  1  0  0   2  1  1  0  0  1    8  ; 192 c0 ; not ACC; goto 8X
X;X
X; ADD (0000 00aa) - add to accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 193 c1 ; hold <- MBRX
X 0  0  1  0  0   7  1  1  0  0  1    8  ; 194 c2 ; ACC <- ACC+hold; goto 8X
X; X
X; logicX
X 0  0  0  0  0   0  0  0  0  0  4  196  ; 195 c3 ; test IR3, IR2X
X 0  0  0  0  0   0  0  0  0  0  1  202  ; 196 c4 ; IR32 00; goto 202X
X 0  0  0  0  0   0  0  0  0  0  1  200  ; 197 c5 ; IR32 01; goto 200X
X;X
X; AND (0001 10aa) - logical AND to accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 198 c6 ; hold <- MBRX
X 0  0  1  0  0   4  1  1  0  0  1  211  ; 199 c7 ; ACC <- ACC&hold; goto211X
X;X
X; XOR (0001 01aa) - logical XOR to accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 200 c8 ; hold <- MBRX
X 0  0  1  0  0   6  1  1  0  0  1  211  ; 201 c9 ; ACC <- ACC^hold; goto211X
X;X
X; OR (0001 00aa) - logical OR to accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 202 ca ; hold <- MBRX
X 0  0  1  0  0   5  1  1  0  0  1  211  ; 203 cb ; ACC <- ACC|hold; goto211X
XX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 204 cc ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 205 cd ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 206 ce ; nopX
X;X
X; loadingX
X 0  0  0  0  0   0  0  0  0  0  4  208  ; 207 cf ; test IR3, IR2X
X;X
X; LDA (0010 00aa) - load accumulatorX
X 0  0  9  0  0   1  1  1  0  0  1  211  ; 208 d0 ; ACC <- MBR; goto 211 X
X;X
X; LDX (0010 01aa) - load index registerX
X 0  0  9  0  0   1  6  0  0  0  1    8  ; 209 d1 ; X <- MBR; goto 8X
X;X
X; LDS (0010 10aa) - load stack registerX
X 0  0  9  0  0   1  3  0  0  0  1    8  ; 210 d2 ; SP <- MBR; goto 8X
X;X
X; set bits 'VC' to zero in flags registerX
X 0  0 10  0  0   0  0  0  1  0  0  252  ; 211 d3 ; hold <- 11111100X
X 0  0  5  0  0   4  5  0  0  0  1    8  ; 212 d4 ; FLAGS<-hold&FLGS; goto 8X
X;X
X; set bit 'V' to zero in flags registerX
X 0  0  0  0  1  15  7  0  0  0  0    0  ; 213 d5 ; B <- CCX
X 0  0  7  0  0   0  0  0  1  0  0    0  ; 214 d6 ; hold <- BX
X 0  0  5  0  0   5  5  0  0  0  0    0  ; 215 d7 ; FLAGS <- hold | FLAGSX
X 0  0 10  0  0   0  0  0  1  0  0  253  ; 216 d8 ; hold <- 11111101X
X 0  0  5  0  0   4  5  0  0  0  1    8  ; 217 d9 ; FLAGS<-hold&FLGS; goto 8X
X;X
X; set bit 'C' to zero in flags registerX
X 0  0 10  0  0   0  0  0  1  0  0  254  ; 218 da ; hold <- 11111110X
X 0  0  5  0  0   4  5  0  0  0  1    8  ; 219 db ; FLAGS<-hold&FLGS; goto 8X
XX
X; That's All Folks!X
Zaphod for prez
cat << 'Zaphod for prez' | sed 's/X\(.*\)X/\1/' > hfile
XBEGINX
XFORMATX
X    write[1],X
X    read[1],X
X    asource[4],X
X    cccntrl[2],X
X    shftcntrl[2],X
X    alufunc[4],X
X    zdest[4],X
X    ldflags[1],X
X    ldhold[1],X
X    test[2],X
X    cond[3],X
X    addrf[9];X
XX
XPARTSX
X    pc[8], ac[8], sp[8], ir[8], flags[8],X
X    rx[8], rb[8], rc[8], alu[8], mbr[8], mar[8], hold[8],X
X    shifter[8], abus[8], zbus[8], *mpc[10], cc[1],X
X    nbit[1], zbit[1], vbit[1], cbit[1];X
XX
XVARSX
X    garbage[8], temp[8], temp2[8], temp3[8];X
XX
XMEMORYX
X    cpu[512], mem[256][8];X
XX
XSUBCYCLEX
X    subcycle = 2;X
XX
XINITX
X    sp = 0xaa;X
X    pc = 0xaa;X
X    mpc = 0; X
X    garbage = 0xaa;X
X    hold = 0xaa;X
XX
XMICROENGINEX
Xif ( subcycle == 1 ) {X
XX
X    /* Set value on ABUS */X
XX
X    abus = garbage;X
XX
X    temp3 = ( addrf & 0x0ff );X
XX
X    switch ( asource ) {X
X        case 0: abus = garbage; break;X
X        case 1: abus = ac; break;X
X        case 2: abus = pc; break;X
X        case 3: abus = sp; break;X
X        case 4: abus = ir; break;X
X        case 5: abus = flags; break;X
X        case 6: abus = rx; break;X
X        case 7: abus = rb; break;X
X        case 8: abus = rc; break;X
X        case 9: abus = mbr; break;X
X        case 10: abus = temp3; break;X
X    }X
XX
X    /* Set value in HOLD register */X
XX
X    if ( ldhold ) {X
X        hold = abus;X
X    }X
XX
X    /* Set ALU function */X
X    X
X    switch ( alufunc ) {X
X        case 0:    alu = hold; break;X
X        case 1:    alu = abus; break;X
X        case 2:    alu = ( ~ abus ) - 1; break;X
X        case 3:    alu = hold + abus + 1; break;X
X        case 4:    alu = hold & abus; break;X
X        case 5:    alu = hold | abus; break;X
X        case 6:    alu = hold ^ abus; break;X
X        case 7:    alu = hold + abus; break;X
X        case 8:    alu = hold + 1; break;X
X        case 9: alu = abus + 1; break;X
X        case 10: alu = ( ~ hold ) - 1; break;X
X        case 11: alu = abus & 1; break;X
X        case 12: alu = abus - hold; break;X
X        case 13: alu = hold & 1; break;X
X        case 14: alu = -1; break;X
X        case 15: alu = 0; break;X
X    }X
X}X
XX
Xif ( subcycle == 2 ) {X
XX
X    /* Set Condition Codes */X
X    nbit = 0; zbit = 0; vbit = 0; cbit = 0;X
X    temp = alu;X
XX
X    temp2 = temp & 0x80;X
X    if ( temp2 != 0) nbit = 1;X
XX
X    temp2 = temp & 0xff;X
X    if ( temp2 == 0 ) zbit = 1;X
XX
X    temp2 = temp & 0x1ff00;X
X    if ( temp2 != 0 ) cbit = 1;X
XX
X    switch ( alufunc ) {X
X        case 0:X
X        case 1:X
X        case 2: break;X
X        case 3: alu = hold + abus + 1; break;X
X        case 4:X
X        case 5:X
X        case 6: break;X
X        case 7: if (((hold & 0x80) == 0) && ((abus & 0x80) == 0))X
X                if (nbit != 0 ) vbit = 1;X
X            if (((hold & 0x80) != 0) && ((abus & 0x80) != 0))X
X                if (nbit != 1 ) vbit = 1;X
X            break;X
X        case 8:    if ((hold & 0x80 ) == 0 )X
X                if ( nbit != 0 ) vbit = 1;X
X            break;X
X        case 9: if ((abus & 0x80 ) == 0)X
X                if ( nbit != 0 ) vbit = 1;X
X            break;X
X        case 10:X
X        case 11: break;X
X        case 12: if (((hold & 0x80 ) != 0) && ((abus & 0x80) == 0))X
X                if ( nbit != 0 ) vbit = 1;X
X             if (((hold & 0x80 ) == 0) && ((abus & 0x80) != 0))X
X                if ( nbit != 1 ) vbit = 1;X
X             break;X
X        case 13:X
X        case 14:X
X        case 15: break;X
X    }X
XX
X    /* set CC bit for the shifter */X
XX
X    switch ( cccntrl ) {X
X        case 0: break;X
X        case 1: cc = 1; break;X
X        case 2: cc = 0; break;X
X        case 3: cc = cbit; break;X
X    }X
XX
X    /* Load FLAGS from status of ALU */X
XX
X    if ( ldflags ) {X
X        flags = cbit + ( 2 * vbit ) + ( 4 * zbit ) + ( 8 * nbit );X
X    }X
XX
X    /* set output of shifter to zbus */X
XX
X    shifter = alu;X
XX
X    temp = cc;X
XX
X    switch ( shftcntrl ) {X
X        case 1:    if ( shifter & 0x80 ) cc =1;X
X            else cc = 0;X
X            shifter = shifter << 1;X
X            shifter = shifter + temp;X
X            break;X
X        case 2: cc = shifter & 1;X
X            shifter = shifter >> 1;X
X            if ( temp ) shifter = shifter | 0x80;X
X            break;X
X        default:X
X            break;X
X    }X
XX
X    zbus = shifter;X
XX
X    /* store zbus into any specified register */X
XX
X    if ( zdest != 0 ) X
X        switch ( zdest ) {X
X            case 0: garbage = zbus; break;X
X            case 1: ac = zbus; break;X
X            case 2: pc = zbus; break;X
X            case 3: sp = zbus; break;X
X            case 4: ir = zbus; break;X
X            case 5: flags = zbus; break;X
X            case 6: rx = zbus; break;X
X            case 7: rb = zbus; break;X
X            case 8: rc = zbus; break;X
X            case 9: mbr = zbus; break;X
X            case 10: mar = zbus; break;X
X        }X
XX
X    /* Set MBR for reads */X
XX
X    if ( write ) {X
X        if ( zdest <= 9 ) mem[mar] = mbr;X
X        else mem[mar] = garbage;X
X    }X
X    if ( read ) {X
X        if ( zdest <= 9 ) mbr = mem[mar];X
X        else mbr = garbage;X
X    }X
XX
X    /* determine select bit from the current ALU flag settings */X
XX
X    switch ( test ) {X
X        case 0:    temp = cbit; break;X
X        case 1:    temp = vbit; break;X
X        case 2:    temp = zbit; break;X
X        case 3:    temp = nbit; break;X
X    }X
XX
X    /* Determine next value of MPC */X
XX
X    switch ( cond ) {X
X        case 0: mpc = mpc + 1; break;X
X        case 1: mpc = addrf; break;X
X        case 2: mpc = ( addrf & 0x3fe ) + temp; break;X
X        case 3: temp3 = ( ir & 0x03 );X
X            mpc = (addrf & 0x1fc ) + temp3; break;X
X        case 4: temp3 = ( ir & 0x0c ) >> 2;X
X            mpc = ( addrf & 0x1fc ) + temp3; break;X
X        case 5: temp3 = ( ir & 0x30 ) >> 4;X
X            mpc = ( addrf & 0x1fc ) + temp3; break;X
X        case 6: temp3 = ( ir & 0xc0 ) >> 6;X
X            mpc = ( addrf & 0x1fc ) + temp3; break;X
X        default: mpc = 9999; break;X
X    }X
X}X
XX
XENDX
Zaphod for prez
cat << 'Zaphod for prez' | sed 's/X\(.*\)X/\1/' > license.gnu
XX
XX
X                    GNU GENERAL PUBLIC LICENSEX
X                       Version 2, June 1991X
XX
X Copyright (C) 1989, 1991 Free Software Foundation, Inc.X
X                          675 Mass Ave, Cambridge, MA 02139, USAX
X Everyone is permitted to copy and distribute verbatim copiesX
X of this license document, but changing it is not allowed.X
XX
X                            PreambleX
XX
X  The licenses for most software are designed to take away yourX
Xfreedom to share and change it.  By contrast, the GNU General PublicX
XLicense is intended to guarantee your freedom to share and change freeX
Xsoftware--to make sure the software is free for all its users.  ThisX
XGeneral Public License applies to most of the Free SoftwareX
XFoundation's software and to any other program whose authors commit toX
Xusing it.  (Some other Free Software Foundation software is covered byX
Xthe GNU Library General Public License instead.)  You can apply it toX
Xyour programs, too.X
XX
X  When we speak of free software, we are referring to freedom, notX
Xprice.  Our General Public Licenses are designed to make sure that youX
Xhave the freedom to distribute copies of free software (and charge forX
Xthis service if you wish), that you receive source code or can get itX
Xif you want it, that you can change the software or use pieces of itX
Xin new free programs; and that you know you can do these things.X
XX
X  To protect your rights, we need to make restrictions that forbidX
Xanyone to deny you these rights or to ask you to surrender the rights.X
XThese restrictions translate to certain responsibilities for you if youX
Xdistribute copies of the software, or if you modify it.X
XX
X  For example, if you distribute copies of such a program, whetherX
Xgratis or for a fee, you must give the recipients all the rights thatX
Xyou have.  You must make sure that they, too, receive or can get theX
Xsource code.  And you must show them these terms so they know theirX
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X  We protect your rights with two steps: (1) copyright the software, andX
X(2) offer you this license which gives you legal permission to copy,X
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X   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATIONX
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Xrestrictions on the recipients' exercise of the rights granted herein.X
XYou are not responsible for enforcing compliance by third parties toX
Xthis License.X
XX
X  7. If, as a consequence of a court judgment or allegation of patentX
Xinfringement or for any other reason (not limited to patent issues),X
Xconditions are imposed on you (whether by court order, agreement orX
Xotherwise) that contradict the conditions of this License, they do notX
Xexcuse you from the conditions of this License.  If you cannotX
Xdistribute so as to satisfy simultaneously your obligations under thisX
XLicense and any other pertinent obligations, then as a consequence youX
Xmay not distribute the Program at all.  For example, if a patentX
Xlicense would not permit royalty-free redistribution of the Program byX
Xall those who receive copies directly or indirectly through you, thenX
Xthe only way you could satisfy both it and this License would be toX
Xrefrain entirely from distribution of the Program.X
XX
XIf any portion of this section is held invalid or unenforceable underX
Xany particular circumstance, the balance of the section is intended toX
Xapply and the section as a whole is intended to apply in otherX
Xcircumstances.X
XX
XIt is not the purpose of this section to induce you to infringe anyX
Xpatents or other property right claims or to contest validity of anyX
Xsuch claims; this section has the sole purpose of protecting theX
Xintegrity of the free software distribution system, which isX
Ximplemented by public license practices.  Many people have madeX
Xgenerous contributions to the wide range of software distributedX
Xthrough that system in reliance on consistent application of thatX
Xsystem; it is up to the author/donor to decide if he or she is willingX
Xto distribute software through any other system and a licensee cannotX
Ximpose that choice.X
XX
XThis section is intended to make thoroughly clear what is believed toX
Xbe a consequence of the rest of this License.X
XX
X  8. If the distribution and/or use of the Program is restricted inX
Xcertain countries either by patents or by copyrighted interfaces, theX
Xoriginal copyright holder who places the Program under this LicenseX
Xmay add an explicit geographical distribution limitation excludingX
Xthose countries, so that distribution is permitted only in or amongX
Xcountries not thus excluded.  In such case, this License incorporatesX
Xthe limitation as if written in the body of this License.X
XX
X  9. The Free Software Foundation may publish revised and/or new versionsX
Xof the General Public License from time to time.  Such new versions willX
Xbe similar in spirit to the present version, but may differ in detail toX
Xaddress new problems or concerns.X
XX
XEach version is given a distinguishing version number.  If the ProgramX
Xspecifies a version number of this License which applies to it and "anyX
Xlater version", you have the option of following the terms and conditionsX
Xeither of that version or of any later version published by the FreeX
XSoftware Foundation.  If the Program does not specify a version number ofX
Xthis License, you may choose any version ever published by the Free SoftwareX
XFoundation.X
XX
X  10. If you wish to incorporate parts of the Program into other freeX
Xprograms whose distribution conditions are different, write to the authorX
Xto ask for permission.  For software which is copyrighted by the FreeX
XSoftware Foundation, write to the Free Software Foundation; we sometimesX
Xmake exceptions for this.  Our decision will be guided by the two goalsX
Xof preserving the free status of all derivatives of our free software andX
Xof promoting the sharing and reuse of software generally.X
XX
X                            NO WARRANTYX
XX
X  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTYX
XFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHENX
XOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIESX
XPROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSEDX
XOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OFX
XMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK ASX
XTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THEX
XPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,X
XREPAIR OR CORRECTION.X
XX
X  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITINGX
XWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/ORX
XREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,X
XINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISINGX
XOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITEDX
XTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BYX
XYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHERX
XPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THEX
XPOSSIBILITY OF SUCH DAMAGES.X
XX
X                     END OF TERMS AND CONDITIONSX
XX
X        Appendix: How to Apply These Terms to Your New ProgramsX
XX
X  If you develop a new program, and you want it to be of the greatestX
Xpossible use to the public, the best way to achieve this is to make itX
Xfree software which everyone can redistribute and change under these terms.X
XX
X  To do so, attach the following notices to the program.  It is safestX
Xto attach them to the start of each source file to most effectivelyX
Xconvey the exclusion of warranty; and each file should have at leastX
Xthe "copyright" line and a pointer to where the full notice is found.X
XX
X    <one line to give the program's name and a brief idea of what it does.>X
X    Copyright (C) 19yy  <name of author>X
XX
X    This program is free software; you can redistribute it and/or modifyX
X    it under the terms of the GNU General Public License as published byX
X    the Free Software Foundation; either version 2 of the License, orX
X    (at your option) any later version.X
XX
X    This program is distributed in the hope that it will be useful,X
X    but WITHOUT ANY WARRANTY; without even the implied warranty ofX
X    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theX
X    GNU General Public License for more details.X
XX
X    You should have received a copy of the GNU General Public LicenseX
X    along with this program; if not, write to the Free SoftwareX
X    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.X
XX
XAlso add information on how to contact you by electronic and paper mail.X
XX
XIf the program is interactive, make it output a short notice like thisX
Xwhen it starts in an interactive mode:X
XX
X    Gnomovision version 69, Copyright (C) 19yy name of authorX
X    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.X
X    This is free software, and you are welcome to redistribute itX
X    under certain conditions; type `show c' for details.X
XX
XThe hypothetical commands `show w' and `show c' should show the appropriateX
Xparts of the General Public License.  Of course, the commands you use mayX
Xbe called something other than `show w' and `show c'; they could even beX
Xmouse-clicks or menu items--whatever suits your program.X
XX
XYou should also get your employer (if you work as a programmer) or yourX
Xschool, if any, to sign a "copyright disclaimer" for the program, ifX
Xnecessary.  Here is a sample; alter the names:X
XX
X  Yoyodyne, Inc., hereby disclaims all copyright interest in the programX
X  `Gnomovision' (which makes passes at compilers) written by James Hacker.X
XX
X  <signature of Ty Coon>, 1 April 1989X
X  Ty Coon, President of ViceX
XX
XThis General Public License does not permit incorporating your program intoX
Xproprietary programs.  If your program is a subroutine library, you mayX
Xconsider it more useful to permit linking proprietary applications with theX
Xlibrary.  If this is what you want to do, use the GNU Library GeneralX
XPublic License instead of this License.X
Zaphod for prez
cat << 'Zaphod for prez' | sed 's/X\(.*\)X/\1/' > memory
X; YAMPC test memoryX
X; YAMPC distribution packageX
X20 ; 0 load direct acc from 20 - all address in hexX
X20 ; 1 address 20X
X00 ; 2 add direct 21 to accX
X21 ; 3 address 21X
X80 ; 4 increment accX
X04 ; 5 subtract direct 22 from accX
X22 ; 6 address 22X
X30 ; 7 store direct acc into 23X
X23 ; 8X
X90 ; 9 clear accX
X80 ; a increment accX
X82 ; b decrement accX
X82 ; c decrement accX
X30 ; d store in 24X
X24 ; eX
X91 ; f clear xX
X83 ;10 dec xX
X81 ;11 inc xX
X81 ;12 inc xX
X34 ;13 store x in 25X
X25 ;14X
Xf0 ;15 haltX
X00 ;16 nopX
X00 ;17 nopX
X00 ;18 nopX
X00 ;19 nopX
X00 ;1a nopX
X00 ;1b nopX
X00 ;1c nopX
X00 ;1d nopX
X00 ;1e nopX
X00 ;1f nopX
X44 ;20X
X21 ;21X
X15 ;22X
Xaa ;23 -- 51 load/add/sub/storX
Xaa ;24 -- ff inc/dec accX
Xaa ;25 -- 01 inc/dec xX
XX
XX
Zaphod for prez
cat << 'Zaphod for prez' | sed 's/X\(.*\)X/\1/' > tmac.ine
X.\"X
X.\" TROFF MACRO DEFINTIONX
X.\" Patrick Palmer, January 31, 1992X
X.\"X
X.\" MACRO: Start typewriter fontX
X.de YSX
X.fp 2 CX
X.cs C 24X
X.nfX
X.ft CX
X..X
X.\" MACRO: End typewriter fontX
X.de YEX
X.ft PX
X.fiX
X.cs CX
X.fp 2 IX
X..X
X.\" MACRO: New PageX
X.de NPX
X.ev 1        \" change the environmentX
X'sp 0.5i    \" go down half wayX
X.ft R        \" set title font to RomanX
X.ps 10        \" set size to 10pX
X.po 0.5i    \" set page offsetX
X.lt 7i        \" set length to 7 inchesX
X.tl '''\\*(BS'X
X'bp        \" page breakX
X'sp 1iX
X.vs 3p        \" set vertical spacing to noneX
X.if o .tl '''\\*(TY    %'X
X.if e .tl '%    \\*(TZ'''X
X\l'7i'X
X.vsX
X.poX
X.psX
X.ev        \" restore the environmentX
X'sp 0.3iX
X..X
X.\" MACRO: Title at bottom page, right sideX
X.de PBX
X.ds BS \\$1X
X..X
X.\" MACRO: Title at top of page, right side, odd pageX
X.de POX
X.ds TY \\$1X
X..X
X.\" MACRO: Title at top of page, right side, even pageX
X.de PEX
X.ds TZ \\$1X
X..X
X.\" MACRO: New paragraphX
X.de PPX
X.spX
X..X
X.\" MACRO: Section PartX
X.de SPX
X.ne 1i        \" new page first if with 2 inches of bottomX
X.mkX
X.ll 1.75i    \" set line length to 1 3/4 inchesX
X.po 0.5iX
X.ps 12X
X\\$1X
X.brX
X.psX
X.llX
X.poX
X.rtX
X..X
X.\" MACRO: Section TitleX
X.de STX
X.SP "\fB\\$1\fP"X
X..X
X.\" MACRO: Section Part Right JustifyX
X.de SRX
X.ad r        \" right justifyX
X.SP "\\$1"X
X.ad l        \" left justifyX
X..X
X.\" MACRO: Update Start (mark in margin update changes)X
X.de USX
X.mc \s12\(br\s0X
X..X
X.\" MACRO: Update EndX
X.de UEX
X.mcX
X..X
X.\" MACRO: Full PageX
X.de FPX
X.ll 7iX
X.po 0.5iX
X..X
X.\ MACRO: Page FormattedX
X.de PFX
X.ll 5i        \" line length is 5 inchesX
X.po 2.5i    \" page offset set to 2 3/4 inchesX
X..X
X.\"X
X.\" DEFAULT DEFINITIONSX
X.PFX
X.ps 11X
X.wh -1i NPX
X.ad l        \" produce flush-left, ragged-right outputX
XX
XX
Zaphod for prez
cat << 'Zaphod for prez' | sed 's/X\(.*\)X/\1/' > yampc.1
X.TH YAMPC 1X
X.SH NAMEX
XYAMPC \- Yet Another Micro Program CompilerX
X.SH SYNOPSISX
X.B yampcX
XfileX
X.B X
X.SH DESCRIPTIONX
X.I YampcX
Xis a compiler to convert the hardware description file of theX
Xdesired architecture into C.X
XOnce the architecture is compiled by X
X.I yampcX
Xand the C compiler, the microprogramming systemX
Xcan be used to simulate the particular hardware using X
Xmicrocode.X
X.I YampcX
Xis the first step in creating the microprogramming system.X
X.PPX
XMany CISC microprocessors use microcode interally so theX
Xdevelopment and the debugging of the CPU can be done quicklyX
Xand efficently.  X
XWith this in mind, this microprogramming system was developed X
Xto be used as a teaching aid and as a first phase developmentX
Xkit of microcode for a particular hardware.X
X.PPX
XThe argument toX
X.I yampcX
Xis the hardware description file to be compiled. X
XThe results of this program is to create a C source code fileX
Xwith the same file name plus a ".c" extention.X
X.SH EXAMPLEX
XTo compile the desired architecture into C.X
X.RS 4X
Xyampc hdfX
X.RE 1X
X.PPX
XTo create the executable to interpretX
Xthe microcode of the architecture.X
X.RS 4X
Xcc hdf.c -o hdf -lyampcX
X.RE 1X
X.SH SEE ALSOX
XTheX
X.I YAMPC Reference Manual,X
Xincluded as the fileX
X.B yampc.docX
Xin the X
X.I yampcX
Xsource distribution.X
X.SH DIAGNOSTICSX
XNested comments are not valid.X
X.SH BUGSX
XSome syntax errors cause a slew of more errors to appear X
Xeven though there isn't any others.X
XThis is due to the fact thatX
X.I yampcX
Xdoesn't try to analyze and fix the error.X
Zaphod for prez
cat << 'Zaphod for prez' | sed 's/X\(.*\)X/\1/' > yampc.doc
X.\"X
X.\" YAMPC Microcode Development Kit DocumentX
X.\" Patrick Palmer, January 31, 1992X
X.\"X
X.\" Read in the pre-defined macro packageX
X.so tmac.ine    \" read in -mine macro definitionX
X.\"X
X.\" DOCUMENTX
X.\"X
X.ds Y Y\s-2AMPC\s+2X
X.ta 3.5iX
X.PB "Draft A"X
X.PO "\*Y Microcode Development Kit"X
X.PE "\*Y version 1.2"X
X.sp 3iX
X.ps 24X
X.vs 28X
X.FPX
X.ce 2X
XYAMPCX
XMicrocode Development KitX
X.brX
X.psX
X.vsX
X.sp 1iX
X.ce 2X
XPatrick PalmerX
XFebruary 28, 1992X
X.PFX
X.bpX
X.SP "Table of Contents"X
X.TSX
Xl.X
X1. IntroductionX
X2. Microcode DevelopmentX
X3. Hardware Description LanguageX
X4. Trial by ExampleX
X5. Technical GuideX
XA. Reserved WordsX
XB. TutorialX
XC. Miscellaneous NotesX
X.TEX
X.PPX
X.PPX
X.PPX
X.SP "Acknowledgements"X
XI wish to thank the following people for their assistanceX
Xin the completion of this project.X
X.PPX
X.TSX
Xcenter;X
Xl.X
XRayno Neimi, \fIRochester Institute of Technology\fPX
XMargaret Reek, \fIRochester Institute of Technology\fPX
X.TEX
X.PPX
XA lot of \*Y was derived from the AMISS project written X
Xby Robert Pesar, ex graduate student of Rochester Institute ofX
XTechnology.X
XSome of this documentation was adapted from the AMISS thesis and by noX
Xway means to infinge on that.X
X.PPX
X.PPX
X.PPX
X.SP "Distribution"X
XThis program is free software; you can redistribute it and/or modifyX
Xit under the terms of the GNU General Public License (version 2)X
Xas published by the Free Software Foundation.X
X.PPX
XThis program is distributed in the hope that it will be useful,X
Xbut WITHOUT ANY WARRANTY; without even the implied warranty ofX
XMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theX
XGNU General Public License for more details.X
X.PPX
XYou should have received a copy of the GNU General Public LicenseX
Xalong with this program; if not, write to the Free SoftwareX
XFoundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.X
X.PPX
X\*Y Microcode Development KitX
X.brX
X\(co 1992 by Patrick PalmerX
X.PPX
X.PPX
X.PPX
X.SP "Source Availability"X
XThe current source for this project has been submitted to theX
X\fIalt.sources\fP usenet group and can be retrievedX
Xanonymous ftp from any of the known archive locations.X
X.PE "Introduction"X
X.bpX
X.ST "1. Introduction"X
XIn today's world, there is the need to develop microprocessorsX
Xquickly and easily with very little room for bugs.X
XA methodology that developed in microprocessor design was theX
Xincorporation of microcode.X
XMicrocode interprets the assembly language instruction set andX
Xmanipulate the hardware.X
XIn turn, this removes many of the hassles and low level hardwareX
Xneeded.X
X.PPX
XMicrocoding has been around for a while and has been addressedX
Xby many of the technical societies. X
XBoth the ACM and the IEEE has discussed and presented articlesX
Xabout microcode as a topic of study.X
XA microprogramming simulation system can be usefulX
Xaddition to the teachings of microprogramming principles.X
XSuch systems do exist and are available but many are limitedX
Xby their ability to represent only a single microarchitecture.X
XThe intent of this project is to overcome that barrier.X
X.PPX
X\*Y is inheritly adaptable for a variety of microcodingX
Xprojects.X
XThe system is quite flexiable because of it's ability to X
Xcompletely design the architecture and the instruction set.X
XThe interactive debugger helps in quickly  identifying X
Xbugs with the microcode without ever touching actualX
Xhardware.X
X.PPX
XA primary goal in developing \*Y was to identify those detailsX
Xcommon to the description of microarchitectures and toX
Xcombine those details into a Hardware Description Language (HDL).X
XRather than developing a new programming language, \*Y HDL is X
Xbased on the C programming language and an HDL program is X
Xtranslated into a C program.X
XA \*Y HDL program is divided into two parts.X
XIn the first part the specifications of the elements of theX
Xarchitecture and of the control memory format are identified.X
XIn the second part, the course of events within the processorX
Xgoverned by the contents of a control memory word areX
Xdescribed.X
X.PPX
XThis is not a complete system by any means.X
XThere doesn't exist the ability nor was its intention to beX
Xused in a production environment.X
XThe purpose of this project is solely educational for bothX
Xmyself and the people it will be used by.X
X.PPX
X.SP "Educational Purposes"X
XWith the above discussion in mind, \*Y was developed X
Xfor the purpose to teach students about microcode and X
Xthe underlying architecture of microprocessors.X
XMicrocode development and easily be integrated intoX
Xa Computer Architecture course so students can learnX
Xhands on.X
X.PPX
XThere are many texts available that discuss ComputerX
XArchitecture.X
XEach in their own way present a hypothetical X
Xmicroarchitecture and a microprogram written in a high X
Xlevel microprogramming language that is capable of implementingX
Xall or some part of an instruction set.X
XWith the flexability to design hardware, the professor now hasX
Xthe ability to create a project for the students that isX
Xmodeled after a course text book.X
X.PPX
X.SP "Example"X
XI am convinced that the best way to explain the use of this systemX
Xis by example.X
XChapter 4 is by far the largest chapter and it shows a completeX
XHDL and microcode.X
XThe example is simple by nature but it does implement most of theX
Xcapabilities of the system.X
XI figure that chapter will become the focal point for reference.X
X.PE "Microcode Development"X
X.bpX
X.ST "2. Microcode Development"X
XThe intention of this project is let the user beX
Xable to develop microcode for a designed microhardware set.X
XThe purpose of microcode is to be able to interpret theX
Xassembly language and manipulate the hardware.X
X.PPX
XFrom a hardware point, there are separate parts of theX
Xmicroarchitecture that the microcode will interact with.X
XThese may include registers, Arithmetic Logic Unit, or a shifterX
Xof some sort.X
XThe microcode control word has access to all of the individualX
Xunits and manipulates them based on possible instructions.X
X.PPX
XThe process just to read in the a single assembly languageX
Xinstruction and act on it can be a full process.X
XLets take a instruction from the example in chapter 4 and X
Xfollow it through.X
X.PPX
X.TSX
Xcenter;X
Xl.X
X1. Initialization of the processor.X
X2. Fetch an instruction from memory - CLRA.X
X3. Decode the instruction.X
X4. Set the flags register - Zero flag set.X
X5. Move zero into the accumulator.X
X6. Go back to the fetch cycle and fetch another ins.X
X.TEX
X.PPX
X.SP "File Format"X
XThe microcode file is a listing of all of the control words thatX
Xare used to manipulate the hardware.X
XThe entire control word needs to be on one contingious line.X
XEach of the elements of the control word need to be separated X
Xwith a white space.X
X.PPX
XThe fetch cycle default start at microcode address 8.X
XThis in most cases will be satisfactory but there is the abilityX
Xto change it.X
XThe '.fetch [#]' command can appear at the beginning of the fileX
Xbut to note, the number specifying the new fetch cycle must beX
Xin decimal.X
X.PPX
XThe default is all values in the microcode file is hexidecimal.X
XThis can be changed by using a '.decimal' for decimal notationX
Xand '.octal' for octal notation.X
XThe '.decimal' or '.octal' should appear at the top of the file.X
X.PPX
XIn chapter 4, there is a complete microcode file and it isX
Xvery useful in helping the beginner understand the file format.X
X.PPX
X.SP "Assembly Programs"X
XOnce the microcode has be created, it needs to be tested againstX
Xsome actual data.X
XSince the purpose of microcode is to interpret assembly instructions,X
Xan assembly language file is used.X
XThis assembly language file contains the values of the instructions.X
XFor example, using the chapter 4 example, the instruction CLRA isX
Xactually 0x90.X
XEach of the instructions should be placed into the 'memory' fileX
Xand can be included into the interpreter at the command line.X
XThe can be one or more instructions on a line but there is noX
Xneed for the '0x' infront of every value.X
X.PPX
XComments can appear anywhere in the file and are delimited byX
Xa ';' and a newline.X
XThere doesn't need to be an assembly instruction on every line in theX
Xfile.X
XAlso, the '.decimal' and '.octal' commands that are available in theX
Xmicrocode file are also available here.X
X.PPX
X.SP "Using the Interpreter"X
XUsing the processor interpreter is pretty simple to use.X
XThe processor needs to be created from the HDL file and thenX
Xcompiled.X
XFor the sake of example, lets say it was compiled into theX
Xname 'CPU'.X
XTo start executing the microcode, the 'CPU' command can be used alone.X
XThis assumes though that the microcode is containedX
Xin a file called 'cmemory' and the assemblyX
Xlanguage code is in a file 'memory'.X
XIf this isn't true, then the file names need to be specified on theX
Xcommand line.X
X.PPX
XOnce the 'CPU' program is executing, a version banner is displayed andX
Xexecution begins.X
XThe program will end when the assembly language program finishes.X
XWhen it does, a message will appear displaying the number of cyclesX
Xto took to complete.X
X.PPX
X.SP "Correction File"X
XOne of the most powerful features of \*Y is the ability to create X
Xa correction file.X
XThis correction file can be used by students to determine which X
Xinstructions are working properly or by a professor grading X
Xthe submitted student code.X
X.PPX
XTo build a correction file, there is the '-c' option at the commandX
Xlevel that is used to build the correction file.X
XSince there is the need to know the correction file name (it doesn'tX
Xdefault), all of the memory file name must be listed in the commandX
Xline.X
XHere is an example:X
X.PPX
X.ps 9X
X.in +1iX
X.YSX
X% cpu -cpc,sp,flags,ac cmemory memory correctX
X.YEX
X.inX
X.psX
X.PPX
XThe above command will create a correction file asssuming thatX
Xthe 'cmemory' and 'memory' files are correct and that the registersX
Xthat are listed are actually defined.X
XThis file is only a correction file for that one assembly languageX
Xprogram found in the 'memory' file.X
XGiven the example in Chapter 4, listed below is an outcome with theX
Xdistributed 'memory' file.X
X.PPX
X.in +1iX
X.YSX
X1 sp=ffX
X2 pc=2 ac=44X
X3 pc=4 ac=65X
X4 pc=5 ac=66X
X5 pc=7 ac=51X
X6 pc=9X
X7 pc=a flags=4 ac=0X
X8 pc=b flags=0 ac=1X
X9 pc=c flags=4 ac=0X
Xa pc=d flags=8 ac=ffX
Xb pc=fX
Xc pc=10X
Xd pc=11X
Xe pc=12X
Xf pc=13X
X10 pc=15X
X.YEX
X.inX
X.PPX
XThe first number represents the count of the fetch cycle.X
XEach time that the fetch cycle is reached, each of the registersX
Xis compared and the ones that are changed from the previousX
Xfetch cycle is written out.X
X.PPX
XWhen using the correction file to test out the microcode, the '-c'X
Xoption is not used.X
XThe correction file is just added to the end of the command line.X
XIn the process of executing the microcode, the correction fileX
Xis checked against the current value of the registers.X
XIf the two compared values differ, the message is printed to X
Xstandard output and the register is updated.X
XThe register is updated so the program can continue on its properX
Xdirection.X
X.PPX
X.SP "Debugging"X
XThe interactive debugger allows the user to manipulate the microcodeX
Xand memory at run time.X
XThis is very useful in tracking down bugs that may exist in theX
Xmicrocode.X
X.PPX
XTo enter the debugger, the '-d' option is used in the command line.X
XThe system will then initialize itself and prompt the user forX
Xcommands.X
XCommand reference for the interactive debugger is availableX
Xin Appendix B.X
X.PE "Hardware Description Language"X
X.bpX
X.ST "3. Hardware Description Language"X
XThe Hardware Desciption Language (HDL) is the low levelX
Xprocessor code.X
XThis gives the ability to design the microarchitectureX
Xand customize it to personal taste.X
XThis is really the heart and advantage of the system.X
XThis is part that separates this project from the others.X
X.PPX
X.SP "Language Structure"X
XThe HDL language is a comparable to a sectionalized C.X
XMeaning that the actual code is similar to C but thereX
Xare sections for each part of the language.X
XListed below is each section (in proper order) and theirX
Xmeaning.X
X.PPX
X.TSX
Xcenter box tab(/);X
Xcw(1i) c, l | l.X
XSection/MeaningX
X=X
XFORMAT/This is the area that defines theX
X/actual control word.  Each part ofX
X/the control word is defined withX
X/the appropriate number of bits wide.X
X_X
XPARTS/This is where all of the registersX
X/and internal variables that can beX
X/accesses by the microcode. EachX
X/register is defined with the numberX
X/of desired bits.X
X_X
XVARS/Local variables that are definedX
X/are placed into this section.  Again,X
X/the desired number of bits is used.X
X_X
XMEMORY/This is where the control wordX
X/and main memory is defined.  TheX
X/size of each plus the actual mainX
X/memory word size is also defined.X
X_X
XSUBCYCLE/This section is used toX
X/define the number of subcycles inX
X/a particular cycle.X
X_X
XINTERRUPT/This section contains allX
X/of the defined interrupts uponX
X/boot of the processor.X
X_X
XINIT/This section contains all of theX
X/code that is needed for theX
X/initialization of the processor.X
X/Usually this would be setting theX
X/registers to a known state.X
X_X
XMICROENGINE/This is all of the code X
X/that is executed each cycle of theX
X/processor.  It does all of theX
X/actual manipulating of the micro-X
X/hardware.X
X.TEX
X.PPX
XThe entire program must be enclosed in the keywords 'BEGIN'X
Xand 'END'.X
X.PPX
XComments can appear anywhere in the codeX
Xand use standard C language style.X
XAll comments are delimited as the following.X
X.PPX
X.in +1iX
X.YSX
X/* ... Comment ... */X
X.YEX
X.inX
X.PPX
X.SP "Variable Definitions"X
XVariables are being defined in the FORMAT, PARTS and VARSX
Xsection of the language.X
XEach variable is listed with a brackets and numbers appearingX
Xright afters for bit definitions.X
XBelow is a listing of some variables defined in a FORMATX
Xsection.X
X.PPX
X.in +1iX
X.YSX
XFORMATX
X    write[1],X
X    read[1],X
X    asource[4],X
X    cccntrl[2],X
X    shftcntrl[2],X
X    alufunc[4],X
X    zdest[4],X
X    ldflags[1],X
X    ldhold[1],X
X    test[2],X
X    cond[3],X
X    addrf[9];X
X.YEX
X.inX
X.PPX
XThere is one difference though in the PARTS section.X
XA '*' is placed before the variable that will be theX
XMicro Program Counter (MPC).X
XThis must be defined or the program will not be able toX
Xwork properly.X
XThe MPC is the only way to move around in the microcode.X
X.PPX
X.SP "Memory Definitions"X
XDefining memory is set in that there is only one methodologyX
Xto do it.X
XThe best way is by example and then explain.X
X.PPX
X.in +1iX
X.YSX
XMEMORYX
X     cpu[512], mem[256][8];X
X.YEX
X.inX
X.PPX
XFirst the cpu control words are defined as being up to 512 of them.X
XThe size of the control word is determined from the FORMAT section.X
XThe actual main memory is defined as 256 bytes, 8 bits each byte.X
X.PPX
X.SP "Constructs"X
XThe Hardware Description language supports a subset commandsX
Xavailable from the C language.X
XThe ones supports should be enough for anything theX
Xprogrammer needs to accomplish.X
X.PPX
XWherever numerical input is expected, you can type an X
Xarithmetic expression.X
XAn expression involves parenthese and arithmetic operatorsX
Xand logical operators shown the table below:X
X.PPX
X.TSX
Xcenter box tab(#);X
Xc c, c l.X
X\fIArithmetic Operator#Meaning\fPX
X_X
X+#AdditionX
X-#SubtractionX
X/#DivisionX
X*#MultiplicationX
X%#ModuloX
X<<#Shift leftX
X>>#Shift rightX
X&#Bitwise andX
X|#Bitwise orX
X^#Exclusive orX
X~#Binary NotX
X_X
X.T&X
Xc c, c l.X
X\fILogical Operator#Meaning\fPX
X_X
X<#Less thanX
X>#Greater thanX
X<\&=#Less than or equal toX
X>\&=#Greater than or equal toX
X\&= or \&=\&=#Equal toX
X&&#andX
X||#orX
X.TEX
X.PPX
XListed below is a syntax summary of the availableX
Xlanguage constructs.X
X.PPX
X.in +1iX
X\fIcompound-statement:X
X.brX
X        declaration-list statement-listX
X.PPX
Xdeclaration-list:X
X.brX
X        declarationX
X.brX
X        declaration declaration-listX
X.PPX
Xstatement-list:X
X.brX
X        statementX
X.brX
X        statement statement-listX
X.PPX
Xstatement:X
X.brX
X        compound-statementX
X.brX
X        expression ;X
X.brX
X        \fPif (\fI expression \fP)\fI statementX
X.brX
X        \fPif (\fI expression \fP)\fI statement \fPelse\fI statementX
X.brX
X        \fPswitch (\fI expression \fP)\fI statementX
X.brX
X        \fPcase\fI constant-expression\fP:\fI statementX
X.brX
X        \fPdefault:\fI statementX
X.brX
X        \fPbreak;X
X.brX
X        Ireturn;X
X.brX
X        ;X
X.inX
X.PPX
X.SP "Initialization"X
XInitialization of the processor is only done at X
Xprocessor bootup and if the system is reset inX
Xthe interactive debugger.X
XThis section can contain any of the language X
Xconstructs but it is usually left for setting ofX
Xregisters.X
X.PPX
X.SP "Microcode Engine"X
XThe microcode engine is executed every subcycleX
Xor every cycle.X
XThe actual code inside the engine can use any ofX
Xthe language constructs available.X
XThe programmer will find that a lot of this section becomesX
Xbig switch statements for moving a value from/to a register.X
X.PPX
XExamine the HDL file found in chapter 4 for a complete example.X
XThat program uses all of the available constructs toX
Xbuild the microengine.X
X.PPX
X.SP "Pre-defined Variables"X
XCurrently there is only one predefined variable.X
XThe keyword 'subcycle' is used so at differentX
Xsubcycles different operations can occur.X
XAt this time, there is no support for debuggingX
Xon the subcycle level but it is on the FutureX
XEnhansement list in Appendix C.X
XThere is entire support within the system forX
Xsubcycles.X
X.PPX
X.SP "Compiling"X
XOnce the HDL language has been written, it needs to be submitted X
Xto the \*Y compiler.X
XThe compiler compiles the HDL source code into C source code.X
XThe C source output is then compiled and linked with theX
Xaccompanied library.X
XAfter these steps have been completed, the microcode interpreterX
Xfor the specified hardware will now be available to usage.X
XListed below is the explict steps needed to create thisX
Xinterpreter.X
X.PPX
X.in +1iX
X.YSX
X% yampc HardwareFileX
X% cc HardwareFile.c -o cpu libyampc.aX
X.YEX
X.inX
X.PPX
XAny errors returned from the compiler are quite self-explanatoryX
Xand useful.X
XThe system has a tendency though to display many more errorsX
Xthan necessary once it has come across one.X
XI suggest to fix the first one and try once again toX
Xrecompile.X
X.PE "Trial by Example"X
X.bpX
X.ST "4. Trial by Example"X
XThe best way to understand the usage of this project is byX
Xexample.X
XIn the section, a Hardware Description Language and associatedX
Xmicrocode will be demonstrated.X
XThe HDL has actually be used in a class at Rochester Institute ofX
XTechnology.X
XFor a first step, there needs to be an explanation of the X
Xdesired hardware.X
X.PPX
X.SP "Machine Description"X
XThe target machine is very simple.X
XThe following user-visible registers are 8-bits wide:X
X.PPX
X.TSX
Xcenter tab (/);X
Xc c, l l.X
XRegister/PurposeX
X_X
XPC/program counterX
XSP/stack pointerX
XX/index registerX
XFlags/flags registerX
XACC/arithmetic accumulatorX
X.TEX
X.PPX
XThis the entire "reach" of this target von Veuman machine is only 256X
Xlocations of one byte (8-bits per byte) each.X
XThe data path is eight bits.X
X.PPX
XThe bits in a byte are numbered from 7 for high-order bit to 0 for X
Xlow-order bit.X
XThe bits in the flags register have the following interpretation:X
X.PPX
X.TSX
Xcenter tab (/);X
Xc c, c l.X
XBit Position/DescriptionX
X_X
X7/Not UsedX
X6/Not UsedX
X5/Not UsedX
X4/Not UsedX
X3/"N" for negative resultX
X2/"Z" for zero resultX
X1/"V" for overflow resultX
X0/"C" for carry outX
X.TEX
X.PPX
XThe values of N, Z, V, and C are determined by the current inputs toX
Xthe ALU.X
XTo save these status bits for later operations, they need to be storedX
Xin the flags register.X
X.PPX
X.SP "Machine Instruction Set"X
XThe machine has short and long instructions.X
XShort instructions are one byte long while long instructions are twoX
Xbytes long.X
XThe first bit is always 1 for short instructions and 0 for long X
Xinstructions.X
XThe short instructions are zero operand instructions.X
XThe long instructions are one operand instructions with an implied X
Xregister, the accumulator.X
XThe machine follows the accumulator register model.X
X.bpX
XThe condition code setting for each instruction are the following:X
X"0" indicates bit cleared, "1" indicates bit set, "x" indicatesX
Xbit may chage, and "-" indicates no change.X
X.PPX
X.ne 3iX
X.ps 7X
X.vs 9X
X.TSX
Xcenter tab (/);X
Xc s s s, c c c c, l l l l.X
X\fBShort Instructions\fPX
XOp Code/Mnemonic/Description/NZVCX
X_X
X1000 0000/INCA/increment accumulator/xxxxX
X1000 0001/INCX/increment index register/----X
X1000 0010/DECA/decrement accumulator/xxxxX
X1000 0011/DECX/decrement index register/----X
X///X
X1001 0000/CLRA/clear accumulator/0100X
X1001 0001/CLRX/clear index register/----X
X///X
X1010 0000/NOT/bitwise complement of accumulator/xx00X
X1010 0001/NEG/2's complement negation of accumulator/xxx0X
X///X
X1011 0000/SLL/shift left logical/xx0xX
X1011 0001/SLC/shift left circular/xx0xX
X///X
X1011 0010/SRL/shift right logical/xx0xX
X1011 0011/SRC/shift right circular/xx0xX
X1011 0100/SRA/shift right arithmetic/xx0xX
X///X
X1100 0000/POP ACC/pop accumulator off top of stack/xx00X
X1100 0001/POP X/pop index register off top of stack/----X
X1100 0010/POP FLAGS/pop flags off top of stack/----X
X///X
X1101 0000/PUSH ACC/push accumulator on stack/----X
X1101 0001/PUSH X/push index register on stack/----X
X1101 0010/PUSH FLAGS/push flags on stack/----X
X///X
X1110 0000/RETN/return from subroutine/----X
X///X
X1111 0000/HALT/halt execution/----X
X.TEX
X.ps 11X
X.vs 13X
X.PPX
XThe two low-order bits (indicated by "aa") for a long instructionX
Xindicate the addressing mode.X
X.PPX
X.ne 2iX
X.ps 7X
X.vs 9X
X.TSX
Xcenter tab (/);X
Xc s s s, c c c c, l l l l.X
X\fBLong Instructions\fPX
XOp Code/Mnemonic/Description/NZVCX
X_X
X0000 00aa/ADD/add to accumulator/xxxxX
X0000 01aa/SUB/suctract from accumulator/xxxxX
X///X
X0001 00aa/OR/logical OR to accumulator/xx00X
X0001 01aa/XOR/logical XOR to accumulator/xx00X
X0001 10aa/AND/logical AND to accumulator/xx00X
X///X
X0010 00aa/LDA/load accumulator/xx00X
X0010 01aa/LDX/load index register/----X
X0010 10aa/LDS/load stack register/----X
X///X
X0011 00aa/STA/store accumulator/----X
X0011 01aa/STX/store index register/----X
X///X
X0101 00aa/CALL/jump to subroutine/----X
X///X
X0111 00aa/BR/branch always/----X
X0111 01aa/BEQ/branch if zero (Z bit = 1)/----X
X0111 10aa/BLSS/branch if negative (N bit = 1)/----X
X0111 11aa/BNEQ/branch if not zero (Z bit = 0)/----X
X.TEX
X.ps 11X
X.vs 13X
X.bpX
XThe machine has four address mode for long instructions.X
XThe second instruction holds an 8-bit operand.X
XThe addressing mode combines with the operand to yield a memoryX
Xaddress \fBaddr\fP as described below:X
X.PPX
X.TSX
Xcenter tab(/);X
Xc c c, c l l.X
XMode Bits/Mode/DescriptionX
X_X
X00/Direct/addr\(<-operandX
X01/Indirect/addr\(<-Memory[operand]X
X10/Indexed/addr\(<-(X) + operandX
X11/Stack/addr\(<-(SP) + operandX
X.T&X
Xc.X
Xwhere operand is stored in next byteX
X.TEX
X.PPX
X.SP "MicroInstruction Format"X
XThe following table describes the format of the control word X
Xfor the microcode.X
X.PPX
X.TSX
Xcenter expand tab (/);X
Xc c c c, c c l l l.X
XBit/Field/Name/OperationX
X=X
X0/A/WRITE/0 - no operationX
X///1 - WriteX
X_X
X1/B/READ/0 - no operationX
X///1 - ReadX
X_X
X2/C/ASOURCE/0000 - noneX
X3///0001 - ACCX
X4///0010 - PCX
X5///0011 - PCX
X///0100 - IRX
X///0101 - FLAGSX
X///0110 - XX
X///0111 - BX
X///1000 - CX
X///1001 - MBRX
X///1010 - low-order 8-bits from/Address FieldX
X///1011 - 1111 - unusedX
X_X
X6/D/CCCTRL/00 - Leave CC aloneX
X7///01 - Set CCX
X///10 - Clear CCX
X///11 - CC := carry out of ALUX
X_X
X8/E/SHFTCTRL/00 - No shiftX
X9///01 - Shift leftX
X///10 - Shift rightX
X///11 - unusedX
X_X
X10/F/ALUCTRL/0000 - X/1000 - X + 1X
X11///0001 - Y/1001 - Y + 1X
X12///0010 - ~ Y/1010 - ~ XX
X13///0011 - X + Y + 1/1011 - Y & 1X
X///0100 - X & Y/1100 - Y + ~ X + 1X
X///0101 - X | Y/1101 - X & 1X
X///0110 - X ^ Y/1110 - -1 (all 1s)X
X///0111 - X + Y/1111 - 0 (all 0s)X
X_X
X.TEX
X.bpX
X.TSX
Xcenter expand tab (/);X
Xc c c c, c c l l.X
XBit/Field/Name/OperationX
X=X
X14/G/ZDEST/0000 - noneX
X15///0001 - ACCX
X16///0010 - PCX
X17///0011 - SPX
X///0100 - IRX
X///0101 - FLAGSX
X///0110 - XX
X///0111 - BX
X///1000 - CX
X///1001 - MBRX
X///1010 - MARX
X///1011 - 1111 - unusedX
X_X
X18/H/LOADFLGS/0 - do not change FLAGS registerX
X///1 - load FLAGS register from N,Z,V,C-BITX
X_X
X19/I/LOADHOLD/0 - do not change HOLD registerX
X///1 - Load HOLD register from ABUSX
X_X
X20/J/TEST/00 - Select C-BIT from ALUX
X21///01 - Select V-BIT from ALUX
X///10 - Select Z-BIT from ALUX
X///11 - Select N-BIT from ALUX
X_X
X22/K/COND/Determines type of next addressX
X23///(see next section)X
X24///X
X_X
X25/L/ADDRF/Next microinstruction address fieldX
X26///(see next section)X
X27///X
X28///X
X29///X
X30///X
X31///X
X32///X
X33///X
X_X
X.TEX
X.PPX
X.SP "Microcode Program Counter"X
XThe control store is 512 x 34 bits.X
XThe MPC is 9 bits wide and the MIR is 36 bits wide.X
XThe next value of the MicroProgram Counter (MPC) is determined by theX
Xvalue of the ADDRF, COND, and TEST fields in the following manner.X
X.PPX
X.TSX
Xcenter box tab (/);X
Xc | c, c | l.X
XCOND/MPCX
X=X
X000/MPC + 1X
X_X
X001/ADDRFX
X_X
X010/25 26 27 28 29 30 31 32 TEST-BIT (2-way branch)X
X_X
X011/25 26 27 28 29 30 31 IR1 IR0 (4-way branch)X
X_X
X100/25 26 27 28 29 30 31 IR3 IR2 (4-way branch)X
X_X
X101/25 26 27 28 29 30 31 IR5 IR4 (4-way branch)X
X_X
X110/25 26 27 28 29 30 31 IR7 IR6 (4-way branch)X
X_X
X111/not usedX
X.TEX
X.PPX
X.SP "Memory Timing"X
XAll memory accesses take at least 2 machine cycles.X
XTo write to memory, the WRITE fields must be 1 in the microinstructionX
Xwhich completes the loading of the MAR and the MBR registers.X
XThe next microinstruction must also have the WRITE field set to 1.X
XThe READ fields must be 0.X
X.PPX
XTo read from memory, the data is not available for one completeX
Xmachine cycle after the MAR register hsa been loaded with the address.X
XThe READ field must be 1 in both microinstructions and the WRITEX
Xfields set to 0.X
X.PPX
X.SP "Hardware Description Language"X
XListed below is the source for the Hardware Description Language for theX
Xabove described machine.X
X.PPX
X.FPX
X.in +1iX
X.ps 9X
X.vs 11X
X.YSX
XX
XBEGINX
XFORMATX
X    write[1],X
X    read[1],X
X    asource[4],X
X    cccntrl[2],X
X    shftcntrl[2],X
X    alufunc[4],X
X    zdest[4],X
X    ldflags[1],X
X    ldhold[1],X
X    test[2],X
X    cond[3],X
X    addrf[9];X
XX
XPARTSX
X    pc[8], ac[8], sp[8], ir[8], flags[8],X
X    rx[8], rb[8], rc[8], alu[8], mbr[8], mar[8], hold[8],X
X    shifter[8], abus[8], zbus[8], *mpc[10], cc[1],X
X    nbit[1], zbit[1], vbit[1], cbit[1];X
XX
XVARSX
X    garbage[8], temp[8], temp2[8], temp3[8];X
XX
XMEMORYX
X    cpu[512], mem[256][8];X
XX
XSUBCYCLEX
X    subcycle = 2;X
XX
XINITX
X    sp = 0xaa;X
X    pc = 0xaa;X
X    mpc = 0; X
X    garbage = 0xaa;X
X    hold = 0xaa;X
XX
XMICROENGINEX
Xif ( subcycle == 1 ) {X
XX
X    /* Set value on ABUS */X
XX
X    abus = garbage;X
XX
X    temp3 = ( addrf & 0x0ff );X
XX
X    switch ( asource ) {X
X        case 0:  abus = garbage;  break;X
X        case 1:  abus = ac;       break;X
X        case 2:  abus = pc;       break;X
X        case 3:  abus = sp;       break;X
X        case 4:  abus = ir;       break;X
X        case 5:  abus = flags;    break;X
X        case 6:  abus = rx;       break;X
X        case 7:  abus = rb;       break;X
X        case 8:  abus = rc;       break;X
X        case 9:  abus = mbr;      break;X
X        case 10: abus = temp3;    break;X
X    }X
XX
X    /* Set value in HOLD register */X
XX
X    if ( ldhold ) {X
X        hold = abus;X
X    }X
XX
X    /* Set ALU function */X
X    X
X    switch ( alufunc ) {X
X        case 0:    alu = hold;              break;X
X        case 1:    alu = abus;              break;X
X        case 2:    alu = ( ~ abus ) - 1;    break;X
X        case 3:    alu = hold + abus + 1;   break;X
X        case 4:    alu = hold & abus;       break;X
X        case 5:    alu = hold | abus;       break;X
X        case 6:    alu = hold ^ abus;       break;X
X        case 7:    alu = hold + abus;       break;X
X        case 8:    alu = hold + 1;          break;X
X        case 9:    alu = abus + 1;          break;X
X        case 10:   alu = ( ~ hold ) - 1;    break;X
X        case 11:   alu = abus & 1;          break;X
X        case 12:   alu = abus - hold;       break;X
X        case 13:   alu = hold & 1;          break;X
X        case 14:   alu = -1;                break;X
X        case 15:   alu = 0;                 break;X
X    }X
X}X
XX
Xif ( subcycle == 2 ) {X
XX
X    /* Set Condition Codes */X
X    nbit = 0; zbit = 0; vbit = 0; cbit = 0;X
X    temp = alu;X
XX
X    temp2 = temp & 0x80;X
X    if ( temp2 != 0) nbit = 1;X
XX
X    temp2 = temp & 0xff;X
X    if ( temp2 == 0 ) zbit = 1;X
XX
X    temp2 = temp & 0x1ff00;X
X    if ( temp2 != 0 ) cbit = 1;X
XX
X    switch ( alufunc ) {X
X        case 0:X
X        case 1:X
X        case 2: break;X
X        case 3: alu = hold + abus + 1; break;X
X        case 4:X
X        case 5:X
X        case 6: break;X
X        case 7: if (((hold & 0x80) == 0) && ((abus & 0x80) == 0))X
X                if (nbit != 0 ) vbit = 1;X
X            if (((hold & 0x80) != 0) && ((abus & 0x80) != 0))X
X                if (nbit != 1 ) vbit = 1;X
X            break;X
X        case 8:    if ((hold & 0x80 ) == 0 )X
X                if ( nbit != 0 ) vbit = 1;X
X            break;X
X        case 9: if ((abus & 0x80 ) == 0)X
X                if ( nbit != 0 ) vbit = 1;X
X            break;X
X        case 10:X
X        case 11: break;X
X        case 12: if (((hold & 0x80 ) != 0) && ((abus & 0x80) == 0))X
X                if ( nbit != 0 ) vbit = 1;X
X             if (((hold & 0x80 ) == 0) && ((abus & 0x80) != 0))X
X                if ( nbit != 1 ) vbit = 1;X
X             break;X
X        case 13:X
X        case 14:X
X        case 15: break;X
X    }X
XX
X    /* set CC bit for the shifter */X
XX
X    switch ( cccntrl ) {X
X        case 0:            break;X
X        case 1: cc = 1;    break;X
X        case 2: cc = 0;    break;X
X        case 3: cc = cbit; break;X
X    }X
XX
X    /* Load FLAGS from status of ALU */X
XX
X    if ( ldflags ) {X
X        flags = cbit + ( 2 * vbit ) + ( 4 * zbit ) + ( 8 * nbit );X
X    }X
XX
X    /* set output of shifter to zbus */X
XX
X    shifter = alu;X
XX
X    temp = cc;X
XX
X    switch ( shftcntrl ) {X
X        case 1:X
X            if ( shifter & 0x80 ) cc = 1;X
X            else cc = 0;X
X            shifter = shifter << 1;X
X            shifter = shifter + temp;X
X            break;X
XX
X        case 2: X
X            cc = shifter & 1;X
X            shifter = shifter >> 1;X
X            if ( temp ) shifter = shifter | 0x80;X
X            break;X
XX
X        default:X
X            break;X
X    }X
XX
X    zbus = shifter;X
XX
X    /* store zbus into any specified register */X
XX
X    if ( zdest != 0 ) X
X        switch ( zdest ) {X
X            case 0:  garbage = zbus;  break;X
X            case 1:  ac = zbus;       break;X
X            case 2:  pc = zbus;       break;X
X            case 3:  sp = zbus;       break;X
X            case 4:  ir = zbus;       break;X
X            case 5:  flags = zbus;    break;X
X            case 6:  rx = zbus;       break;X
X            case 7:  rb = zbus;       break;X
X            case 8:  rc = zbus;       break;X
X            case 9:  mbr = zbus;      break;X
X            case 10: mar = zbus;      break;X
X        }X
XX
X    /* Set MBR for reads */X
XX
X    if ( write ) {X
X        if ( zdest <= 9 ) mem[mar] = mbr;X
X        else mem[mar] = garbage;X
X    }X
X    if ( read ) {X
X        if ( zdest <= 9 ) mbr = mem[mar];X
X        else mbr = garbage;X
X    }X
XX
X    /* determine select bit from the current ALU flag settings */X
XX
X    switch ( test ) {X
X        case 0:    temp = cbit; break;X
X        case 1:    temp = vbit; break;X
X        case 2:    temp = zbit; break;X
X        case 3:    temp = nbit; break;X
X    }X
XX
X    /* Determine next value of MPC */X
XX
X    switch ( cond ) {X
X        case 0: mpc = mpc + 1; break;X
X        case 1: mpc = addrf; break;X
X        case 2: mpc = ( addrf & 0x3fe ) + temp; break;X
X        case 3: temp3 = ( ir & 0x03 );X
X            mpc = (addrf & 0x1fc ) + temp3; break;X
X        case 4: temp3 = ( ir & 0x0c ) >> 2;X
X            mpc = ( addrf & 0x1fc ) + temp3; break;X
X        case 5: temp3 = ( ir & 0x30 ) >> 4;X
X            mpc = ( addrf & 0x1fc ) + temp3; break;X
X        case 6: temp3 = ( ir & 0xc0 ) >> 6;X
X            mpc = ( addrf & 0x1fc ) + temp3; break;X
X        default: mpc = 9999; break;X
X    }X
X}X
XX
XENDX
X.YEX
X.vsX
X.psX
X.inX
X.PFX
X.PPX
X.SP "Microcode"X
XListed below is an example of microcode that implements the designedX
Xhardware.X
XThe actual microcode is not necessarily the fastest possible implementationX
Xbut it is straight forward and easy to understand.X
X.PPX
X.FPX
X.in +1iX
X.ps 8X
X.vs 10X
X.YSX
X; Data contained is in decimalX
X .decimalX
XX
X;X
X;WRITE -  Write MAR into memoryX
X;|  READ - Read MAR address into MBRX
X;|  |  ASOURCE - Source for ABUSX
X;|  |  |  CCCNTRL - CC controlX
X;|  |  |  |  SHFTCTRL - shift controlX
X;|  |  |  |  |   ALUCTRL - Function from ALUX
X;|  |  |  |  |   |  ZDEST - Destination on ZBUSX
X;|  |  |  |  |   |  |  LOADFLAGS - Load FLAGS from ALUX
X;|  |  |  |  |   |  |  |  LOADHOLD - Load HOLD from ABUSX
X;|  |  |  |  |   |  |  |  |  TEST - Select bit from ALU status bitsX
X;|  |  |  |  |   |  |  |  |  |  COND - Type of next addressX
X;|  |  |  |  |   |  |  |  |  |  |    ADDRF - Address for micro jumpX
X;|  |  |  |  |   |  |  |  |  |  |    |    Decimal AddressX
X;|  |  |  |  |   |  |  |  |  |  |    |    |   Hex AddressX
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    CommentX
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    | X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;|  |  |  |  |   |  |  |  |  |  |    |    |   |    |X
X;A  B  C  D  E   F  G  H  I  J  K    L    Dec Hex  RemX
X;******** Initialize PC to 0 ****************************************X
X 0  0  0  0  0  15  2  0  0  0  0    0  ; 0   00 ; PC    <- 0X
X 0  0  0  0  0  15  5  0  0  0  0    0  ; 1   01 ; FLAGS <- 0X
X 0  0  0  0  0  15  1  0  0  0  0    0  ; 2   02 ; AC    <- 0X
X 0  0  0  0  0  14  3  0  0  0  0    0  ; 3   03 ; SP    <- 0xFFX
X 0  0  0  0  0  15  6  0  0  0  0    0  ; 4   04 ; X     <- 0X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 5   05 ; goto fetchX
XX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 6   06 ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 7   07 ; nopX
XX
X;******** Fetch Next Instruction ***********************************X
X 0  1  2  0  0   1 10  0  0  0  0    0  ; 8   08 ; MAR <- PC; READX
X 0  1  2  0  0   9  2  0  0  0  0    0  ; 9   09 ; PC <- PC + 1; READX
X 0  0  9  0  0   1  4  0  0  0  6   12  ; 10  0a ; IR <- MBR;X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 11  0b ; nopX
X;                                                ; start instruction decodeX
X;                                                ; goto 12 + IR7 * 2 + IR6X
X 0  0  0  0  0   0  0  0  0  0  1  115  ; 12  0c ; IR76 00; goto 115X
X 0  0  0  0  0   0  0  0  0  0  1  115  ; 13  0d ; IR76 01; goto 115X
X 0  0  0  0  0   0  0  0  0  0  1   50  ; 14  0e ; IR76 10; goto 50X
X;X
X; OpCodes that have IR7=1 and IR6=1X
X 0  0  0  0  0   0  0  0  0  0  5   16  ; 15  0f ; test IR5, IR4X
X 0  0  0  0  0   0  0  0  0  0  1   20  ; 16  10 ; IR54 00; goto 20 X
X 0  0  0  0  0   0  0  0  0  0  1   32  ; 17  11 ; IR54 01; goto 32X
X 0  0  0  0  0   0  0  0  0  0  1   46  ; 18  12 ; IR54 10; goto 46X
X;X
X; HALT (1111 0000) - halt executionX
X 999 999 999 999 999 999 999 999 999 999 999 999 ; 19  13 ; DIE!!X
X;X
X; pop instructions  X
X 0  1  3  0  0   1 10  0  0  0  0    0  ; 20  14 ; MAR <- SP; READX
X 0  1  3  0  0   9  3  0  0  0  0    0  ; 21  15 ; SP <- SP + 1; READX
X 0  0  0  0  0   0  0  0  0  0  3   24  ; 22  16 ; test IR1, IR0X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 23  17 ; nopX
X 0  0  0  0  0   0  0  0  0  0  1   28  ; 24  18 ; IR10 00; goto 28 X
X 0  0  0  0  0   0  0  0  0  0  1   29  ; 25  19 ; IR10 01; goto 29 X
X 0  0  0  0  0   0  0  0  0  0  1   30  ; 26  1a ; IR10 10; goto 30 X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 27  1b ; IR10 11; goto 8; neverX
X;X
X; POP ACC (1100 0000) - pop accumulator off top of stackX
X 0  0  9  0  0   1  1  1  0  0  1  211  ; 28  1c ; ACC <- MBR; goto 211 X
X;X
X; POP X (1100 0001) - pop index register off top of stackX
X 0  0  9  0  0   1  6  0  0  0  1    8  ; 29  1d ; X <- MBR; goto 8 X
X;X
X; POP FLAGS (1100 0010) - pop flags off top of stackX
X 0  0  9  0  0   1  5  0  0  0  1    8  ; 30  1e ; FLAGS <- MBR; goto 8 X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 31  1f ; nopX
X;X
X; push instructionsX
X 0  0  3  0  0   2  3  0  0  0  0    0  ; 32  20 ; not SP X
X 0  0  3  0  0   9  3  0  0  0  0    0  ; 33  21 ; SP <- SP + 1 X
X 0  0  3  0  0   2  3  0  0  0  0    0  ; 34  22 ; not SP X
X 0  0  3  0  0   1 10  0  0  0  3   36  ; 35  23 ; MAR <- SP; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1   40  ; 36  24 ; IR10 00; goto 40 X
X 0  0  0  0  0   0  0  0  0  0  1   42  ; 37  25 ; IR10 01; goto 42 X
X 0  0  0  0  0   0  0  0  0  0  1   44  ; 38  26 ; IR10 10; goto 44 X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 39  27 ; IR10 11; goto 8; neverX
X;X
X; PUSH ACC (1101 0000) - push accumulator on stackX
X 1  0  1  0  0   1  9  0  0  0  0    0  ; 40  28 ; MBR <- ACC; WRITEX
X 1  0  0  0  0   0  0  0  0  0  1    8  ; 41  29 ; WRITE; goto 8X
X;X
X; PUSH X (1101 0001) - push index register on stackX
X 1  0  6  0  0   1  9  0  0  0  0    0  ; 42  2a ; MBR <- X; WRITEX
X 1  0  0  0  0   0  0  0  0  0  1    8  ; 43  2b ; WRITE; goto 8X
X;X
X; PUSH FLAGS (1101 0010) - push flags on stackX
X 1  0  5  0  0   1  9  0  0  0  0    0  ; 44  2c ; MBR <- FLAGS; WRITEX
X 1  0  0  0  0   0  0  0  0  0  1    8  ; 45  2d ; WRITE; goto 8X
X;X
X; RETN (1110 0000) - return from subroutineX
X 0  1  3  0  0   1 10  0  0  0  0    0  ; 46  2e ; MAR <- SP; READX
X 0  1  3  0  0   9  3  0  0  0  0    0  ; 47  2f ; SP <- SP + 1; READX
X 0  0  9  0  0   1  2  0  0  0  1    8  ; 48  30 ; PC <- MBR; goto 8 X
XX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 49  31 ; nopX
X;X
X; OpCodes that have IR7=1 and IR6=0X
X 0  0  0  0  0   0  0  0  0  0  5   52  ; 50  32 ; test IR5, IR4X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 51  33 ; nopX
X 0  0  0  0  0   0  0  0  0  0  1   59  ; 52  34 ; IR54 00; goto 59 X
X 0  0  0  0  0   0  0  0  0  0  1   71  ; 53  35 ; IR54 01; goto 71X
X 0  0  0  0  0   0  0  0  0  0  1   79  ; 54  36 ; IR54 10; goto 79X
X 0  0  0  0  0   0  0  0  0  0  1   87  ; 55  37 ; IR54 11; goto 87X
XX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 56  38 ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 57  39 ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 58  3a ; nopX
X;X
X; increment/decrement registersX
X 0  0  0  0  0   0  0  0  0  0  3   60  ; 59  3b ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1   70  ; 60  3c ; IR10 00; goto 70 X
X 0  0  0  0  0   0  0  0  0  0  1   69  ; 61  3d ; IR10 01; goto 69 X
X 0  0  0  0  0   0  0  0  0  0  1   66  ; 62  3e ; IR10 10; goto 66 X
X;X
X; DECX (1000 0011) - decrement index registerX
X 0  0  6  0  0   2  6  0  0  0  0    0  ; 63  3f ; not X X
X 0  0  6  0  0   9  6  0  0  0  0    0  ; 64  40 ; X <- X + 1X
X 0  0  6  0  0   2  6  0  0  0  1    8  ; 65  41 ; not X ; goto 8X
X;X
X; DECA (1000 0010) - decrement accumulatorX
X 0  0  1  0  0   2  1  0  0  0  0    0  ; 66  42 ; not ACC X
X 0  0  1  0  0   9  1  0  0  0  0    0  ; 67  43 ; ACC <- ACC + 1 X
X 0  0  1  0  0   2  1  1  0  0  1    8  ; 68  44 ; not ACC; goto 8X
X;X
X; INCX (1000 0001) - increment index registerX
X 0  0  6  0  0   9  6  0  0  0  1    8  ; 69  45 ; X <- X + 1; goto 8X
X;X
X; INCA (1000 0000) - increment accumulatorX
X 0  0  1  0  0   9  1  1  0  0  1    8  ; 70  46 ; ACC <- ACC + 1; goto 8X
X;X
X; clearing registersX
X 0  0  0  0  0   0  0  0  0  0  3   72  ; 71  47 ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1   76  ; 72  48 ; IR10 00; goto 76X
X 0  0  0  0  0   0  0  0  0  0  1   78  ; 73  49 ; IR10 01; goto 78X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 74  4a ; IR10 10; goto 8; never X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 75  4b ; IR10 11; goto 8; never X
X;X
X; CLRA (1001 0000) - clear accumulatorX
X 0  0 10  0  0   1  5  0  0  0  0    4  ; 76  4c ; FLAGS <- 00000100X
X 0  0  1  0  0  15  1  0  0  0  1    8  ; 77  4d ; ACC <- 0; goto 8X
X;X
X; CLRX (1001 0000) - clear index registerX
X 0  0  6  0  0  15  6  0  0  0  1    8  ; 78  4e ; X <- 0; goto 8X
X;X
X; ones/twos complementX
X 0  0  0  0  0   0  0  0  0  0  3   80  ; 79  4f ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1   84  ; 80  50 ; IR10 00; goto 84X
X 0  0  0  0  0   0  0  0  0  0  1   85  ; 81  51 ; IR10 01; goto 85X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 82  52 ; IR10 10; goto 8; never X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 83  53 ; IR10 11; goto 8; never X
X;X
X; NOT (1010 0000) - bitwise complement of accumulatorX
X 0  0  1  0  0   2  1  1  0  0  1  211  ; 84  54 ; not ACC; goto 211X
X;X
X; NEG (1010 0001) - 2's complement negation of the accumulatorX
X 0  0  1  0  0   2  1  0  0  0  0    0  ; 85  55 ; not ACCX
X 0  0  1  0  0   9  1  1  0  0  1  218  ; 86  56 ; ACC <- ACC + 1; goto 218X
X;X
X; shiftingX
X 0  0  0  0  0   0  0  0  0  0  4   88  ; 87  57 ; test IR3,IR2 X
X 0  0  0  0  0   0  0  0  0  0  1   95  ; 88  58 ; IR32 00; goto 95X
X 0  0  0  0  0   0  0  0  0  0  1  104  ; 89  59 ; IR32 01; goto 104X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 90  5a ; IR32 10; goto 8; never X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 91  5b ; IR32 11; goto 8; never X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 92  5c ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 93  5d ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 94  5e ; nopX
X 0  0  0  0  0   0  0  0  0  0  3   96  ; 95  5f ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1  100  ; 96  60 ; IR10 00; goto 100X
X 0  0  0  0  0   0  0  0  0  0  1  108  ; 97  61 ; IR10 01; goto 108X
X 0  0  0  0  0   0  0  0  0  0  1  102  ; 98  62 ; IR10 10; goto 102 X
X 0  0  0  0  0   0  0  0  0  0  1  111  ; 99  63 ; IR10 11; goto 111 X
X;X
X; SLL (1011 0000) - shift logical leftX
X 0  0  0  2  0   0  0  0  0  0  0    0  ; 100 64 ; clear shifterX
X 0  0  1  0  1   1  1  0  0  0  1  114  ; 101 65 ; lshift ACC; goto 114X
X;X
X; SRL (1011 0010) - shift logical rightX
X 0  0  0  2  0   0  0  0  0  0  0    0  ; 102 66 ; clear shifterX
X 0  0  1  0  2   1  1  0  0  0  1  114  ; 103 67 ; rshift ACC; goto 114X
X;X
X; SRA (1011 0100) - shift arithmetically rightX
X 0  0 10  0  0   0  0  0  1  0  0  128  ; 104 68 ; hold <- mask(10000000)X
X 0  0  1  0  1   4  0  0  0  0  0    0  ; 105 69 ; CC <- lshift(0x80&ACC)X
X 0  0  1  0  2   1  1  0  0  0  1  114  ; 106 6a ; rshift ACC; goto 114X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 107 6b ; nopX
X;X
X; SLC (1011 0001) - shift circular leftX
X 0  0 10  0  0   0  0  0  1  0  0  128  ; 108 6c ; hold <- mask(10000000)X
X 0  0  1  0  1   4  0  0  0  0  0    0  ; 109 6d ; CC <- lshift(0x80&ACC)X
X 0  0  1  0  1   1  1  0  0  0  1  114  ; 110 6e ; lshift ACC; goto 114X
X;X
X; SRC (1011 0011) - shift circular rightX
X 0  0 10  0  0   0  0  0  1  0  0    1  ; 111 6f ; hold <- mask(00000001)X
X 0  0  1  0  2   4  0  0  0  0  0    0  ; 112 70 ; CC <- rshift(0x01&ACC)X
X 0  0  1  0  2   1  1  0  0  0  0    0  ; 113 71 ; rshift ACCX
X;X
X; send ACC thru ALU to get proper flags because shifter is after ALUX
X 0  0  1  0  0   1  0  1  0  0  1  213  ; 114 72 ; ACC ; goto 213 X
X;X
X; OpCodes that have IR7=0X
X 0  0  0  0  0   0  0  0  0  0  3  116  ; 115 73 ; test IR0,IR1 X
X 0  0  0  0  0   0  0  0  0  0  1  120  ; 116 74 ; IR10 00; goto 120X
X 0  0  0  0  0   0  0  0  0  0  1  126  ; 117 75 ; IR10 01; goto 126X
X 0  0  0  0  0   0  0  0  0  0  1  133  ; 118 76 ; IR10 10; goto 133 X
X;X
X; Mode is Stack (11) - addr <- (SP) + operandX
X 0  0  3  0  0   0  0  0  1  0  1  134  ; 119 77 ; hold <- SP; goto 134X
X;X
X; Mode is Direct (00) - addr <- operandX
X 0  1  2  0  0   1 10  0  0  0  0    0  ; 120 78 ; MAR <- PC; READX
X 0  1  2  0  0   9  2  0  0  0  0    0  ; 121 79 ; PC <- PC + 1; READX
X 0  0  9  0  0   1  7  0  0  0  0    0  ; 122 7a ; B <- MBRX
X 0  1  7  0  0   1 10  0  0  0  0    0  ; 123 7b ; MAR <- B; READX
X 0  1  0  0  0   0  0  0  0  0  0    0  ; 124 7c ; READX
X 0  0  0  0  0   0  0  0  0  0  1  139  ; 125 7d ; goto 139X
X;X
X; Mode is Indirect (01) - addr <- Memory[operand]X
X 0  1  2  0  0   1 10  0  0  0  0    0  ; 126 7e ; MAR <- PC; READX
X 0  1  2  0  0   9  2  0  0  0  0    0  ; 127 7f ; PC <- PC + 1; READX
X 0  1  9  0  0   1 10  0  0  0  0    0  ; 128 80 ; MAR <- MBR; READX
X 0  1  0  0  0   0  0  0  0  0  0    0  ; 129 81 ; READX
X 0  0  9  0  0   1  7  0  0  0  0    0  ; 130 82 ; B <- MBRX
X 0  1  7  0  0   1 10  0  0  0  0    0  ; 131 83 ; MAR <- B; READX
X 0  1  0  0  0   0  0  0  0  0  1  139  ; 132 84 ; READ; goto 139X
X;X
X; Mode is Indexed (10) - addr <- (X) + operandX
X 0  0  6  0  0   0  0  0  1  0  0    0  ; 133 85 ; hold <- XX
X 0  1  2  0  0   1 10  0  0  0  0    0  ; 134 86 ; MAR <- PC; READX
X 0  1  2  0  0   9  2  0  0  0  0    0  ; 135 87 ; PC <- PC + 1; READX
X 0  0  9  0  0   7  7  0  0  0  0    0  ; 136 88 ; B <- MBR + holdX
X 0  1  7  0  0   1 10  0  0  0  0    0  ; 137 89 ; MAR <- B; READX
X 0  1  0  0  0   0  0  0  0  0  0    0  ; 138 8a ; READX
X;X
X; Mode is loaded into register B, keep on decoding instructionX
X 0  0  0  0  0   0  0  0  0  0  6  140  ; 139 8b ; test IR7, IR6X
X 0  0  0  0  0   0  0  0  0  0  1  170  ; 140 8c ; IR76 00; goto 170X
X;X
X; pc changersX
X 0  0  5  0  0   0  0  0  1  0  0    0  ; 141 8d ; hold <- FLAGSX
X 0  0 10  0  0   4  8  0  0  0  0    4  ; 142 8e ; C <- hold & 00000100X
X 0  0  0  0  0   0  0  0  0  0  5  144  ; 143 8f ; test IR5, IR4X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 144 90 ; goto 8; neverX
X 0  0  0  0  0   0  0  0  0  0  1  162  ; 145 91 ; goto 162X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 146 92 ; goto 8; neverX
X;X
X; branchingX
X 0  0  0  0  0   0  0  0  0  0  4  148  ; 147 93 ; test IR3, IR2X
X;X
X; BR (0111 00aa) - branch alwaysX
X 0  0  7  0  0   1  2  0  0  0  1    8  ; 148 94 ; PC <- B; goto 8 X
X;X
X 0  0  0  0  0   0  0  0  0  0  1  154  ; 149 95 ; IR32 01; goto 154X
X 0  0  0  0  0   0  0  0  0  0  1  158  ; 150 96 ; IR32 10; goto 158X
X;X
X; BNEQ (0111 11aa) - branch if not zero (Z bit = 0)X
X 0  0  8  0  0   1  0  0  0  2  2  152  ; 151 97 ; C; test ZBIT (inverse)X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 152 98 ; 1; goto 8X
X 0  0  7  0  0   1  2  0  0  0  1    8  ; 153 99 ; 0; PC <- B; goto 8 X
X;X
X; BEQ (0111 01aa) - branch if zero (Z bit = 1)X
X 0  0  8  0  0   1  0  0  0  2  2  156  ; 154 9a ; C; test ZBIT (inverse)X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 155 9b ; nopX
X 0  0  7  0  0   1  2  0  0  0  1    8  ; 156 9c ; 1; PC <- B; goto 8 X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 157 9d ; 0; goto 8X
X;X
X; BLSS (0111 10aa) - branch if negative (N bit = 1) X
X 0  0 10  0  0   4  8  0  0  0  0    8  ; 158 9e ; C <- hold & 00001000X
X 0  0  8  0  0   1  0  0  0  2  2  160  ; 159 9f ; C ; test ZBITX
X 0  0  7  0  0   1  2  0  0  0  1    8  ; 160 a0 ; N 1; PC <- B; goto 8 X
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 161 a1 ; N 0; goto 8X
X;X
X; CALL (0101 00aa) - jump to subroutineX
X 0  0  3  0  0   2  3  0  0  0  0    0  ; 162 a2 ; not SPX
X 0  0  3  0  0   9  3  0  0  0  0    0  ; 163 a3 ; SP <- SP + 1X
X 0  0  3  0  0   2  3  0  0  0  0    0  ; 164 a4 ; not SPX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 165 a5 ; nopX
X 0  0  3  0  0   1 10  0  0  0  0    0  ; 166 a6 ; MAR <- SPX
X 1  0  2  0  0   1  9  0  0  0  0    0  ; 167 a7 ; MBR <- PC; WRITEX
X 1  0  7  0  0   1  2  0  0  0  0    0  ; 168 a8 ; PC <- B; WRITEX
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 169 a9 ; goto 8X
X;X
X; OpCodes that have IR7=0 and IR6=0X
X 0  0  0  0  0   0  0  0  0  0  5  172  ; 170 aa ; test IR5, IR4X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 171 ab ; nopX
X 0  0  0  0  0   0  0  0  0  0  1  185  ; 172 ac ; IR54 00; goto 185X
X 0  0  0  0  0   0  0  0  0  0  1  195  ; 173 ad ; IR54 01; goto 195X
X 0  0  0  0  0   0  0  0  0  0  1  207  ; 174 ae ; IR54 10; goto 207X
X;X
X; storingX
X 0  0  0  0  0   0  0  0  0  0  4  176  ; 175 af ; test IR3, IR2X
X 0  0  0  0  0   0  0  0  0  0  1  181  ; 176 b0 ; IR32 00; goto 181X
X;X
X; STX (0011 01aa) - store index registerX
X 0  0  7  0  0   1 10  0  0  0  0    0  ; 177 b1 ; MAR <- BX
X 1  0  6  0  0   1  9  0  0  0  0    0  ; 178 b2 ; MBR <- X; WRITEX
X 1  0  0  0  0   0  0  0  0  0  0    0  ; 179 b3 ; WRITEX
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 180 b4 ; goto 8X
X;X
X; STA (0011 00aa) - store accumulatorX
X 0  0  7  0  0   1 10  0  0  0  0    0  ; 181 b5 ; MAR <- BX
X 1  0  1  0  0   1  9  0  0  0  0    0  ; 182 b6 ; MBR <- ACC; WRITEX
X 1  0  0  0  0   0  0  0  0  0  0    0  ; 183 b7 ; WRITEX
X 0  0  0  0  0   0  0  0  0  0  1    8  ; 184 b8 ; goto 8X
X;X
X; math (add/subtract)X
X 0  0  0  0  0   0  0  0  0  0  4  188  ; 185 b9 ; test IR3, IR2X
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 186 ba ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 187 bb ; nopX
X 0  0  0  0  0   0  0  0  0  0  1  193  ; 188 bc ; IR32 00; goto 193X
X;X
X; SUB (0000 01aa) - subtract from accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 189 bd ; hold <- MBRX
X 0  0  1  0  0   2  1  0  0  0  0    0  ; 190 be ; not ACCX
X 0  0  1  0  0   7  1  0  0  0  0    0  ; 191 bf ; ACC <- ACC + holdX
X 0  0  1  0  0   2  1  1  0  0  1    8  ; 192 c0 ; not ACC; goto 8X
X;X
X; ADD (0000 00aa) - add to accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 193 c1 ; hold <- MBRX
X 0  0  1  0  0   7  1  1  0  0  1    8  ; 194 c2 ; ACC <- ACC+hold; goto 8X
X; X
X; logicX
X 0  0  0  0  0   0  0  0  0  0  4  196  ; 195 c3 ; test IR3, IR2X
X 0  0  0  0  0   0  0  0  0  0  1  202  ; 196 c4 ; IR32 00; goto 202X
X 0  0  0  0  0   0  0  0  0  0  1  200  ; 197 c5 ; IR32 01; goto 200X
X;X
X; AND (0001 10aa) - logical AND to accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 198 c6 ; hold <- MBRX
X 0  0  1  0  0   4  1  1  0  0  1  211  ; 199 c7 ; ACC <- ACC&hold; goto211X
X;X
X; XOR (0001 01aa) - logical XOR to accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 200 c8 ; hold <- MBRX
X 0  0  1  0  0   6  1  1  0  0  1  211  ; 201 c9 ; ACC <- ACC^hold; goto211X
X;X
X; OR (0001 00aa) - logical OR to accumulatorX
X 0  0  9  0  0   1  0  0  1  0  0    0  ; 202 ca ; hold <- MBRX
X 0  0  1  0  0   5  1  1  0  0  1  211  ; 203 cb ; ACC <- ACC|hold; goto211X
XX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 204 cc ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 205 cd ; nopX
X 0  0  0  0  0   0  0  0  0  0  0    0  ; 206 ce ; nopX
X;X
X; loadingX
X 0  0  0  0  0   0  0  0  0  0  4  208  ; 207 cf ; test IR3, IR2X
X;X
X; LDA (0010 00aa) - load accumulatorX
X 0  0  9  0  0   1  1  1  0  0  1  211  ; 208 d0 ; ACC <- MBR; goto 211 X
X;X
X; LDX (0010 01aa) - load index registerX
X 0  0  9  0  0   1  6  0  0  0  1    8  ; 209 d1 ; X <- MBR; goto 8X
X;X
X; LDS (0010 10aa) - load stack registerX
X 0  0  9  0  0   1  3  0  0  0  1    8  ; 210 d2 ; SP <- MBR; goto 8X
X;X
X; set bits 'VC' to zero in flags registerX
X 0  0 10  0  0   0  0  0  1  0  0  252  ; 211 d3 ; hold <- 11111100X
X 0  0  5  0  0   4  5  0  0  0  1    8  ; 212 d4 ; FLAGS<-hold&FLGS; goto 8X
X;X
X; set bit 'V' to zero in flags registerX
X 0  0  0  0  1  15  7  0  0  0  0    0  ; 213 d5 ; B <- CCX
X 0  0  7  0  0   0  0  0  1  0  0    0  ; 214 d6 ; hold <- BX
X 0  0  5  0  0   5  5  0  0  0  0    0  ; 215 d7 ; FLAGS <- hold | FLAGSX
X 0  0 10  0  0   0  0  0  1  0  0  253  ; 216 d8 ; hold <- 11111101X
X 0  0  5  0  0   4  5  0  0  0  1    8  ; 217 d9 ; FLAGS<-hold&FLGS; goto 8X
X;X
X; set bit 'C' to zero in flags registerX
X 0  0 10  0  0   0  0  0  1  0  0  254  ; 218 da ; hold <- 11111110X
X 0  0  5  0  0   4  5  0  0  0  1    8  ; 219 db ; FLAGS<-hold&FLGS; goto 8X
XX
X; That's All Folks!X
X.YEX
X.vsX
X.psX
X.inX
X.PFX
X.PE "Technical Guide"X
X.bpX
X.ST "5. Technical Guide"X
XThis final chapter is used for the understanding of the actualX
Xsource code. X
XA lot of times it is nice to be able to look at the source codeX
Xquickly and gather the needed information.X
XThere are projects that are available that are difficult to understandX
Xwithout going into an in depth search.X
XThis chapter will try to overcome that.X
X.PPX
X.SP "Source Modules"X
XHere is a list of the source modules that is currently beingX
Xdistributed and the purpose of each.X
X.PPX
X.TSX
Xcenter box tab (/);X
Xc c, l l.X
XModule/PurposeX
X_X
Xbrkpts.c/Breakpoint codeX
Xcorrect.c/Correction File codeX
Xdebug.c/Debugging CodeX
Xmain.c/Main interpreter codeX
Xmemory.c/CPU and main memory codeX
Xmisc.c/Common functionsX
Xstack.c/Stack functionsX
Xy_misc.c/Misc functions for compilerX
Xyampc.c/Initial spawn of HDL compileX
Xdebug.h/Debugger function definitionsX
Xmain.h/Main header file for interpreterX
Xmisc.h/Common header fileX
Xyampc.h/Main header file for compilerX
Xlex.l/lexical analyzerX
Xlalr.y/YACC file used in parsing HDLX
XMakefile/object creationX
Xhfile/Example of HDL programX
Xcmemory/Example of microcode programX
Xmemory/Example of assembly language programX
Xyampc.1/Man page for YAMPCX
Xyampc.doc/DocumentationX
Xtmac.ine/Troff macro package for docsX
Xlicense.gnu/Version 2 of GNU Public LicenseX
X.TEX
X.PPX
X.SP "Compiler"X
XThe \*Y compiler uses YACC and Lex explicitly to do all of theX
Xwork.X
XThere isn't anything that is actually time dependent and X
Xmaintaining Lex and YACC is much easier.X
XThis also makes it much easier to add because Lex and YACCX
Xare known well enough and it would be easier than examiningX
XC source code.X
X.PPX
X.SP "Lex & YACC"X
XWhen working with Lex and YACC, it was made sure that thereX
Xwas nothing used that couldn't be used by different versionsX
Xother than the standard AT&T.X
XThis was particularly done so this project could be compiledX
Xusing Flex and Bison.X
XFlex and Bison are distributed by the Free Software Foundation.X
X.PPX
X.SP "Library"X
XThe library contains all of the code for the operation of theX
Xprocessor.X
XCertain machines when creating the library don't actuallyX
Xplace a table of contents into it.X
XThis may need to be done using the 'ranlib' or the 'ar -ts'X
Xcommands.X
X.PPX
X.SP "Stack"X
XAll expression math done in the HDL is using stack commands.X
XThe expression is broken up and placed onto the stack inX
XReverse Polish Notation (RPN).X
XThe reasoning is that it was a easy way to maintain completeX
Xcontrol over all math operations.X
XOtherwise it would be machine dependent and that would beX
Xpointless.X
X.PPX
XAnother consideration is that is was desired the ability toX
Xsupport many different word sized machines.X
XIf the processor intends on creating a 10 bit word machine,X
X\*Y is able to support it completely.X
X\*Y takes in account that the machine is 10 bit and all X
Xmath operations are done in 10 bit math.X
X.PPX
XAll math operations are in control.X
XIf a math operation is being done on a 5 bit word and a 6 bitX
Xword and placed into a 7 bit word.X
XThe operation on the 5 bit and 6 bit will be done in 6 bit andX
Xmoved into the 7 bit word.X
X.PPX
X.SP "Interrupts"X
XInterrupts will probably be the least used function of theX
Xproduct.X
XIt was placed in as an after though because it was interestingX
Xfor myself during development time.X
XIn a normal class scenario, there would be no needX
Xfor the interrupt support.X
XA student wouldn't really get that much more out of the X
Xclass project if interrupts were used.X
X.PPX
XInterrupts can occur every X period of time which can be setX
Xup by the HDL programmer or at run time.X
XWhen it is time for the interrupt to occur, the microengineX
Xis called with the subcycle set to the maximum plus one.X
XThe microengine code can then determine that the inputX
Xis an interrupt and continue processing on that.X
XThe keyword 'Ireturn' is available for the programmer to returnX
Xfrom the microengine.X
XThis can be useful if the interrupt code is in the beginning ofX
Xthe engine and there is other code that shouldn't be executed.X
X.PPX
X.SP "Adding Commands"X
XAdding commands is pretty simple.X
XThere is a file called 'debug.h' which lists all of theX
Xcurrent commands available while in the interactive debugger.X
XIn that file, a structure is declared.X
X.PPX
X.ps 8X
X.in +.5iX
X.YSX
X/* structure containing the debug routines */X
Xstruct debug_cmds {X
X   char *word;       /* the word spelling */X
X   int matchnum;     /* number of characters neededX
X                      * to match */X
X   char *usage;      /* usage message if used improperly */X
X   char *help;       /* help message */X
X   int (*func) ( );  /* function pointer */X
XX
X};X
X.YEX
X.inX
X.psX
X.PPX
XEach function that is to be added needs to be placed into thisX
Xstructure.X
XWhen creating the function, take in account that it is expectedX
Xto do certain things.X
XThe single argument to the function is the command entry value.X
XThis is useful for when the command is misused.X
XAlso, there is a finite number of possible returns that should beX
Xused.X
XListed below are the possible return values.X
X.PPX
X.TSX
Xcenter tab(/);X
Xlw(1i) l, l l.X
XReturn/MeaningX
X_X
XP_CONT/Continue processing debugger commandsX
XP_GOON/Start executing code until some event occursX
XP_LEAVE/Leave the interactive debuggerX
X.TEX
X.PPX
X.SP "System Limitations"X
XOne of the limitations is that the desired architecture can not X
Xbe larger than 32 bits. X
XThis is cause all references to all variables is done longs.X
XWhen compiling a HDL program, \*Y will notify the user if inX
Xsuch an event does occur.X
X.PE "Appendix"X
X.bpX
X.ST "A. Reserved Words"X
XHere is a list of all of the reserved words used by the HardwareX
XDescription Language.X
X.PPX
X.PPX
X.TSX
Xcenter;X
Xl.X
XBEGINX
XENDX
XFORMATX
XINITX
XINTERRUPTX
XMEMORYX
XMICROENGINEX
XPARTSX
XSUBCYCLEX
XVARSX
XbreakX
XcaseX
XcpuX
XdefaultX
XelseX
XIreturnX
XifX
XinterruptX
XmemX
XsubcycleX
XswitchX
X.TEX
X.bpX
X.ST "B. Debugger Command Summary"X
XThis section contains a synopsis of the commands available in the X
Xdebugger option of \*Y.X
X.PPX
X.SP "Breakpoint"X
XBreakpoints allow the user to stop at a microcode instructionX
Xand return to the debugger.X
XThis allows the user to examine the operation of the microcode toX
Xsee if it is performing properly.X
XBreakpoints are set to a particular microcode address and theX
Xdebugger will notify the user when the breakpoint has been reached.X
XThere can be up to 10 breakpoints set.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xbreakpoint [mpc]/breakpoint 8X
Xb [mpc]/b 250X
X.TEX
X.PPX
X.PPX
X.SP "Calculator"X
XThe calculator command allows the user to do simple arithmeticX
Xoperations in Reverse Polish Notation (RPN).X
XRegisters and hexidecimal numbers can be used in the expression.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xcalculator [expression]/calculator 7 6 +X
X/c 9 6 4 * /X
X/c 9 pc + mpc =X
X/ (note: this actually changes mpc)X
X.TEX
X.PPX
X.PPX
X.SP "Delete"X
XThe delete command allows the user to remove a breakpoint fromX
Xthe list.X
XThe only argument is the mpc address of the breakpoint set.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xdelete [mpc]/delete 8X
Xde [mpc]/de 8X
X.TEX
X.PPX
X.PPX
X.SP "Display"X
XDisplay shows the contents of the registers, cpu or main memory.X
XTo display the registers, "display regs" would suffice.X
XWhen displaying memory of some sort, it is necessary to specifyX
Xa range of locations.X
XThis range can be a single or multiple locations.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xdisplay regs/display regsX
X/d regsX
Xdisplay mem [integer]/display mem 65X
Xdisplay mem [integer] - [integer]/display mem 65 - 80X
Xdisplay cpu [integer]/display cpu 65X
Xdisplay cpu [integer] - [integer]/display cpu 65 - 80X
X.TEX
X.bpX
X.SP "Exit, Quit"X
XThese sinonmous commands give the ability to the user to leaveX
Xthe program.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xexit/exitX
X/eX
Xquit/quitX
X/qX
X.TEX
X.PPX
X.PPX
X.SP "Help"X
XThe debugger command set is quickly available on line by usingX
Xthe help command.X
XHelp will give a quick reference to all of the commands that theX
Xuser can use with their appropriate syntax.X
X.PPX
X.PPX
X.SP "Interrupts"X
XThe interrupt command allows the user to list, set or X
Xunset interrupts.X
XThe interrupt command can take up to two arguments.X
XIf there are no arguments, all interrupts vectors are displayed.X
XWith one argument, the interrupt vector is removed from the  list.X
XIf there are two arguments, the interrupt becomes active every X
XX number of cycles where X is the second argument.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xinterrupt/iX
Xinterrupt <#>/i 6X
Xinterrupt <#> <#>/i 6 50X
X.TEX
X.PPX
X.SP "List"X
XList all breakpoints set.X
XThis command doesn't take any arguments.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xlist/listX
X/lX
X.TEX
X.PPX
X.SP "Reset"X
XReset sets all the elements of the processor to their originalX
Xvalues, ie. the values at the start of the simulation.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xreset/resetX
X/reX
X.TEX
X.PPX
X.SP "Run"X
XRun causes the debugger to initiate a simulation of the processor.X
XRun with no arguments runs the processor until the processor isX
Xhalted by breakpoint or finishing.X
XIf there is an argument, the processor will execute that number ofX
Xcycles before returning to the debugging prompt.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xrun/runX
X/rX
Xrun <#>/run 10X
X.TEX
X.PPX
X.SP "Set"X
XA valid part of the architecture is set to some value, number.X
XThe number is in hexidecimal notation.X
XThe set command is possible of setting either a register orX
Xthe main memory.X
X.PPX
X.TSX
Xcenter tab (/);X
Xlw(2i) lw(2i), l l.X
X\fISyntax/Examples\fPX
Xset [regs|mem] [#] <#>/set regs mpc 20X
X/set mem 16 40X
X.TEX
X.PPX
X.SP "Trace"X
XTrace sets the output of the simulated running of the processorX
Xaccording to:X
X.in +1iX
X.PPX
Xtrace off - no outputX
X.PPX
Xtrace on - output consists of a heading containing the control fieldX
Xname and values for the current contents of the microinstructionX
Xregister; each part of the architecture is listed with its X
Xcontents in hexidecimal.X
X.PPX
Xtrace header - output is identical to the trace on except the contentsX
Xof the architecture parts are not displayed.X
X.inX
X.PPX
X.SP "Version"X
XThe version command displays to the user the current version of the X
X\*Y software package.X
X.bpX
X.ST "C. Miscellaneous Notes"X
XThis project is currently being used in the undergraduate courseX
Xat Rochester Institute of Technology.X
X.PPX
X.PPX
X.SP "Future Developments"X
XThere are some changes that can be made that might make this projectX
Xwork better.X
X.PPX
XIt may be nice to have window support (X ?) for this so the dubuggerX
Xcould be icon driven.X
XAlso, a map showing the execution path visually would be really nice.X
X.PPX
XThere is internal support for subcycles but there currently isn't theX
Xability to debug by subcycle.X
XIn the future, this could be a nice addition.X
X.PPX
XThe correction file is sufficient but instead of correcting by X
Xfetch cycle, correct via the memory address.X
XThis would allow more freedom with the microcode.X
X.PPX
X.PPX
X.SP "Hacker Ethics"X
X"Hackers", by Steven Levy.X
X.PPX
XAccess to computers - and anything which might teach you somethingX
Xabout the way the world workds - should be unlimited and total.X
XAlways yield to the Hands On Imperative!X
X.PPX
XAll Information should be free.X
X.PPX
XMistrust Authority - Promote Decentralization.X
X.PPX
XHacker's should be judged by their hacking, not bogusX
Xcriteria such as degrees, age, race or position.X
X.PPX
XYou can create art and beauty on a computer.X
X.PPX
X.PPX
X.SP "YAMPC"X
XAs a side note, \*Y stands for:X
X.PPX
X.in +1iX
XYet Another Micro Program CompilerX
X.inX
Zaphod for prez
exit 0