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- From: gumby@Cygnus.COM (David V. Henkel-Wallace)
- Subject: Specialized hardware ain't what it's cracked up to be (was: New RISC chip / IMS 3250)
- In-Reply-To: bruce@pages.com's message of 17 Nov 92 20:59:59 GMT
- References: <1992Nov15.192329.324@pages.com> <1992Nov17.205959.8187@pages.com>
- Sender: news@nas.nasa.gov (News Administrator)
- Organization: Cygnus Support, Palo Alto, California
- Date: 23 Nov 92 02:17:02
- Message-ID: <GUMBY.92Nov23021702@Cygnus.COM>
- Lines: 18
-
- Date: 17 Nov 92 20:59:59 GMT
- From: bruce@pages.com (Bruce Henderson)
-
- What if an objective-C message pass (a somewhat computationally
- expensive thing) was a processor level thing, and say happened in
- 3 clocks?
-
- Unfortunately this doesn't turn out to be as big a win as you think.
- Basically, smarter cacheing and optimization of certain lookup cases
- can get you more than hashing hardware. For instance, the
- memoization-dispatch scheme in PCL turned out to be faster than a
- dispatch using lookup hardware (on the lisp machine). Ultimately this
- boils down to the RISC vs CISC debate again.
-
- There are other reasons for using a writable control store, and you
- touch on them in your message. But many of the interesting
- optimizations one can imagine turn out not to be the big win one
- imagines at first. Too bad, eh?
-