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- Newsgroups: comp.sys.intel
- Path: sparky!uunet!cs.utexas.edu!convex!constellation!a.cs.okstate.edu!yeoy
- From: yeoy@a.cs.okstate.edu (YEO YEK CHONG)
- Subject: RISC vs CISC
- Message-ID: <1992Nov23.204336.2883@a.cs.okstate.edu>
- Organization: Oklahoma State University, Computer Science, Stillwater
- Date: Mon, 23 Nov 92 20:43:36 GMT
- Lines: 28
-
- In article <DOCONNOR.92Nov20100231@potato.sedona.intel.com>, doconnor@sedona.intel.com (Dennis O'Connor) writes:
- >
- > mu@terapin.com (Mu Hong Lin) writes:
- > ] Will someone explain ( technially ) why RISC chips are so much faster
- > ] than CISC chips??
- >
- > RISC chips don't need to support obsolete mis-features from 10 years ago.
- > CISC chips generally do, because they are all old architectures.
- > --
- > Dennis O'Connor doconnor@sedona.intel.com
-
- >tmcconne@sedona
- > To be fair, that answer may fit a particular part, but has nothing to do with
- >the RISC/CISC question...........
- > In a more general sense, there is no clear winner in the RISC/CISC wars,
- >although RISC seems to be gaining the edge,based on announcements from the last
- >couple of years. ^^^^^^^^^^^^^^^^^^^^^^
-
- Although the initial idea was for RISC to have simple architecture,
- single clock cycle instruction set and taking full advantage of piplining and
- other parallel processing techniques, some argue that delaying hardware
- architectural decisions to software engineers has made compiler writing and
- other software engineering issues much difficult tasks to accomplish. And thus
- there is also this sentiment that we are not getting anywhere with RISC.
- Comments and responses please.
-
- Yeo Yek Chong
-
-