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- From: moss@cs.cmu.edu (Eliot Moss)
- Subject: Re: DEC Alpha architecture issues
- In-Reply-To: woodacre@mips.com's message of 19 Nov 1992 16:14:59 GMT
- Message-ID: <MOSS.92Nov20101151@CRAFTY.cs.cmu.edu>
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- Organization: Dept of Comp and Info Sci, Univ of Mass (Amherst)
- References: <1992Nov18.210416.27212@nntpd.lkg.dec.com>
- <lgnfc3INNqnt@spim.mti.sgi.com>
- Date: Fri, 20 Nov 1992 15:11:51 GMT
- Lines: 28
-
- >>>>> On 19 Nov 1992 16:14:59 GMT, woodacre@mips.com (Michael Woodacre) said:
-
- > PALcode allows for the implementation of uniprocessor-atomic
- > "instructions" which are actually a sequence of Alpha instructions.
- > It allows the architecture to remain pure RISC and not compromise
- > performance to implement some complex instructions. This was very
- > useful in the port of VMS to Alpha.
-
- Michael> Can you explain how this is different from kernel code with interrupts
- Michael> disabled on any other risc processor? For instance, an R4000 can
- Michael> implement uniprocessor-atomic "instructions" which are sequences of
- Michael> MIPS instructions to implement complex functions by running code
- Michael> in kernel level with interrupts switched off.
-
- It's not really all that different. My understanding of the point of PAL code
- is that a collection of architecture implementation specific routines are
- provided in ROM, reducing implementation specificities of the kernel. It may
- also be the case that entering/exiting PAL code is a little faster than a
- usual syscall (but gives a more restricted execution environment).
- --
-
- J. Eliot B. Moss, Associate Professor Visiting Associate Professor
- Department of Computer Science School of Computer Science
- Lederle Graduate Research Center Carnegie Mellon University
- University of Massachusetts 5000 Forbes Avenue
- Amherst, MA 01003 Pittsburgh, PA 15213-3891
- (413) 545-4206, 545-1249 (fax) (412) 268-6767, 681-5739 (fax)
- Moss@cs.umass.edu Moss@cs.cmu.edu
-