NetNews Usenet Archive 1992 #27/NN_1992_27.iso/spool/comp/arch/10942

Internet Message Format | 1992-11-19 | 4.0 KB

Path: sparky!uunet!sun-barr!ames!agate!doc.ic.ac.uk!uknet!mucs!mshute
From: [e-mail] (Malcolm Shute)
Newsgroups: comp.arch
Subject: Re: 600 transistor CPU (was: MINIMUM instruction set)
Message-ID: <[e-mail]>
Date: 19 Nov 92 16:58:18 GMT
References: <[e-mail]> <[e-mail]> <[e-mail]>
Sender: [e-mail]
Organization: Dept Computer Science, University of Manchester, U.K.
Lines: 59

In article <[e-mail]> [e-mail] (Steve Ligett) writes:
>Somewhere I have a copy of an article (or two) titled
>"A design for a 16 bit processor using only 600 transistors"
>from Microelectronics Journal, Vol 15, Nr 3,
>copyright 1984 Benn Electronics Publications Ltd, London
>The machine has 4 instructions: three subtracts, and one bit clear.

In article <[e-mail]> [e-mail] (Eugene F. Styer) writes:
> I don't have that article any more (at least where I can find it), but I do
> remember it.  I decided that if his goal was a small CPU to watch over things,
> he would do better to have (say) 8 instructions and include load, store, etc.
No... that wasn't my primary goal... though in the paper I did suggest (rather
naively) two possible applications for the design:  (a) as a 'free' processor
which memory manufacturers could include on their memory chips as a test device
(for exercising the memory), which the customer could either use, or disable;
(b) as a simple design exercise for students or for a low gate-count technology
(as GaAs was at that time).  In reality, my *real* motivation for doing the design
was as a challenge... to see how low I could get the transistor count.

Unlike the OIC, I could have as many instructions as I liked.
My motivation for moving the PC out to memory was also subtly different.
For the OIC, the PC is at a 'magic' location in memory, the changing
of whose contents, causes a program jump.  For the NVDAC, though, memory location
zero contained an executable instruction, just like any other memory location.
It must be admitted, though, that the MAR did keep getting cleared
(so address zero was a privileged location, in that respect),
and the instruction was given a slightly different side effect when it was
addressed after one of these 'clear' signals (so, in effect, there were
5 instructions in the 2-bit instruction set).

> My conclusion was that the additional size of the processor (I estimated 1000-
> 1200 transistors) would be more than balanced by the smaller programs required
> (1/2 or smaller) for programs as small as a few hundred instructions.  If his
> goal was the fewest number of instructions, then other posts have indicated he
> has 3 too many instructions.  All in all, it was an attempt to be more practical
> than most of the minimal-instruction systems.
In fact, I have to disagree with you! :-)
Just like the OIC, a huge number of self-modifying instructions would have
to be executed to emulate even the simplest PDP-11 type of instruction.
Indeed, both the NVDAC and the version of the OIC reported by Bown,
needed of the order of 16 instructions to do simple ALU type operations
on memory arguments.

No.  My goal really was: to do it as a challenge.

In article <[e-mail]> [e-mail] (Charles Perkins) writes:
> How many transistors would it take to make a minimally sized 32-bit chip?
> Optimized for transistor count, not cycle speed, op-code simplicity, or
> speed of design.
If you mean exactly the same NVDAC processor, as in the MEJ, but twice as wide,
the answer is about 1200.
The processor was nearly all data path, with very little random control logic.

BTW, I was interested by your multiple mini-prolog-processor idea.
I used to be on a project to design a multiple mini-Lisp-processor machine.
I'd be interested in exchanging notes, if you like.
--

Malcolm SHUTE.         (The AM Mollusc:   v_@_ )        Disclaimer: all